mirror of
https://github.com/citra-emu/citra.git
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JitX64: Implement ADC_imm
This commit is contained in:
MerryMage
parent
5331b7c4a5
commit
a80f9d8a66
@ -9,46 +9,48 @@
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#include "common/assert.h"
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#include "common/common_types.h"
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#include "common/make_unique.h"
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#include "core/arm/decoder/decoder.h"
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namespace ArmDecoder {
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namespace Impl {
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template<typename T, size_t N, typename... Args>
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template<typename Function, size_t i, typename Container, typename... Args>
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struct Call {
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static void call(Visitor* v, T fn, u32* list, Args... args) {
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Call<T, N - 1, Args..., u32>::call(v, fn, ++list, args..., *list);
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FORCE_INLINE static void call(Visitor* v, Function fn, const Container& list, Args&&... args) {
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using ArgT = decltype(std::get<i-1>(list));
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Call<Function, i-1, Container, ArgT, Args...>::call(v, fn, list, std::get<i-1>(list), args...);
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}
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};
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template<typename T, typename... Args>
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struct Call<T, 0, Args...> {
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static void call(Visitor* v, T fn, u32* list, Args... args) {
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template<typename Function, typename Container, typename... Args>
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struct Call<Function, 0, Container, Args...> {
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FORCE_INLINE static void call(Visitor* v, Function fn, const Container& list, Args&&... args) {
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(v->*fn)(args...);
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}
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};
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template<size_t N, typename T>
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template<size_t N, typename Function>
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struct MatcherImpl : Matcher {
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std::array<u32, N> masks;
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std::array<size_t, N> shifts;
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T fn;
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Function fn;
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virtual void visit(Visitor *v, u32 inst) override {
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std::array<u32, N> values;
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for (int i = 0; i<N; i++) {
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for (int i = 0; i < N; i++) {
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values[i] = (inst & masks[i]) >> shifts[i];
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}
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Call<T, N>::call(v, fn, values.data());
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Call<Function, N, decltype(values)>::call(v, fn, values);
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}
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};
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}
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template<size_t N, typename T>
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static std::unique_ptr<Matcher> MakeMatcher(const char* const format, T fn) {
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template<size_t N, typename Function>
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static std::unique_ptr<Matcher> MakeMatcher(const char* const format, Function fn) {
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ASSERT(strlen(format) == 32);
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auto ret = new Impl::MatcherImpl<N, T>();
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auto ret = Common::make_unique<Impl::MatcherImpl<N, Function>>();
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ret->fn = fn;
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ret->masks.fill(0);
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ret->shifts.fill(0);
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@ -57,16 +59,18 @@ static std::unique_ptr<Matcher> MakeMatcher(const char* const format, T fn) {
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int j = -1;
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for (int i = 0; i < 32; i++) {
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const u32 bit = 1 << (31 - i);
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if (format[i] == '0') {
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ret->bit_mask |= 1 << (31 - i);
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ret->bit_mask |= bit;
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ch = 0;
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continue;
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} else if (format[i] == '1') {
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ret->bit_mask |= 1 << (31 - i);
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ret->expected |= 1 << (31 - i);
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ret->bit_mask |= bit;
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ret->expected |= bit;
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ch = 0;
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continue;
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} else if (format[i] == 'x') {
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} else if (format[i] == '-') {
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ch = 0;
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continue;
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}
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@ -75,7 +79,6 @@ static std::unique_ptr<Matcher> MakeMatcher(const char* const format, T fn) {
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ASSERT(format[i] != 'I');
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ASSERT(format[i] != 'l');
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ASSERT(format[i] != 'O');
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ASSERT(format[i] != 'i');
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if (format[i] != ch){
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j++;
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@ -83,20 +86,20 @@ static std::unique_ptr<Matcher> MakeMatcher(const char* const format, T fn) {
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ch = format[i];
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}
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ret->masks[j] |= 1 << (31 - i);
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ret->masks[j] |= bit;
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ret->shifts[j] = 31 - i;
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}
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ASSERT(j == N-1);
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return std::unique_ptr<Matcher>(ret);
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return ret;
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}
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static const std::array<Instruction, 246> arm_instruction_table = {{
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// Barrier instructions
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{ "DSB", MakeMatcher<0>("1111010101111111111100000100xxxx", &Visitor::DSB) },
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{ "DMB", MakeMatcher<0>("1111010101111111111100000101xxxx", &Visitor::DMB) },
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{ "ISB", MakeMatcher<0>("1111010101111111111100000110xxxx", &Visitor::ISB) },
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{ "DSB", MakeMatcher<0>("1111010101111111111100000100----", &Visitor::DSB) },
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{ "DMB", MakeMatcher<0>("1111010101111111111100000101----", &Visitor::DMB) },
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{ "ISB", MakeMatcher<0>("1111010101111111111100000110----", &Visitor::ISB) },
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// Branch instructions
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{ "BLX (immediate)", MakeMatcher<2>("1111101hvvvvvvvvvvvvvvvvvvvvvvvv", &Visitor::BLX_imm) },
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@ -107,20 +110,20 @@ static const std::array<Instruction, 246> arm_instruction_table = {{
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{ "BXJ", MakeMatcher<2>("cccc000100101111111111110010mmmm", &Visitor::BXJ) },
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// Coprocessor instructions
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{ "CDP2", MakeMatcher<0>("11111110xxxxxxxxxxxxxxxxxxx1xxxx", &Visitor::CDP) },
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{ "CDP", MakeMatcher<0>("xxxx1110xxxxxxxxxxxxxxxxxxx0xxxx", &Visitor::CDP) },
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{ "LDC2", MakeMatcher<0>("1111110xxxx1xxxxxxxxxxxxxxxxxxxx", &Visitor::LDC) },
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{ "LDC", MakeMatcher<0>("xxxx110xxxx1xxxxxxxxxxxxxxxxxxxx", &Visitor::LDC) },
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{ "MCR2", MakeMatcher<0>("xxxx1110xxx0xxxxxxxxxxxxxxx1xxxx", &Visitor::MCR) },
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{ "MCR", MakeMatcher<0>("xxxx1110xxx0xxxxxxxxxxxxxxx1xxxx", &Visitor::MCR) },
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{ "MCRR2", MakeMatcher<0>("111111000100xxxxxxxxxxxxxxxxxxxx", &Visitor::MCRR) },
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{ "MCRR", MakeMatcher<0>("xxxx11000100xxxxxxxxxxxxxxxxxxxx", &Visitor::MCRR) },
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{ "MRC2", MakeMatcher<0>("11111110xxx1xxxxxxxxxxxxxxx1xxxx", &Visitor::MRC) },
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{ "MRC", MakeMatcher<0>("xxxx1110xxx1xxxxxxxxxxxxxxx1xxxx", &Visitor::MRC) },
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{ "MRRC2", MakeMatcher<0>("111111000101xxxxxxxxxxxxxxxxxxxx", &Visitor::MRRC) },
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{ "MRRC", MakeMatcher<0>("xxxx11000101xxxxxxxxxxxxxxxxxxxx", &Visitor::MRRC) },
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{ "STC2", MakeMatcher<0>("1111110xxxx0xxxxxxxxxxxxxxxxxxxx", &Visitor::STC) },
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{ "STC", MakeMatcher<0>("xxxx110xxxx0xxxxxxxxxxxxxxxxxxxx", &Visitor::STC) },
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{ "CDP2", MakeMatcher<0>("11111110-------------------1----", &Visitor::CDP) },
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{ "CDP", MakeMatcher<0>("----1110-------------------0----", &Visitor::CDP) },
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{ "LDC2", MakeMatcher<0>("1111110----1--------------------", &Visitor::LDC) },
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{ "LDC", MakeMatcher<0>("----110----1--------------------", &Visitor::LDC) },
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{ "MCR2", MakeMatcher<0>("----1110---0---------------1----", &Visitor::MCR) },
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{ "MCR", MakeMatcher<0>("----1110---0---------------1----", &Visitor::MCR) },
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{ "MCRR2", MakeMatcher<0>("111111000100--------------------", &Visitor::MCRR) },
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{ "MCRR", MakeMatcher<0>("----11000100--------------------", &Visitor::MCRR) },
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{ "MRC2", MakeMatcher<0>("11111110---1---------------1----", &Visitor::MRC) },
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{ "MRC", MakeMatcher<0>("----1110---1---------------1----", &Visitor::MRC) },
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{ "MRRC2", MakeMatcher<0>("111111000101--------------------", &Visitor::MRRC) },
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{ "MRRC", MakeMatcher<0>("----11000101--------------------", &Visitor::MRRC) },
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{ "STC2", MakeMatcher<0>("1111110----0--------------------", &Visitor::STC) },
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{ "STC", MakeMatcher<0>("----110----0--------------------", &Visitor::STC) },
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// Data Processing instructions
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{ "ADC (imm)", MakeMatcher<6>("cccc0010101Snnnnddddrrrrvvvvvvvv", &Visitor::ADC_imm) },
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@ -173,223 +176,223 @@ static const std::array<Instruction, 246> arm_instruction_table = {{
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{ "TST (rsr)", MakeMatcher<5>("cccc00010001nnnn0000ssss0rr1mmmm", &Visitor::TST_rsr) },
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// Exception Generating instructions
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{ "BKPT", MakeMatcher<0>("xxxx00010010xxxxxxxxxxxx0111xxxx", &Visitor::BKPT) },
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{ "HVC", MakeMatcher<0>("xxxx00010100xxxxxxxxxxxx0111xxxx", &Visitor::HVC) },
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{ "SMC", MakeMatcher<0>("xxxx000101100000000000000111xxxx", &Visitor::SMC) },
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{ "SVC", MakeMatcher<0>("xxxx1111xxxxxxxxxxxxxxxxxxxxxxxx", &Visitor::SVC) },
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{ "UDF", MakeMatcher<0>("111001111111xxxxxxxxxxxx1111xxxx", &Visitor::UDF) },
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{ "BKPT", MakeMatcher<0>("----00010010------------0111----", &Visitor::BKPT) },
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{ "HVC", MakeMatcher<0>("----00010100------------0111----", &Visitor::HVC) },
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{ "SMC", MakeMatcher<0>("----000101100000000000000111----", &Visitor::SMC) },
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{ "SVC", MakeMatcher<0>("----1111------------------------", &Visitor::SVC) },
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{ "UDF", MakeMatcher<0>("111001111111------------1111----", &Visitor::UDF) },
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// Extension instructions
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{ "SXTB", MakeMatcher<0>("xxxx011010101111xxxxxx000111xxxx", &Visitor::SXTB) },
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{ "SXTB16", MakeMatcher<0>("xxxx011010001111xxxxxx000111xxxx", &Visitor::SXTB16) },
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{ "SXTH", MakeMatcher<0>("xxxx011010111111xxxxxx000111xxxx", &Visitor::SXTH) },
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{ "SXTAB", MakeMatcher<0>("xxxx01101010xxxxxxxxxx000111xxxx", &Visitor::SXTAB) },
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{ "SXTAB16", MakeMatcher<0>("xxxx01101000xxxxxxxxxx000111xxxx", &Visitor::SXTAB16) },
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{ "SXTAH", MakeMatcher<0>("xxxx01101011xxxxxxxxxx000111xxxx", &Visitor::SXTAH) },
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{ "UXTB", MakeMatcher<0>("xxxx011011101111xxxxxx000111xxxx", &Visitor::UXTB) },
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{ "UXTB16", MakeMatcher<0>("xxxx011011001111xxxxxx000111xxxx", &Visitor::UXTB16) },
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{ "UXTH", MakeMatcher<0>("xxxx011011111111xxxxxx000111xxxx", &Visitor::UXTH) },
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{ "UXTAB", MakeMatcher<0>("xxxx01101110xxxxxxxxxx000111xxxx", &Visitor::UXTAB) },
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{ "UXTAB16", MakeMatcher<0>("xxxx01101100xxxxxxxxxx000111xxxx", &Visitor::UXTAB16) },
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{ "UXTAH", MakeMatcher<0>("xxxx01101111xxxxxxxxxx000111xxxx", &Visitor::UXTAH) },
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{ "SXTB", MakeMatcher<0>("----011010101111------000111----", &Visitor::SXTB) },
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{ "SXTB16", MakeMatcher<0>("----011010001111------000111----", &Visitor::SXTB16) },
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{ "SXTH", MakeMatcher<0>("----011010111111------000111----", &Visitor::SXTH) },
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{ "SXTAB", MakeMatcher<0>("----01101010----------000111----", &Visitor::SXTAB) },
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{ "SXTAB16", MakeMatcher<0>("----01101000----------000111----", &Visitor::SXTAB16) },
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{ "SXTAH", MakeMatcher<0>("----01101011----------000111----", &Visitor::SXTAH) },
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{ "UXTB", MakeMatcher<0>("----011011101111------000111----", &Visitor::UXTB) },
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{ "UXTB16", MakeMatcher<0>("----011011001111------000111----", &Visitor::UXTB16) },
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{ "UXTH", MakeMatcher<0>("----011011111111------000111----", &Visitor::UXTH) },
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{ "UXTAB", MakeMatcher<0>("----01101110----------000111----", &Visitor::UXTAB) },
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{ "UXTAB16", MakeMatcher<0>("----01101100----------000111----", &Visitor::UXTAB16) },
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{ "UXTAH", MakeMatcher<0>("----01101111----------000111----", &Visitor::UXTAH) },
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// Hint instructions
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{ "DBG", MakeMatcher<0>("xxxx001100100000111100001111xxxx", &Visitor::DBG) },
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{ "PLD (imm)", MakeMatcher<0>("11110101x101xxxx1111xxxxxxxxxxxx", &Visitor::PLD) },
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{ "PLD (lit)", MakeMatcher<0>("11110101010111111111xxxxxxxxxxxx", &Visitor::PLD) },
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{ "PLD (reg)", MakeMatcher<0>("11110111x001xxxx1111xxxxxxx0xxxx", &Visitor::PLD) },
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{ "PLDW (imm)", MakeMatcher<0>("11110101x001xxxx1111xxxxxxxxxxxx", &Visitor::PLD) },
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{ "PLDW (reg)", MakeMatcher<0>("11110111x101xxxx1111xxxxxxx0xxxx", &Visitor::PLD) },
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{ "PLI (imm lit)", MakeMatcher<0>("11110100x101xxxx1111xxxxxxxxxxxx", &Visitor::PLI) },
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{ "PLI (reg)", MakeMatcher<0>("11110110x101xxxx1111xxxxxxx0xxxx", &Visitor::PLI) },
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{ "DBG", MakeMatcher<0>("----001100100000111100001111----", &Visitor::DBG) },
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{ "PLD (imm)", MakeMatcher<0>("11110101-101----1111------------", &Visitor::PLD) },
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{ "PLD (lit)", MakeMatcher<0>("11110101010111111111------------", &Visitor::PLD) },
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{ "PLD (reg)", MakeMatcher<0>("11110111-001----1111-------0----", &Visitor::PLD) },
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{ "PLDW (imm)", MakeMatcher<0>("11110101-001----1111------------", &Visitor::PLD) },
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{ "PLDW (reg)", MakeMatcher<0>("11110111-101----1111-------0----", &Visitor::PLD) },
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{ "PLI (imm lit)", MakeMatcher<0>("11110100-101----1111------------", &Visitor::PLI) },
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{ "PLI (reg)", MakeMatcher<0>("11110110-101----1111-------0----", &Visitor::PLI) },
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// Synchronization Primitive instructions
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{ "CLREX", MakeMatcher<0>("11110101011111111111000000011111", &Visitor::CLREX) },
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{ "LDREX", MakeMatcher<0>("xxxx00011001xxxxxxxx111110011111", &Visitor::LDREX) },
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{ "LDREXB", MakeMatcher<0>("xxxx00011101xxxxxxxx111110011111", &Visitor::LDREXB) },
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{ "LDREXD", MakeMatcher<0>("xxxx00011011xxxxxxxx111110011111", &Visitor::LDREXD) },
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{ "LDREXH", MakeMatcher<0>("xxxx00011111xxxxxxxx111110011111", &Visitor::LDREXH) },
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{ "STREX", MakeMatcher<0>("xxxx00011000xxxxxxxx11111001xxxx", &Visitor::STREX) },
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{ "STREXB", MakeMatcher<0>("xxxx00011100xxxxxxxx11111001xxxx", &Visitor::STREXB) },
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{ "STREXD", MakeMatcher<0>("xxxx00011010xxxxxxxx11111001xxxx", &Visitor::STREXD) },
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{ "STREXH", MakeMatcher<0>("xxxx00011110xxxxxxxx11111001xxxx", &Visitor::STREXH) },
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{ "SWP", MakeMatcher<0>("xxxx00010x00xxxxxxxx00001001xxxx", &Visitor::SWP) },
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{ "LDREX", MakeMatcher<0>("----00011001--------111110011111", &Visitor::LDREX) },
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{ "LDREXB", MakeMatcher<0>("----00011101--------111110011111", &Visitor::LDREXB) },
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{ "LDREXD", MakeMatcher<0>("----00011011--------111110011111", &Visitor::LDREXD) },
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{ "LDREXH", MakeMatcher<0>("----00011111--------111110011111", &Visitor::LDREXH) },
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{ "STREX", MakeMatcher<0>("----00011000--------11111001----", &Visitor::STREX) },
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{ "STREXB", MakeMatcher<0>("----00011100--------11111001----", &Visitor::STREXB) },
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{ "STREXD", MakeMatcher<0>("----00011010--------11111001----", &Visitor::STREXD) },
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{ "STREXH", MakeMatcher<0>("----00011110--------11111001----", &Visitor::STREXH) },
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{ "SWP", MakeMatcher<0>("----00010-00--------00001001----", &Visitor::SWP) },
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// Load/Store instructions
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{ "LDR (imm)", MakeMatcher<0>("xxxx010xx0x1xxxxxxxxxxxxxxxxxxxx", &Visitor::LDR_imm) },
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{ "LDR (reg)", MakeMatcher<0>("xxxx011xx0x1xxxxxxxxxxxxxxx0xxxx", &Visitor::LDR_reg) },
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{ "LDRB (imm)", MakeMatcher<0>("xxxx010xx1x1xxxxxxxxxxxxxxxxxxxx", &Visitor::LDRB_imm) },
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{ "LDRB (reg)", MakeMatcher<0>("xxxx011xx1x1xxxxxxxxxxxxxxx0xxxx", &Visitor::LDRB_reg) },
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{ "LDRBT (A1)", MakeMatcher<0>("xxxx0100x111xxxxxxxxxxxxxxxxxxxx", &Visitor::LDRBT) },
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{ "LDRBT (A2)", MakeMatcher<0>("xxxx0110x111xxxxxxxxxxxxxxx0xxxx", &Visitor::LDRBT) },
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{ "LDRD (imm)", MakeMatcher<0>("xxxx000xx1x0xxxxxxxxxxxx1101xxxx", &Visitor::LDRD_imm) },
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{ "LDRD (reg)", MakeMatcher<0>("xxxx000xx0x0xxxxxxxx00001101xxxx", &Visitor::LDRD_reg) },
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{ "LDRH (imm)", MakeMatcher<0>("xxxx000xx1x1xxxxxxxxxxxx1011xxxx", &Visitor::LDRH_imm) },
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{ "LDRH (reg)", MakeMatcher<0>("xxxx000xx0x1xxxxxxxx00001011xxxx", &Visitor::LDRH_reg) },
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{ "LDRHT (A1)", MakeMatcher<0>("xxxx0000x111xxxxxxxxxxxx1011xxxx", &Visitor::LDRHT) },
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{ "LDRHT (A2)", MakeMatcher<0>("xxxx0000x011xxxxxxxx00001011xxxx", &Visitor::LDRHT) },
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{ "LDRSB (imm)", MakeMatcher<0>("xxxx000xx1x1xxxxxxxxxxxx1101xxxx", &Visitor::LDRSB_imm) },
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{ "LDRSB (reg)", MakeMatcher<0>("xxxx000xx0x1xxxxxxxx00001101xxxx", &Visitor::LDRSB_reg) },
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{ "LDRSBT (A1)", MakeMatcher<0>("xxxx0000x111xxxxxxxxxxxx1101xxxx", &Visitor::LDRSBT) },
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{ "LDRSBT (A2)", MakeMatcher<0>("xxxx0000x011xxxxxxxx00001101xxxx", &Visitor::LDRSBT) },
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{ "LDRSH (imm)", MakeMatcher<0>("xxxx000xx1x1xxxxxxxxxxxx1111xxxx", &Visitor::LDRSH_imm) },
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{ "LDRSH (reg)", MakeMatcher<0>("xxxx000xx0x1xxxxxxxx00001111xxxx", &Visitor::LDRSH_reg) },
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{ "LDRSHT (A1)", MakeMatcher<0>("xxxx0000x111xxxxxxxxxxxx1111xxxx", &Visitor::LDRSHT) },
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{ "LDRSHT (A2)", MakeMatcher<0>("xxxx0000x011xxxxxxxx00001111xxxx", &Visitor::LDRSHT) },
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{ "LDRT (A1)", MakeMatcher<0>("xxxx0100x011xxxxxxxxxxxxxxxxxxxx", &Visitor::LDRT) },
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{ "LDRT (A2)", MakeMatcher<0>("xxxx0110x011xxxxxxxxxxxxxxx0xxxx", &Visitor::LDRT) },
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{ "STR (imm)", MakeMatcher<0>("xxxx010xx0x0xxxxxxxxxxxxxxxxxxxx", &Visitor::STR_imm) },
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{ "STR (reg)", MakeMatcher<0>("xxxx011xx0x0xxxxxxxxxxxxxxx0xxxx", &Visitor::STR_reg) },
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{ "STRB (imm)", MakeMatcher<0>("xxxx010xx1x0xxxxxxxxxxxxxxxxxxxx", &Visitor::STRB_imm) },
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{ "STRB (reg)", MakeMatcher<0>("xxxx011xx1x0xxxxxxxxxxxxxxx0xxxx", &Visitor::STRB_reg) },
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{ "STRBT (A1)", MakeMatcher<0>("xxxx0100x110xxxxxxxxxxxxxxxxxxxx", &Visitor::STRBT) },
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{ "STRBT (A2)", MakeMatcher<0>("xxxx0110x110xxxxxxxxxxxxxxx0xxxx", &Visitor::STRBT) },
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{ "STRD (imm)", MakeMatcher<0>("xxxx000xx1x0xxxxxxxxxxxx1111xxxx", &Visitor::STRD_imm) },
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{ "STRD (reg)", MakeMatcher<0>("xxxx000xx0x0xxxxxxxx00001111xxxx", &Visitor::STRD_reg) },
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{ "STRH (imm)", MakeMatcher<0>("xxxx000xx1x0xxxxxxxxxxxx1011xxxx", &Visitor::STRH_imm) },
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{ "STRH (reg)", MakeMatcher<0>("xxxx000xx0x0xxxxxxxx00001011xxxx", &Visitor::STRH_reg) },
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{ "STRHT (A1)", MakeMatcher<0>("xxxx0000x110xxxxxxxxxxxx1011xxxx", &Visitor::STRHT) },
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{ "STRHT (A2)", MakeMatcher<0>("xxxx0000x010xxxxxxxx00001011xxxx", &Visitor::STRHT) },
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{ "STRT (A1)", MakeMatcher<0>("xxxx0100x010xxxxxxxxxxxxxxxxxxxx", &Visitor::STRT) },
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{ "STRT (A2)", MakeMatcher<0>("xxxx0110x010xxxxxxxxxxxxxxx0xxxx", &Visitor::STRT) },
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{ "LDR (imm)", MakeMatcher<0>("----010--0-1--------------------", &Visitor::LDR_imm) },
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{ "LDR (reg)", MakeMatcher<0>("----011--0-1---------------0----", &Visitor::LDR_reg) },
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{ "LDRB (imm)", MakeMatcher<0>("----010--1-1--------------------", &Visitor::LDRB_imm) },
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{ "LDRB (reg)", MakeMatcher<0>("----011--1-1---------------0----", &Visitor::LDRB_reg) },
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{ "LDRBT (A1)", MakeMatcher<0>("----0100-111--------------------", &Visitor::LDRBT) },
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{ "LDRBT (A2)", MakeMatcher<0>("----0110-111---------------0----", &Visitor::LDRBT) },
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{ "LDRD (imm)", MakeMatcher<0>("----000--1-0------------1101----", &Visitor::LDRD_imm) },
|
||||
{ "LDRD (reg)", MakeMatcher<0>("----000--0-0--------00001101----", &Visitor::LDRD_reg) },
|
||||
{ "LDRH (imm)", MakeMatcher<0>("----000--1-1------------1011----", &Visitor::LDRH_imm) },
|
||||
{ "LDRH (reg)", MakeMatcher<0>("----000--0-1--------00001011----", &Visitor::LDRH_reg) },
|
||||
{ "LDRHT (A1)", MakeMatcher<0>("----0000-111------------1011----", &Visitor::LDRHT) },
|
||||
{ "LDRHT (A2)", MakeMatcher<0>("----0000-011--------00001011----", &Visitor::LDRHT) },
|
||||
{ "LDRSB (imm)", MakeMatcher<0>("----000--1-1------------1101----", &Visitor::LDRSB_imm) },
|
||||
{ "LDRSB (reg)", MakeMatcher<0>("----000--0-1--------00001101----", &Visitor::LDRSB_reg) },
|
||||
{ "LDRSBT (A1)", MakeMatcher<0>("----0000-111------------1101----", &Visitor::LDRSBT) },
|
||||
{ "LDRSBT (A2)", MakeMatcher<0>("----0000-011--------00001101----", &Visitor::LDRSBT) },
|
||||
{ "LDRSH (imm)", MakeMatcher<0>("----000--1-1------------1111----", &Visitor::LDRSH_imm) },
|
||||
{ "LDRSH (reg)", MakeMatcher<0>("----000--0-1--------00001111----", &Visitor::LDRSH_reg) },
|
||||
{ "LDRSHT (A1)", MakeMatcher<0>("----0000-111------------1111----", &Visitor::LDRSHT) },
|
||||
{ "LDRSHT (A2)", MakeMatcher<0>("----0000-011--------00001111----", &Visitor::LDRSHT) },
|
||||
{ "LDRT (A1)", MakeMatcher<0>("----0100-011--------------------", &Visitor::LDRT) },
|
||||
{ "LDRT (A2)", MakeMatcher<0>("----0110-011---------------0----", &Visitor::LDRT) },
|
||||
{ "STR (imm)", MakeMatcher<0>("----010--0-0--------------------", &Visitor::STR_imm) },
|
||||
{ "STR (reg)", MakeMatcher<0>("----011--0-0---------------0----", &Visitor::STR_reg) },
|
||||
{ "STRB (imm)", MakeMatcher<0>("----010--1-0--------------------", &Visitor::STRB_imm) },
|
||||
{ "STRB (reg)", MakeMatcher<0>("----011--1-0---------------0----", &Visitor::STRB_reg) },
|
||||
{ "STRBT (A1)", MakeMatcher<0>("----0100-110--------------------", &Visitor::STRBT) },
|
||||
{ "STRBT (A2)", MakeMatcher<0>("----0110-110---------------0----", &Visitor::STRBT) },
|
||||
{ "STRD (imm)", MakeMatcher<0>("----000--1-0------------1111----", &Visitor::STRD_imm) },
|
||||
{ "STRD (reg)", MakeMatcher<0>("----000--0-0--------00001111----", &Visitor::STRD_reg) },
|
||||
{ "STRH (imm)", MakeMatcher<0>("----000--1-0------------1011----", &Visitor::STRH_imm) },
|
||||
{ "STRH (reg)", MakeMatcher<0>("----000--0-0--------00001011----", &Visitor::STRH_reg) },
|
||||
{ "STRHT (A1)", MakeMatcher<0>("----0000-110------------1011----", &Visitor::STRHT) },
|
||||
{ "STRHT (A2)", MakeMatcher<0>("----0000-010--------00001011----", &Visitor::STRHT) },
|
||||
{ "STRT (A1)", MakeMatcher<0>("----0100-010--------------------", &Visitor::STRT) },
|
||||
{ "STRT (A2)", MakeMatcher<0>("----0110-010---------------0----", &Visitor::STRT) },
|
||||
|
||||
// Load/Store Multiple instructions
|
||||
{ "LDMIA/LDMFD", MakeMatcher<0>("xxxx100010x1xxxxxxxxxxxxxxxxxxxx", &Visitor::LDM) },
|
||||
{ "LDMDA/LDMFA", MakeMatcher<0>("xxxx100000x1xxxxxxxxxxxxxxxxxxxx", &Visitor::LDM) },
|
||||
{ "LDMDB/LDMEA", MakeMatcher<0>("xxxx100100x1xxxxxxxxxxxxxxxxxxxx", &Visitor::LDM) },
|
||||
{ "LDMIB/LDMED", MakeMatcher<0>("xxxx100110x1xxxxxxxxxxxxxxxxxxxx", &Visitor::LDM) },
|
||||
{ "LDM (exc ret)", MakeMatcher<0>("xxxx100xx1x1xxxx1xxxxxxxxxxxxxxx", &Visitor::LDM) },
|
||||
{ "LDM (usr reg)", MakeMatcher<0>("xxxx100xx1x1xxxx0xxxxxxxxxxxxxxx", &Visitor::LDM) },
|
||||
{ "POP", MakeMatcher<0>("xxxx100010111101xxxxxxxxxxxxxxxx", &Visitor::LDM) },
|
||||
{ "POP", MakeMatcher<0>("xxxx010010011101xxxx000000000100", &Visitor::LDM) },
|
||||
{ "PUSH", MakeMatcher<0>("xxxx100100101101xxxxxxxxxxxxxxxx", &Visitor::STM) },
|
||||
{ "PUSH", MakeMatcher<0>("xxxx010100101101xxxx000000000100", &Visitor::STM) },
|
||||
{ "STMIA/STMEA", MakeMatcher<0>("xxxx100010x0xxxxxxxxxxxxxxxxxxxx", &Visitor::STM) },
|
||||
{ "STMDA/STMED", MakeMatcher<0>("xxxx100000x0xxxxxxxxxxxxxxxxxxxx", &Visitor::STM) },
|
||||
{ "STMDB/STMFD", MakeMatcher<0>("xxxx100100x0xxxxxxxxxxxxxxxxxxxx", &Visitor::STM) },
|
||||
{ "STMIB/STMFA", MakeMatcher<0>("xxxx100110x0xxxxxxxxxxxxxxxxxxxx", &Visitor::STM) },
|
||||
{ "STMIB (usr reg)", MakeMatcher<0>("xxxx100xx100xxxxxxxxxxxxxxxxxxxx", &Visitor::STM) },
|
||||
{ "LDMIA/LDMFD", MakeMatcher<0>("----100010-1--------------------", &Visitor::LDM) },
|
||||
{ "LDMDA/LDMFA", MakeMatcher<0>("----100000-1--------------------", &Visitor::LDM) },
|
||||
{ "LDMDB/LDMEA", MakeMatcher<0>("----100100-1--------------------", &Visitor::LDM) },
|
||||
{ "LDMIB/LDMED", MakeMatcher<0>("----100110-1--------------------", &Visitor::LDM) },
|
||||
{ "LDM (exc ret)", MakeMatcher<0>("----100--1-1----1---------------", &Visitor::LDM) },
|
||||
{ "LDM (usr reg)", MakeMatcher<0>("----100--1-1----0---------------", &Visitor::LDM) },
|
||||
{ "POP", MakeMatcher<0>("----100010111101----------------", &Visitor::LDM) },
|
||||
{ "POP", MakeMatcher<0>("----010010011101----000000000100", &Visitor::LDM) },
|
||||
{ "PUSH", MakeMatcher<0>("----100100101101----------------", &Visitor::STM) },
|
||||
{ "PUSH", MakeMatcher<0>("----010100101101----000000000100", &Visitor::STM) },
|
||||
{ "STMIA/STMEA", MakeMatcher<0>("----100010-0--------------------", &Visitor::STM) },
|
||||
{ "STMDA/STMED", MakeMatcher<0>("----100000-0--------------------", &Visitor::STM) },
|
||||
{ "STMDB/STMFD", MakeMatcher<0>("----100100-0--------------------", &Visitor::STM) },
|
||||
{ "STMIB/STMFA", MakeMatcher<0>("----100110-0--------------------", &Visitor::STM) },
|
||||
{ "STMIB (usr reg)", MakeMatcher<0>("----100--100--------------------", &Visitor::STM) },
|
||||
|
||||
// Miscellaneous instructions
|
||||
{ "CLZ", MakeMatcher<0>("xxxx000101101111xxxx11110001xxxx", &Visitor::CLZ) },
|
||||
{ "NOP", MakeMatcher<0>("xxxx0011001000001111000000000000", &Visitor::NOP) },
|
||||
{ "SEL", MakeMatcher<0>("xxxx01101000xxxxxxxx11111011xxxx", &Visitor::SEL) },
|
||||
{ "CLZ", MakeMatcher<0>("----000101101111----11110001----", &Visitor::CLZ) },
|
||||
{ "NOP", MakeMatcher<0>("----0011001000001111000000000000", &Visitor::NOP) },
|
||||
{ "SEL", MakeMatcher<0>("----01101000--------11111011----", &Visitor::SEL) },
|
||||
|
||||
// Unsigned Sum of Absolute Differences instructions
|
||||
{ "USAD8", MakeMatcher<0>("xxxx01111000xxxx1111xxxx0001xxxx", &Visitor::USAD8) },
|
||||
{ "USADA8", MakeMatcher<0>("xxxx01111000xxxxxxxxxxxx0001xxxx", &Visitor::USADA8) },
|
||||
{ "USAD8", MakeMatcher<0>("----01111000----1111----0001----", &Visitor::USAD8) },
|
||||
{ "USADA8", MakeMatcher<0>("----01111000------------0001----", &Visitor::USADA8) },
|
||||
|
||||
// Packing instructions
|
||||
{ "PKH", MakeMatcher<0>("xxxx01101000xxxxxxxxxxxxxx01xxxx", &Visitor::PKH) },
|
||||
{ "PKH", MakeMatcher<0>("----01101000--------------01----", &Visitor::PKH) },
|
||||
|
||||
// Reversal instructions
|
||||
{ "RBIT", MakeMatcher<0>("xxxx011011111111xxxx11110011xxxx", &Visitor::RBIT) },
|
||||
{ "REV", MakeMatcher<0>("xxxx011010111111xxxx11110011xxxx", &Visitor::REV) },
|
||||
{ "REV16", MakeMatcher<0>("xxxx011010111111xxxx11111011xxxx", &Visitor::REV16) },
|
||||
{ "REVSH", MakeMatcher<0>("xxxx011011111111xxxx11111011xxxx", &Visitor::REVSH) },
|
||||
{ "RBIT", MakeMatcher<0>("----011011111111----11110011----", &Visitor::RBIT) },
|
||||
{ "REV", MakeMatcher<0>("----011010111111----11110011----", &Visitor::REV) },
|
||||
{ "REV16", MakeMatcher<0>("----011010111111----11111011----", &Visitor::REV16) },
|
||||
{ "REVSH", MakeMatcher<0>("----011011111111----11111011----", &Visitor::REVSH) },
|
||||
|
||||
// Saturation instructions
|
||||
{ "SSAT", MakeMatcher<0>("xxxx0110101xxxxxxxxxxxxxxx01xxxx", &Visitor::SSAT) },
|
||||
{ "SSAT16", MakeMatcher<0>("xxxx01101010xxxxxxxx11110011xxxx", &Visitor::SSAT16) },
|
||||
{ "USAT", MakeMatcher<0>("xxxx0110111xxxxxxxxxxxxxxx01xxxx", &Visitor::USAT) },
|
||||
{ "USAT16", MakeMatcher<0>("xxxx01101110xxxxxxxx11110011xxxx", &Visitor::USAT16) },
|
||||
{ "SSAT", MakeMatcher<0>("----0110101---------------01----", &Visitor::SSAT) },
|
||||
{ "SSAT16", MakeMatcher<0>("----01101010--------11110011----", &Visitor::SSAT16) },
|
||||
{ "USAT", MakeMatcher<0>("----0110111---------------01----", &Visitor::USAT) },
|
||||
{ "USAT16", MakeMatcher<0>("----01101110--------11110011----", &Visitor::USAT16) },
|
||||
|
||||
// Multiply (Normal) instructions
|
||||
{ "MLA", MakeMatcher<0>("xxxx0000001xxxxxxxxxxxxx1001xxxx", &Visitor::MLA) },
|
||||
{ "MLS", MakeMatcher<0>("xxxx00000110xxxxxxxxxxxx1001xxxx", &Visitor::MLS) },
|
||||
{ "MUL", MakeMatcher<0>("xxxx0000000xxxxx0000xxxx1001xxxx", &Visitor::MUL) },
|
||||
{ "MLA", MakeMatcher<0>("----0000001-------------1001----", &Visitor::MLA) },
|
||||
{ "MLS", MakeMatcher<0>("----00000110------------1001----", &Visitor::MLS) },
|
||||
{ "MUL", MakeMatcher<0>("----0000000-----0000----1001----", &Visitor::MUL) },
|
||||
|
||||
// Multiply (Long) instructions
|
||||
{ "SMLAL", MakeMatcher<0>("xxxx0000111xxxxxxxxxxxxx1001xxxx", &Visitor::SMLAL) },
|
||||
{ "SMULL", MakeMatcher<0>("xxxx0000110xxxxxxxxxxxxx1001xxxx", &Visitor::SMULL) },
|
||||
{ "UMAAL", MakeMatcher<0>("xxxx00000100xxxxxxxxxxxx1001xxxx", &Visitor::UMAAL) },
|
||||
{ "UMLAL", MakeMatcher<0>("xxxx0000101xxxxxxxxxxxxx1001xxxx", &Visitor::UMLAL) },
|
||||
{ "UMULL", MakeMatcher<0>("xxxx0000100xxxxxxxxxxxxx1001xxxx", &Visitor::UMULL) },
|
||||
{ "SMLAL", MakeMatcher<0>("----0000111-------------1001----", &Visitor::SMLAL) },
|
||||
{ "SMULL", MakeMatcher<0>("----0000110-------------1001----", &Visitor::SMULL) },
|
||||
{ "UMAAL", MakeMatcher<0>("----00000100------------1001----", &Visitor::UMAAL) },
|
||||
{ "UMLAL", MakeMatcher<0>("----0000101-------------1001----", &Visitor::UMLAL) },
|
||||
{ "UMULL", MakeMatcher<0>("----0000100-------------1001----", &Visitor::UMULL) },
|
||||
|
||||
// Multiply (Halfword) instructions
|
||||
{ "SMLALXY", MakeMatcher<0>("xxxx00010100xxxxxxxxxxxx1xx0xxxx", &Visitor::SMLALxy) },
|
||||
{ "SMLAXY", MakeMatcher<0>("xxxx00010000xxxxxxxxxxxx1xx0xxxx", &Visitor::SMLAxy) },
|
||||
{ "SMULXY", MakeMatcher<0>("xxxx00010110xxxx0000xxxx1xx0xxxx", &Visitor::SMULxy) },
|
||||
{ "SMLALXY", MakeMatcher<0>("----00010100------------1--0----", &Visitor::SMLALxy) },
|
||||
{ "SMLAXY", MakeMatcher<0>("----00010000------------1--0----", &Visitor::SMLAxy) },
|
||||
{ "SMULXY", MakeMatcher<0>("----00010110----0000----1--0----", &Visitor::SMULxy) },
|
||||
|
||||
// Multiply (Word by Halfword) instructions
|
||||
{ "SMLAWY", MakeMatcher<0>("xxxx00010010xxxxxxxxxxxx1x00xxxx", &Visitor::SMLAWy) },
|
||||
{ "SMULWY", MakeMatcher<0>("xxxx00010010xxxx0000xxxx1x10xxxx", &Visitor::SMULWy) },
|
||||
{ "SMLAWY", MakeMatcher<0>("----00010010------------1-00----", &Visitor::SMLAWy) },
|
||||
{ "SMULWY", MakeMatcher<0>("----00010010----0000----1-10----", &Visitor::SMULWy) },
|
||||
|
||||
// Multiply (Most Significant Word) instructions
|
||||
{ "SMMUL", MakeMatcher<0>("xxxx01110101xxxx1111xxxx00x1xxxx", &Visitor::SMMUL) },
|
||||
{ "SMMLA", MakeMatcher<0>("xxxx01110101xxxxxxxxxxxx00x1xxxx", &Visitor::SMMLA) },
|
||||
{ "SMMLS", MakeMatcher<0>("xxxx01110101xxxxxxxxxxxx11x1xxxx", &Visitor::SMMLS) },
|
||||
{ "SMMUL", MakeMatcher<0>("----01110101----1111----00-1----", &Visitor::SMMUL) },
|
||||
{ "SMMLA", MakeMatcher<0>("----01110101------------00-1----", &Visitor::SMMLA) },
|
||||
{ "SMMLS", MakeMatcher<0>("----01110101------------11-1----", &Visitor::SMMLS) },
|
||||
|
||||
// Multiply (Dual) instructions
|
||||
{ "SMLAD", MakeMatcher<0>("xxxx01110000xxxxxxxxxxxx00x1xxxx", &Visitor::SMLAD) },
|
||||
{ "SMLALD", MakeMatcher<0>("xxxx01110100xxxxxxxxxxxx00x1xxxx", &Visitor::SMLALD) },
|
||||
{ "SMLSD", MakeMatcher<0>("xxxx01110000xxxxxxxxxxxx01x1xxxx", &Visitor::SMLSD) },
|
||||
{ "SMLSLD", MakeMatcher<0>("xxxx01110100xxxxxxxxxxxx01x1xxxx", &Visitor::SMLSLD) },
|
||||
{ "SMUAD", MakeMatcher<0>("xxxx01110000xxxx1111xxxx00x1xxxx", &Visitor::SMUAD) },
|
||||
{ "SMUSD", MakeMatcher<0>("xxxx01110000xxxx1111xxxx01x1xxxx", &Visitor::SMUSD) },
|
||||
{ "SMLAD", MakeMatcher<0>("----01110000------------00-1----", &Visitor::SMLAD) },
|
||||
{ "SMLALD", MakeMatcher<0>("----01110100------------00-1----", &Visitor::SMLALD) },
|
||||
{ "SMLSD", MakeMatcher<0>("----01110000------------01-1----", &Visitor::SMLSD) },
|
||||
{ "SMLSLD", MakeMatcher<0>("----01110100------------01-1----", &Visitor::SMLSLD) },
|
||||
{ "SMUAD", MakeMatcher<0>("----01110000----1111----00-1----", &Visitor::SMUAD) },
|
||||
{ "SMUSD", MakeMatcher<0>("----01110000----1111----01-1----", &Visitor::SMUSD) },
|
||||
|
||||
// Parallel Add/Subtract (Modulo) instructions
|
||||
{ "SADD8", MakeMatcher<0>("xxxx01100001xxxxxxxx11111001xxxx", &Visitor::SADD8) },
|
||||
{ "SADD16", MakeMatcher<0>("xxxx01100001xxxxxxxx11110001xxxx", &Visitor::SADD16) },
|
||||
{ "SASX", MakeMatcher<0>("xxxx01100001xxxxxxxx11110011xxxx", &Visitor::SASX) },
|
||||
{ "SSAX", MakeMatcher<0>("xxxx01100001xxxxxxxx11110101xxxx", &Visitor::SSAX) },
|
||||
{ "SSUB8", MakeMatcher<0>("xxxx01100001xxxxxxxx11111111xxxx", &Visitor::SSUB8) },
|
||||
{ "SSUB16", MakeMatcher<0>("xxxx01100001xxxxxxxx11110111xxxx", &Visitor::SSUB16) },
|
||||
{ "UADD8", MakeMatcher<0>("xxxx01100101xxxxxxxx11111001xxxx", &Visitor::UADD8) },
|
||||
{ "UADD16", MakeMatcher<0>("xxxx01100101xxxxxxxx11110001xxxx", &Visitor::UADD16) },
|
||||
{ "UASX", MakeMatcher<0>("xxxx01100101xxxxxxxx11110011xxxx", &Visitor::UASX) },
|
||||
{ "USAX", MakeMatcher<0>("xxxx01100101xxxxxxxx11110101xxxx", &Visitor::USAX) },
|
||||
{ "USUB8", MakeMatcher<0>("xxxx01100101xxxxxxxx11111111xxxx", &Visitor::USUB8) },
|
||||
{ "USUB16", MakeMatcher<0>("xxxx01100101xxxxxxxx11110111xxxx", &Visitor::USUB16) },
|
||||
{ "SADD8", MakeMatcher<0>("----01100001--------11111001----", &Visitor::SADD8) },
|
||||
{ "SADD16", MakeMatcher<0>("----01100001--------11110001----", &Visitor::SADD16) },
|
||||
{ "SASX", MakeMatcher<0>("----01100001--------11110011----", &Visitor::SASX) },
|
||||
{ "SSAX", MakeMatcher<0>("----01100001--------11110101----", &Visitor::SSAX) },
|
||||
{ "SSUB8", MakeMatcher<0>("----01100001--------11111111----", &Visitor::SSUB8) },
|
||||
{ "SSUB16", MakeMatcher<0>("----01100001--------11110111----", &Visitor::SSUB16) },
|
||||
{ "UADD8", MakeMatcher<0>("----01100101--------11111001----", &Visitor::UADD8) },
|
||||
{ "UADD16", MakeMatcher<0>("----01100101--------11110001----", &Visitor::UADD16) },
|
||||
{ "UASX", MakeMatcher<0>("----01100101--------11110011----", &Visitor::UASX) },
|
||||
{ "USAX", MakeMatcher<0>("----01100101--------11110101----", &Visitor::USAX) },
|
||||
{ "USUB8", MakeMatcher<0>("----01100101--------11111111----", &Visitor::USUB8) },
|
||||
{ "USUB16", MakeMatcher<0>("----01100101--------11110111----", &Visitor::USUB16) },
|
||||
|
||||
// Parallel Add/Subtract (Saturating) instructions
|
||||
{ "QADD8", MakeMatcher<0>("xxxx01100010xxxxxxxx11111001xxxx", &Visitor::QADD8) },
|
||||
{ "QADD16", MakeMatcher<0>("xxxx01100010xxxxxxxx11110001xxxx", &Visitor::QADD16) },
|
||||
{ "QASX", MakeMatcher<0>("xxxx01100010xxxxxxxx11110011xxxx", &Visitor::QASX) },
|
||||
{ "QSAX", MakeMatcher<0>("xxxx01100010xxxxxxxx11110101xxxx", &Visitor::QSAX) },
|
||||
{ "QSUB8", MakeMatcher<0>("xxxx01100010xxxxxxxx11111111xxxx", &Visitor::QSUB8) },
|
||||
{ "QSUB16", MakeMatcher<0>("xxxx01100010xxxxxxxx11110111xxxx", &Visitor::QSUB16) },
|
||||
{ "UQADD8", MakeMatcher<0>("xxxx01100110xxxxxxxx11111001xxxx", &Visitor::UQADD8) },
|
||||
{ "UQADD16", MakeMatcher<0>("xxxx01100110xxxxxxxx11110001xxxx", &Visitor::UQADD16) },
|
||||
{ "UQASX", MakeMatcher<0>("xxxx01100110xxxxxxxx11110011xxxx", &Visitor::UQASX) },
|
||||
{ "UQSAX", MakeMatcher<0>("xxxx01100110xxxxxxxx11110101xxxx", &Visitor::UQSAX) },
|
||||
{ "UQSUB8", MakeMatcher<0>("xxxx01100110xxxxxxxx11111111xxxx", &Visitor::UQSUB8) },
|
||||
{ "UQSUB16", MakeMatcher<0>("xxxx01100110xxxxxxxx11110111xxxx", &Visitor::UQSUB16) },
|
||||
{ "QADD8", MakeMatcher<0>("----01100010--------11111001----", &Visitor::QADD8) },
|
||||
{ "QADD16", MakeMatcher<0>("----01100010--------11110001----", &Visitor::QADD16) },
|
||||
{ "QASX", MakeMatcher<0>("----01100010--------11110011----", &Visitor::QASX) },
|
||||
{ "QSAX", MakeMatcher<0>("----01100010--------11110101----", &Visitor::QSAX) },
|
||||
{ "QSUB8", MakeMatcher<0>("----01100010--------11111111----", &Visitor::QSUB8) },
|
||||
{ "QSUB16", MakeMatcher<0>("----01100010--------11110111----", &Visitor::QSUB16) },
|
||||
{ "UQADD8", MakeMatcher<0>("----01100110--------11111001----", &Visitor::UQADD8) },
|
||||
{ "UQADD16", MakeMatcher<0>("----01100110--------11110001----", &Visitor::UQADD16) },
|
||||
{ "UQASX", MakeMatcher<0>("----01100110--------11110011----", &Visitor::UQASX) },
|
||||
{ "UQSAX", MakeMatcher<0>("----01100110--------11110101----", &Visitor::UQSAX) },
|
||||
{ "UQSUB8", MakeMatcher<0>("----01100110--------11111111----", &Visitor::UQSUB8) },
|
||||
{ "UQSUB16", MakeMatcher<0>("----01100110--------11110111----", &Visitor::UQSUB16) },
|
||||
|
||||
// Parallel Add/Subtract (Halving) instructions
|
||||
{ "SHADD8", MakeMatcher<0>("xxxx01100011xxxxxxxx11111001xxxx", &Visitor::SHADD8) },
|
||||
{ "SHADD16", MakeMatcher<0>("xxxx01100011xxxxxxxx11110001xxxx", &Visitor::SHADD16) },
|
||||
{ "SHASX", MakeMatcher<0>("xxxx01100011xxxxxxxx11110011xxxx", &Visitor::SHASX) },
|
||||
{ "SHSAX", MakeMatcher<0>("xxxx01100011xxxxxxxx11110101xxxx", &Visitor::SHSAX) },
|
||||
{ "SHSUB8", MakeMatcher<0>("xxxx01100011xxxxxxxx11111111xxxx", &Visitor::SHSUB8) },
|
||||
{ "SHSUB16", MakeMatcher<0>("xxxx01100011xxxxxxxx11110111xxxx", &Visitor::SHSUB16) },
|
||||
{ "UHADD8", MakeMatcher<0>("xxxx01100111xxxxxxxx11111001xxxx", &Visitor::UHADD8) },
|
||||
{ "UHADD16", MakeMatcher<0>("xxxx01100111xxxxxxxx11110001xxxx", &Visitor::UHADD16) },
|
||||
{ "UHASX", MakeMatcher<0>("xxxx01100111xxxxxxxx11110011xxxx", &Visitor::UHASX) },
|
||||
{ "UHSAX", MakeMatcher<0>("xxxx01100111xxxxxxxx11110101xxxx", &Visitor::UHSAX) },
|
||||
{ "UHSUB8", MakeMatcher<0>("xxxx01100111xxxxxxxx11111111xxxx", &Visitor::UHSUB8) },
|
||||
{ "UHSUB16", MakeMatcher<0>("xxxx01100111xxxxxxxx11110111xxxx", &Visitor::UHSUB16) },
|
||||
{ "SHADD8", MakeMatcher<0>("----01100011--------11111001----", &Visitor::SHADD8) },
|
||||
{ "SHADD16", MakeMatcher<0>("----01100011--------11110001----", &Visitor::SHADD16) },
|
||||
{ "SHASX", MakeMatcher<0>("----01100011--------11110011----", &Visitor::SHASX) },
|
||||
{ "SHSAX", MakeMatcher<0>("----01100011--------11110101----", &Visitor::SHSAX) },
|
||||
{ "SHSUB8", MakeMatcher<0>("----01100011--------11111111----", &Visitor::SHSUB8) },
|
||||
{ "SHSUB16", MakeMatcher<0>("----01100011--------11110111----", &Visitor::SHSUB16) },
|
||||
{ "UHADD8", MakeMatcher<0>("----01100111--------11111001----", &Visitor::UHADD8) },
|
||||
{ "UHADD16", MakeMatcher<0>("----01100111--------11110001----", &Visitor::UHADD16) },
|
||||
{ "UHASX", MakeMatcher<0>("----01100111--------11110011----", &Visitor::UHASX) },
|
||||
{ "UHSAX", MakeMatcher<0>("----01100111--------11110101----", &Visitor::UHSAX) },
|
||||
{ "UHSUB8", MakeMatcher<0>("----01100111--------11111111----", &Visitor::UHSUB8) },
|
||||
{ "UHSUB16", MakeMatcher<0>("----01100111--------11110111----", &Visitor::UHSUB16) },
|
||||
|
||||
// Saturated Add/Subtract instructions
|
||||
{ "QADD", MakeMatcher<0>("xxxx00010000xxxxxxxx00000101xxxx", &Visitor::QADD) },
|
||||
{ "QSUB", MakeMatcher<0>("xxxx00010010xxxxxxxx00000101xxxx", &Visitor::QSUB) },
|
||||
{ "QDADD", MakeMatcher<0>("xxxx00010100xxxxxxxx00000101xxxx", &Visitor::QDADD) },
|
||||
{ "QDSUB", MakeMatcher<0>("xxxx00010110xxxxxxxx00000101xxxx", &Visitor::QDSUB) },
|
||||
{ "QADD", MakeMatcher<0>("----00010000--------00000101----", &Visitor::QADD) },
|
||||
{ "QSUB", MakeMatcher<0>("----00010010--------00000101----", &Visitor::QSUB) },
|
||||
{ "QDADD", MakeMatcher<0>("----00010100--------00000101----", &Visitor::QDADD) },
|
||||
{ "QDSUB", MakeMatcher<0>("----00010110--------00000101----", &Visitor::QDSUB) },
|
||||
|
||||
// Status Register Access instructions
|
||||
{ "CPS", MakeMatcher<0>("xxxx00010000xxx00000000xxx0xxxxx", &Visitor::CPS) },
|
||||
{ "ERET", MakeMatcher<0>("xxxx0001011000000000000001101110", &Visitor::ERET) },
|
||||
{ "SETEND", MakeMatcher<0>("1111000100000001000000x000000000", &Visitor::SETEND) },
|
||||
{ "MRS", MakeMatcher<0>("xxxx000100001111xxxx000000000000", &Visitor::MRS) },
|
||||
{ "MRS (banked)", MakeMatcher<0>("xxxx00010x00xxxxxxxx001x00000000", &Visitor::MRS) },
|
||||
{ "MRS (system)", MakeMatcher<0>("xxxx00010x001111xxxx000000000000", &Visitor::MRS) },
|
||||
{ "MSR (imm)", MakeMatcher<0>("xxxx00110010xx001111xxxxxxxxxxxx", &Visitor::MSR) },
|
||||
{ "MSR (reg)", MakeMatcher<0>("xxxx00010010xx00111100000000xxxx", &Visitor::MSR) },
|
||||
{ "MSR (banked)", MakeMatcher<0>("xxxx00010x10xxxx1111001x0000xxxx", &Visitor::MSR) },
|
||||
{ "MSR (imm special)", MakeMatcher<0>("xxxx00110x10xxxx1111xxxxxxxxxxxx", &Visitor::MSR) },
|
||||
{ "MSR (reg special)", MakeMatcher<0>("xxxx00010x10xxxx111100000000xxxx", &Visitor::MSR) },
|
||||
{ "RFE", MakeMatcher<0>("xxxx0001101x0000xxxxxxxxx110xxxx", &Visitor::RFE) },
|
||||
{ "SRS", MakeMatcher<0>("0000011xx0x00000000000000001xxxx", &Visitor::SRS) },
|
||||
{ "CPS", MakeMatcher<0>("----00010000---00000000---0-----", &Visitor::CPS) },
|
||||
{ "ERET", MakeMatcher<0>("----0001011000000000000001101110", &Visitor::ERET) },
|
||||
{ "SETEND", MakeMatcher<0>("1111000100000001000000-000000000", &Visitor::SETEND) },
|
||||
{ "MRS", MakeMatcher<0>("----000100001111----000000000000", &Visitor::MRS) },
|
||||
{ "MRS (banked)", MakeMatcher<0>("----00010-00--------001-00000000", &Visitor::MRS) },
|
||||
{ "MRS (system)", MakeMatcher<0>("----00010-001111----000000000000", &Visitor::MRS) },
|
||||
{ "MSR (imm)", MakeMatcher<0>("----00110010--001111------------", &Visitor::MSR) },
|
||||
{ "MSR (reg)", MakeMatcher<0>("----00010010--00111100000000----", &Visitor::MSR) },
|
||||
{ "MSR (banked)", MakeMatcher<0>("----00010-10----1111001-0000----", &Visitor::MSR) },
|
||||
{ "MSR (imm special)", MakeMatcher<0>("----00110-10----1111------------", &Visitor::MSR) },
|
||||
{ "MSR (reg special)", MakeMatcher<0>("----00010-10----111100000000----", &Visitor::MSR) },
|
||||
{ "RFE", MakeMatcher<0>("----0001101-0000---------110----", &Visitor::RFE) },
|
||||
{ "SRS", MakeMatcher<0>("0000011--0-00000000000000001----", &Visitor::SRS) },
|
||||
}};
|
||||
|
||||
const Instruction& DecodeArm(u32 i) {
|
||||
|
||||
@ -2,11 +2,79 @@
|
||||
// Licensed under GPLv2 or any later version
|
||||
// Refer to the license.txt file included.
|
||||
|
||||
#include "common/common_funcs.h"
|
||||
|
||||
#include "core/arm/jit_x64/jit_x64.h"
|
||||
|
||||
namespace JitX64 {
|
||||
|
||||
void JitX64::ADC_imm(Cond cond, bool S, ArmReg Rn, ArmReg Rd, int rotate, ArmImm8 imm8) { CompileInterpretInstruction(); }
|
||||
using namespace Gen;
|
||||
|
||||
void JitX64::ADC_imm(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, int rotate, ArmImm8 imm8) {
|
||||
cond_manager.CompileCond((ConditionCode)cond);
|
||||
|
||||
u32 immediate = _rotr(imm8, rotate * 2);
|
||||
|
||||
if (Rd_index == 15) {
|
||||
X64Reg Rd = reg_alloc.AllocAndLockTemp();
|
||||
reg_alloc.LockArm(Rn_index);
|
||||
|
||||
if (Rn_index == 15) {
|
||||
code->MOV(32, R(Rd), Imm32(GetReg15Value()));
|
||||
} else {
|
||||
code->MOV(32, R(Rd), reg_alloc.ArmR(Rd_index));
|
||||
}
|
||||
code->BT(32, MJitStateCFlag(), Imm8(0));
|
||||
code->ADC(32, R(Rd), Imm32(immediate));
|
||||
|
||||
reg_alloc.UnlockArm(Rn_index);
|
||||
|
||||
if (S)
|
||||
UNIMPLEMENTED();
|
||||
|
||||
code->MOV(32, MJitStateArmPC(), R(Rd));
|
||||
reg_alloc.UnlockTemp(Rd);
|
||||
current.arm_pc += GetInstSize();
|
||||
CompileReturnToDispatch();
|
||||
return;
|
||||
} else if (Rn_index == 15) {
|
||||
X64Reg Rd = reg_alloc.BindNoLoadAndLockArm(Rd_index);
|
||||
reg_alloc.MarkDirty(Rd_index);
|
||||
|
||||
code->MOV(32, R(Rd), Imm32(GetReg15Value()));
|
||||
code->BT(32, MJitStateCFlag(), Imm8(0));
|
||||
code->ADC(32, R(Rd), Imm32(immediate));
|
||||
|
||||
reg_alloc.UnlockArm(Rd_index);
|
||||
} else if (Rn_index == Rd_index) {
|
||||
X64Reg Rd = reg_alloc.BindAndLockArm(Rd_index);
|
||||
reg_alloc.MarkDirty(Rd_index);
|
||||
|
||||
code->BT(32, MJitStateCFlag(), Imm8(0));
|
||||
code->ADC(32, R(Rd), Imm32(immediate));
|
||||
|
||||
reg_alloc.UnlockArm(Rd_index);
|
||||
} else {
|
||||
X64Reg Rd = reg_alloc.BindNoLoadAndLockArm(Rd_index);
|
||||
reg_alloc.MarkDirty(Rd_index);
|
||||
reg_alloc.LockArm(Rn_index);
|
||||
|
||||
code->MOV(32, R(Rd), reg_alloc.ArmR(Rn_index));
|
||||
code->BT(32, MJitStateCFlag(), Imm8(0));
|
||||
code->ADC(32, R(Rd), Imm32(immediate));
|
||||
|
||||
reg_alloc.UnlockArm(Rd_index);
|
||||
reg_alloc.UnlockArm(Rn_index);
|
||||
}
|
||||
|
||||
if (S) {
|
||||
cond_manager.FlagsDirty();
|
||||
UpdateFlagsZVCN();
|
||||
}
|
||||
|
||||
current.arm_pc += GetInstSize();
|
||||
}
|
||||
|
||||
void JitX64::ADC_reg(Cond cond, bool S, ArmReg Rn, ArmReg Rd, ArmImm5 imm5, ShiftType shift, ArmReg Rm) { CompileInterpretInstruction(); }
|
||||
void JitX64::ADC_rsr(Cond cond, bool S, ArmReg Rn, ArmReg Rd, ArmReg Rs, ShiftType shift, ArmReg Rm) { CompileInterpretInstruction(); }
|
||||
void JitX64::ADD_imm(Cond cond, bool S, ArmReg Rn, ArmReg Rd, int rotate, ArmImm8 imm8) { CompileInterpretInstruction(); }
|
||||
|
||||
@ -66,12 +66,38 @@ CodePtr JitX64::Compile(u32 pc, bool TFlag, bool EFlag) {
|
||||
return bb;
|
||||
}
|
||||
|
||||
void JitX64::CompileUpdateCycles() {
|
||||
void JitX64::CompileUpdateCycles(bool reset_cycles) {
|
||||
// We're just taking one instruction == one cycle.
|
||||
if (instructions_compiled) {
|
||||
code->SUB(32, MJitStateCycleCount(), Imm32(instructions_compiled));
|
||||
}
|
||||
instructions_compiled = 0;
|
||||
if (reset_cycles) {
|
||||
instructions_compiled = 0;
|
||||
}
|
||||
}
|
||||
|
||||
void JitX64::CompileReturnToDispatch() {
|
||||
if (cond_manager.CurrentCond() == ConditionCode::AL) {
|
||||
reg_alloc.FlushEverything();
|
||||
CompileUpdateCycles();
|
||||
code->JMPptr(MJitStateHostReturnRIP());
|
||||
|
||||
stop_compilation = true;
|
||||
return;
|
||||
}
|
||||
|
||||
reg_alloc.FlushEverything();
|
||||
CompileUpdateCycles(false);
|
||||
code->JMPptr(MJitStateHostReturnRIP());
|
||||
|
||||
cond_manager.Always();
|
||||
CompileUpdateCycles(true);
|
||||
CompileJumpToBB(current.arm_pc);
|
||||
code->MOV(32, MJitStateArmPC(), Imm32(current.arm_pc));
|
||||
code->JMPptr(MJitStateHostReturnRIP());
|
||||
|
||||
stop_compilation = true;
|
||||
return;
|
||||
}
|
||||
|
||||
void JitX64::CompileJumpToBB(u32 new_pc) {
|
||||
|
||||
@ -65,7 +65,10 @@ private:
|
||||
void CompileSingleThumbInstruction();
|
||||
|
||||
/// Updates the cycle count in JitState and sets instructions_compiled to zero.
|
||||
void CompileUpdateCycles();
|
||||
void CompileUpdateCycles(bool reset_cycles = true);
|
||||
|
||||
/// Update MJitStateArmPC and current.TFlag before calling this function.
|
||||
void CompileReturnToDispatch();
|
||||
|
||||
/// If a basic_block starting at ARM pc is compiled -> these locations need to be patched
|
||||
std::unordered_map<LocationDescriptor, std::vector<CodePtr>, LocationDescriptorHash> patch_jmp_locations;
|
||||
@ -76,6 +79,7 @@ private:
|
||||
|
||||
private:
|
||||
/// Convenience functions
|
||||
|
||||
Gen::OpArg MJitStateCycleCount();
|
||||
Gen::OpArg MJitStateArmPC();
|
||||
Gen::OpArg MJitStateHostReturnRIP();
|
||||
@ -87,6 +91,25 @@ private:
|
||||
Gen::OpArg MJitStateExclusiveTag();
|
||||
Gen::OpArg MJitStateExclusiveState();
|
||||
|
||||
FORCE_INLINE u32 GetReg15Value() { return (current.arm_pc & ~0x1) + GetInstSize() * 2; }
|
||||
|
||||
FORCE_INLINE void UpdateFlagsZVCN() {
|
||||
code->SETcc(Gen::CC_Z, MJitStateZFlag());
|
||||
code->SETcc(Gen::CC_C, MJitStateCFlag());
|
||||
code->SETcc(Gen::CC_O, MJitStateVFlag());
|
||||
code->SETcc(Gen::CC_S, MJitStateNFlag());
|
||||
}
|
||||
|
||||
FORCE_INLINE void UpdateFlagsZVN() {
|
||||
code->SETcc(Gen::CC_Z, MJitStateZFlag());
|
||||
code->SETcc(Gen::CC_O, MJitStateVFlag());
|
||||
code->SETcc(Gen::CC_S, MJitStateNFlag());
|
||||
}
|
||||
|
||||
FORCE_INLINE void UpdateFlagsC_complement() {
|
||||
code->SETcc(Gen::CC_NC, MJitStateCFlag());
|
||||
}
|
||||
|
||||
private:
|
||||
struct CondManager {
|
||||
private:
|
||||
|
||||
@ -68,7 +68,7 @@ public:
|
||||
void UnlockArm(ArmReg arm_reg);
|
||||
/// Flush all ARM registers.
|
||||
void FlushAllArm();
|
||||
/// Marks an ARM register as dirty.
|
||||
/// Marks an ARM register as dirty. If you don't mark something as dirty it won't be flushed.
|
||||
void MarkDirty(ArmReg arm_reg);
|
||||
|
||||
/// Flush absolutely everything.
|
||||
|
||||
@ -152,7 +152,7 @@ TEST_CASE("Fuzz ARM data processing instructions", "[JitX64]") {
|
||||
Memory::Write32(i * 4, inst);
|
||||
}
|
||||
|
||||
Memory::Write32(NUM_INST * 4, 0b11100011001000000000111100000000);
|
||||
Memory::Write32(NUM_INST * 4, 0b0011001000001111000000000000);
|
||||
|
||||
interp.ExecuteInstructions(NUM_INST);
|
||||
jit.ExecuteInstructions(NUM_INST);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user