From a80f9d8a66eb6abe4ef28bc3215cb6db1c302daa Mon Sep 17 00:00:00 2001 From: MerryMage Date: Sun, 20 Mar 2016 19:20:41 +0000 Subject: [PATCH] JitX64: Implement ADC_imm --- src/core/arm/decoder/arm.cpp | 425 +++++++++--------- .../jit_x64/instructions/data_processing.cpp | 70 ++- src/core/arm/jit_x64/jit_x64.cpp | 30 +- src/core/arm/jit_x64/jit_x64.h | 25 +- src/core/arm/jit_x64/reg_alloc.h | 2 +- .../arm/jit_x64/fuzz_arm_data_processing.cpp | 2 +- 6 files changed, 337 insertions(+), 217 deletions(-) diff --git a/src/core/arm/decoder/arm.cpp b/src/core/arm/decoder/arm.cpp index a427f6dc5..9b48b4698 100644 --- a/src/core/arm/decoder/arm.cpp +++ b/src/core/arm/decoder/arm.cpp @@ -9,46 +9,48 @@ #include "common/assert.h" #include "common/common_types.h" +#include "common/make_unique.h" #include "core/arm/decoder/decoder.h" namespace ArmDecoder { namespace Impl { - template + template struct Call { - static void call(Visitor* v, T fn, u32* list, Args... args) { - Call::call(v, fn, ++list, args..., *list); + FORCE_INLINE static void call(Visitor* v, Function fn, const Container& list, Args&&... args) { + using ArgT = decltype(std::get(list)); + Call::call(v, fn, list, std::get(list), args...); } }; - template - struct Call { - static void call(Visitor* v, T fn, u32* list, Args... args) { + template + struct Call { + FORCE_INLINE static void call(Visitor* v, Function fn, const Container& list, Args&&... args) { (v->*fn)(args...); } }; - template + template struct MatcherImpl : Matcher { std::array masks; std::array shifts; - T fn; + Function fn; virtual void visit(Visitor *v, u32 inst) override { std::array values; - for (int i = 0; i> shifts[i]; } - Call::call(v, fn, values.data()); + Call::call(v, fn, values); } }; } -template -static std::unique_ptr MakeMatcher(const char* const format, T fn) { +template +static std::unique_ptr MakeMatcher(const char* const format, Function fn) { ASSERT(strlen(format) == 32); - auto ret = new Impl::MatcherImpl(); + auto ret = Common::make_unique>(); ret->fn = fn; ret->masks.fill(0); ret->shifts.fill(0); @@ -57,16 +59,18 @@ static std::unique_ptr MakeMatcher(const char* const format, T fn) { int j = -1; for (int i = 0; i < 32; i++) { + const u32 bit = 1 << (31 - i); + if (format[i] == '0') { - ret->bit_mask |= 1 << (31 - i); + ret->bit_mask |= bit; ch = 0; continue; } else if (format[i] == '1') { - ret->bit_mask |= 1 << (31 - i); - ret->expected |= 1 << (31 - i); + ret->bit_mask |= bit; + ret->expected |= bit; ch = 0; continue; - } else if (format[i] == 'x') { + } else if (format[i] == '-') { ch = 0; continue; } @@ -75,7 +79,6 @@ static std::unique_ptr MakeMatcher(const char* const format, T fn) { ASSERT(format[i] != 'I'); ASSERT(format[i] != 'l'); ASSERT(format[i] != 'O'); - ASSERT(format[i] != 'i'); if (format[i] != ch){ j++; @@ -83,20 +86,20 @@ static std::unique_ptr MakeMatcher(const char* const format, T fn) { ch = format[i]; } - ret->masks[j] |= 1 << (31 - i); + ret->masks[j] |= bit; ret->shifts[j] = 31 - i; } ASSERT(j == N-1); - return std::unique_ptr(ret); + return ret; } static const std::array arm_instruction_table = {{ // Barrier instructions - { "DSB", MakeMatcher<0>("1111010101111111111100000100xxxx", &Visitor::DSB) }, - { "DMB", MakeMatcher<0>("1111010101111111111100000101xxxx", &Visitor::DMB) }, - { "ISB", MakeMatcher<0>("1111010101111111111100000110xxxx", &Visitor::ISB) }, + { "DSB", MakeMatcher<0>("1111010101111111111100000100----", &Visitor::DSB) }, + { "DMB", MakeMatcher<0>("1111010101111111111100000101----", &Visitor::DMB) }, + { "ISB", MakeMatcher<0>("1111010101111111111100000110----", &Visitor::ISB) }, // Branch instructions { "BLX (immediate)", MakeMatcher<2>("1111101hvvvvvvvvvvvvvvvvvvvvvvvv", &Visitor::BLX_imm) }, @@ -107,20 +110,20 @@ static const std::array arm_instruction_table = {{ { "BXJ", MakeMatcher<2>("cccc000100101111111111110010mmmm", &Visitor::BXJ) }, // Coprocessor instructions - { "CDP2", MakeMatcher<0>("11111110xxxxxxxxxxxxxxxxxxx1xxxx", &Visitor::CDP) }, - { "CDP", MakeMatcher<0>("xxxx1110xxxxxxxxxxxxxxxxxxx0xxxx", &Visitor::CDP) }, - { "LDC2", MakeMatcher<0>("1111110xxxx1xxxxxxxxxxxxxxxxxxxx", &Visitor::LDC) }, - { "LDC", MakeMatcher<0>("xxxx110xxxx1xxxxxxxxxxxxxxxxxxxx", &Visitor::LDC) }, - { "MCR2", MakeMatcher<0>("xxxx1110xxx0xxxxxxxxxxxxxxx1xxxx", &Visitor::MCR) }, - { "MCR", MakeMatcher<0>("xxxx1110xxx0xxxxxxxxxxxxxxx1xxxx", &Visitor::MCR) }, - { "MCRR2", MakeMatcher<0>("111111000100xxxxxxxxxxxxxxxxxxxx", &Visitor::MCRR) }, - { "MCRR", MakeMatcher<0>("xxxx11000100xxxxxxxxxxxxxxxxxxxx", &Visitor::MCRR) }, - { "MRC2", MakeMatcher<0>("11111110xxx1xxxxxxxxxxxxxxx1xxxx", &Visitor::MRC) }, - { "MRC", MakeMatcher<0>("xxxx1110xxx1xxxxxxxxxxxxxxx1xxxx", &Visitor::MRC) }, - { "MRRC2", MakeMatcher<0>("111111000101xxxxxxxxxxxxxxxxxxxx", &Visitor::MRRC) }, - { "MRRC", MakeMatcher<0>("xxxx11000101xxxxxxxxxxxxxxxxxxxx", &Visitor::MRRC) }, - { "STC2", MakeMatcher<0>("1111110xxxx0xxxxxxxxxxxxxxxxxxxx", &Visitor::STC) }, - { "STC", MakeMatcher<0>("xxxx110xxxx0xxxxxxxxxxxxxxxxxxxx", &Visitor::STC) }, + { "CDP2", MakeMatcher<0>("11111110-------------------1----", &Visitor::CDP) }, + { "CDP", MakeMatcher<0>("----1110-------------------0----", &Visitor::CDP) }, + { "LDC2", MakeMatcher<0>("1111110----1--------------------", &Visitor::LDC) }, + { "LDC", MakeMatcher<0>("----110----1--------------------", &Visitor::LDC) }, + { "MCR2", MakeMatcher<0>("----1110---0---------------1----", &Visitor::MCR) }, + { "MCR", MakeMatcher<0>("----1110---0---------------1----", &Visitor::MCR) }, + { "MCRR2", MakeMatcher<0>("111111000100--------------------", &Visitor::MCRR) }, + { "MCRR", MakeMatcher<0>("----11000100--------------------", &Visitor::MCRR) }, + { "MRC2", MakeMatcher<0>("11111110---1---------------1----", &Visitor::MRC) }, + { "MRC", MakeMatcher<0>("----1110---1---------------1----", &Visitor::MRC) }, + { "MRRC2", MakeMatcher<0>("111111000101--------------------", &Visitor::MRRC) }, + { "MRRC", MakeMatcher<0>("----11000101--------------------", &Visitor::MRRC) }, + { "STC2", MakeMatcher<0>("1111110----0--------------------", &Visitor::STC) }, + { "STC", MakeMatcher<0>("----110----0--------------------", &Visitor::STC) }, // Data Processing instructions { "ADC (imm)", MakeMatcher<6>("cccc0010101Snnnnddddrrrrvvvvvvvv", &Visitor::ADC_imm) }, @@ -173,223 +176,223 @@ static const std::array arm_instruction_table = {{ { "TST (rsr)", MakeMatcher<5>("cccc00010001nnnn0000ssss0rr1mmmm", &Visitor::TST_rsr) }, // Exception Generating instructions - { "BKPT", MakeMatcher<0>("xxxx00010010xxxxxxxxxxxx0111xxxx", &Visitor::BKPT) }, - { "HVC", MakeMatcher<0>("xxxx00010100xxxxxxxxxxxx0111xxxx", &Visitor::HVC) }, - { "SMC", MakeMatcher<0>("xxxx000101100000000000000111xxxx", &Visitor::SMC) }, - { "SVC", MakeMatcher<0>("xxxx1111xxxxxxxxxxxxxxxxxxxxxxxx", &Visitor::SVC) }, - { "UDF", MakeMatcher<0>("111001111111xxxxxxxxxxxx1111xxxx", &Visitor::UDF) }, + { "BKPT", MakeMatcher<0>("----00010010------------0111----", &Visitor::BKPT) }, + { "HVC", MakeMatcher<0>("----00010100------------0111----", &Visitor::HVC) }, + { "SMC", MakeMatcher<0>("----000101100000000000000111----", &Visitor::SMC) }, + { "SVC", MakeMatcher<0>("----1111------------------------", &Visitor::SVC) }, + { "UDF", MakeMatcher<0>("111001111111------------1111----", &Visitor::UDF) }, // Extension instructions - { "SXTB", MakeMatcher<0>("xxxx011010101111xxxxxx000111xxxx", &Visitor::SXTB) }, - { "SXTB16", MakeMatcher<0>("xxxx011010001111xxxxxx000111xxxx", &Visitor::SXTB16) }, - { "SXTH", MakeMatcher<0>("xxxx011010111111xxxxxx000111xxxx", &Visitor::SXTH) }, - { "SXTAB", MakeMatcher<0>("xxxx01101010xxxxxxxxxx000111xxxx", &Visitor::SXTAB) }, - { "SXTAB16", MakeMatcher<0>("xxxx01101000xxxxxxxxxx000111xxxx", &Visitor::SXTAB16) }, - { "SXTAH", MakeMatcher<0>("xxxx01101011xxxxxxxxxx000111xxxx", &Visitor::SXTAH) }, - { "UXTB", MakeMatcher<0>("xxxx011011101111xxxxxx000111xxxx", &Visitor::UXTB) }, - { "UXTB16", MakeMatcher<0>("xxxx011011001111xxxxxx000111xxxx", &Visitor::UXTB16) }, - { "UXTH", MakeMatcher<0>("xxxx011011111111xxxxxx000111xxxx", &Visitor::UXTH) }, - { "UXTAB", MakeMatcher<0>("xxxx01101110xxxxxxxxxx000111xxxx", &Visitor::UXTAB) }, - { "UXTAB16", MakeMatcher<0>("xxxx01101100xxxxxxxxxx000111xxxx", &Visitor::UXTAB16) }, - { "UXTAH", MakeMatcher<0>("xxxx01101111xxxxxxxxxx000111xxxx", &Visitor::UXTAH) }, + { "SXTB", MakeMatcher<0>("----011010101111------000111----", &Visitor::SXTB) }, + { "SXTB16", MakeMatcher<0>("----011010001111------000111----", &Visitor::SXTB16) }, + { "SXTH", MakeMatcher<0>("----011010111111------000111----", &Visitor::SXTH) }, + { "SXTAB", MakeMatcher<0>("----01101010----------000111----", &Visitor::SXTAB) }, + { "SXTAB16", MakeMatcher<0>("----01101000----------000111----", &Visitor::SXTAB16) }, + { "SXTAH", MakeMatcher<0>("----01101011----------000111----", &Visitor::SXTAH) }, + { "UXTB", MakeMatcher<0>("----011011101111------000111----", &Visitor::UXTB) }, + { "UXTB16", MakeMatcher<0>("----011011001111------000111----", &Visitor::UXTB16) }, + { "UXTH", MakeMatcher<0>("----011011111111------000111----", &Visitor::UXTH) }, + { "UXTAB", MakeMatcher<0>("----01101110----------000111----", &Visitor::UXTAB) }, + { "UXTAB16", MakeMatcher<0>("----01101100----------000111----", &Visitor::UXTAB16) }, + { "UXTAH", MakeMatcher<0>("----01101111----------000111----", &Visitor::UXTAH) }, // Hint instructions - { "DBG", MakeMatcher<0>("xxxx001100100000111100001111xxxx", &Visitor::DBG) }, - { "PLD (imm)", MakeMatcher<0>("11110101x101xxxx1111xxxxxxxxxxxx", &Visitor::PLD) }, - { "PLD (lit)", MakeMatcher<0>("11110101010111111111xxxxxxxxxxxx", &Visitor::PLD) }, - { "PLD (reg)", MakeMatcher<0>("11110111x001xxxx1111xxxxxxx0xxxx", &Visitor::PLD) }, - { "PLDW (imm)", MakeMatcher<0>("11110101x001xxxx1111xxxxxxxxxxxx", &Visitor::PLD) }, - { "PLDW (reg)", MakeMatcher<0>("11110111x101xxxx1111xxxxxxx0xxxx", &Visitor::PLD) }, - { "PLI (imm lit)", MakeMatcher<0>("11110100x101xxxx1111xxxxxxxxxxxx", &Visitor::PLI) }, - { "PLI (reg)", MakeMatcher<0>("11110110x101xxxx1111xxxxxxx0xxxx", &Visitor::PLI) }, + { "DBG", MakeMatcher<0>("----001100100000111100001111----", &Visitor::DBG) }, + { "PLD (imm)", MakeMatcher<0>("11110101-101----1111------------", &Visitor::PLD) }, + { "PLD (lit)", MakeMatcher<0>("11110101010111111111------------", &Visitor::PLD) }, + { "PLD (reg)", MakeMatcher<0>("11110111-001----1111-------0----", &Visitor::PLD) }, + { "PLDW (imm)", MakeMatcher<0>("11110101-001----1111------------", &Visitor::PLD) }, + { "PLDW (reg)", MakeMatcher<0>("11110111-101----1111-------0----", &Visitor::PLD) }, + { "PLI (imm lit)", MakeMatcher<0>("11110100-101----1111------------", &Visitor::PLI) }, + { "PLI (reg)", MakeMatcher<0>("11110110-101----1111-------0----", &Visitor::PLI) }, // Synchronization Primitive instructions { "CLREX", MakeMatcher<0>("11110101011111111111000000011111", &Visitor::CLREX) }, - { "LDREX", MakeMatcher<0>("xxxx00011001xxxxxxxx111110011111", &Visitor::LDREX) }, - { "LDREXB", MakeMatcher<0>("xxxx00011101xxxxxxxx111110011111", &Visitor::LDREXB) }, - { "LDREXD", MakeMatcher<0>("xxxx00011011xxxxxxxx111110011111", &Visitor::LDREXD) }, - { "LDREXH", MakeMatcher<0>("xxxx00011111xxxxxxxx111110011111", &Visitor::LDREXH) }, - { "STREX", MakeMatcher<0>("xxxx00011000xxxxxxxx11111001xxxx", &Visitor::STREX) }, - { "STREXB", MakeMatcher<0>("xxxx00011100xxxxxxxx11111001xxxx", &Visitor::STREXB) }, - { "STREXD", MakeMatcher<0>("xxxx00011010xxxxxxxx11111001xxxx", &Visitor::STREXD) }, - { "STREXH", MakeMatcher<0>("xxxx00011110xxxxxxxx11111001xxxx", &Visitor::STREXH) }, - { "SWP", MakeMatcher<0>("xxxx00010x00xxxxxxxx00001001xxxx", &Visitor::SWP) }, + { "LDREX", MakeMatcher<0>("----00011001--------111110011111", &Visitor::LDREX) }, + { "LDREXB", MakeMatcher<0>("----00011101--------111110011111", &Visitor::LDREXB) }, + { "LDREXD", MakeMatcher<0>("----00011011--------111110011111", &Visitor::LDREXD) }, + { "LDREXH", MakeMatcher<0>("----00011111--------111110011111", &Visitor::LDREXH) }, + { "STREX", MakeMatcher<0>("----00011000--------11111001----", &Visitor::STREX) }, + { "STREXB", MakeMatcher<0>("----00011100--------11111001----", &Visitor::STREXB) }, + { "STREXD", MakeMatcher<0>("----00011010--------11111001----", &Visitor::STREXD) }, + { "STREXH", MakeMatcher<0>("----00011110--------11111001----", &Visitor::STREXH) }, + { "SWP", MakeMatcher<0>("----00010-00--------00001001----", &Visitor::SWP) }, // Load/Store instructions - { "LDR (imm)", MakeMatcher<0>("xxxx010xx0x1xxxxxxxxxxxxxxxxxxxx", &Visitor::LDR_imm) }, - { "LDR (reg)", MakeMatcher<0>("xxxx011xx0x1xxxxxxxxxxxxxxx0xxxx", &Visitor::LDR_reg) }, - { "LDRB (imm)", MakeMatcher<0>("xxxx010xx1x1xxxxxxxxxxxxxxxxxxxx", &Visitor::LDRB_imm) }, - { "LDRB (reg)", MakeMatcher<0>("xxxx011xx1x1xxxxxxxxxxxxxxx0xxxx", &Visitor::LDRB_reg) }, - { "LDRBT (A1)", MakeMatcher<0>("xxxx0100x111xxxxxxxxxxxxxxxxxxxx", &Visitor::LDRBT) }, - { "LDRBT (A2)", MakeMatcher<0>("xxxx0110x111xxxxxxxxxxxxxxx0xxxx", &Visitor::LDRBT) }, - { "LDRD (imm)", MakeMatcher<0>("xxxx000xx1x0xxxxxxxxxxxx1101xxxx", &Visitor::LDRD_imm) }, - { "LDRD (reg)", MakeMatcher<0>("xxxx000xx0x0xxxxxxxx00001101xxxx", &Visitor::LDRD_reg) }, - { "LDRH (imm)", MakeMatcher<0>("xxxx000xx1x1xxxxxxxxxxxx1011xxxx", &Visitor::LDRH_imm) }, - { "LDRH (reg)", MakeMatcher<0>("xxxx000xx0x1xxxxxxxx00001011xxxx", &Visitor::LDRH_reg) }, - { "LDRHT (A1)", MakeMatcher<0>("xxxx0000x111xxxxxxxxxxxx1011xxxx", &Visitor::LDRHT) }, - { "LDRHT (A2)", MakeMatcher<0>("xxxx0000x011xxxxxxxx00001011xxxx", &Visitor::LDRHT) }, - { "LDRSB (imm)", MakeMatcher<0>("xxxx000xx1x1xxxxxxxxxxxx1101xxxx", &Visitor::LDRSB_imm) }, - { "LDRSB (reg)", MakeMatcher<0>("xxxx000xx0x1xxxxxxxx00001101xxxx", &Visitor::LDRSB_reg) }, - { "LDRSBT (A1)", MakeMatcher<0>("xxxx0000x111xxxxxxxxxxxx1101xxxx", &Visitor::LDRSBT) }, - { "LDRSBT (A2)", MakeMatcher<0>("xxxx0000x011xxxxxxxx00001101xxxx", &Visitor::LDRSBT) }, - { "LDRSH (imm)", MakeMatcher<0>("xxxx000xx1x1xxxxxxxxxxxx1111xxxx", &Visitor::LDRSH_imm) }, - { "LDRSH (reg)", MakeMatcher<0>("xxxx000xx0x1xxxxxxxx00001111xxxx", &Visitor::LDRSH_reg) }, - { "LDRSHT (A1)", MakeMatcher<0>("xxxx0000x111xxxxxxxxxxxx1111xxxx", &Visitor::LDRSHT) }, - { "LDRSHT (A2)", MakeMatcher<0>("xxxx0000x011xxxxxxxx00001111xxxx", &Visitor::LDRSHT) }, - { "LDRT (A1)", MakeMatcher<0>("xxxx0100x011xxxxxxxxxxxxxxxxxxxx", &Visitor::LDRT) }, - { "LDRT (A2)", MakeMatcher<0>("xxxx0110x011xxxxxxxxxxxxxxx0xxxx", &Visitor::LDRT) }, - { "STR (imm)", MakeMatcher<0>("xxxx010xx0x0xxxxxxxxxxxxxxxxxxxx", &Visitor::STR_imm) }, - { "STR (reg)", MakeMatcher<0>("xxxx011xx0x0xxxxxxxxxxxxxxx0xxxx", &Visitor::STR_reg) }, - { "STRB (imm)", MakeMatcher<0>("xxxx010xx1x0xxxxxxxxxxxxxxxxxxxx", &Visitor::STRB_imm) }, - { "STRB (reg)", MakeMatcher<0>("xxxx011xx1x0xxxxxxxxxxxxxxx0xxxx", &Visitor::STRB_reg) }, - { "STRBT (A1)", MakeMatcher<0>("xxxx0100x110xxxxxxxxxxxxxxxxxxxx", &Visitor::STRBT) }, - { "STRBT (A2)", MakeMatcher<0>("xxxx0110x110xxxxxxxxxxxxxxx0xxxx", &Visitor::STRBT) }, - { "STRD (imm)", MakeMatcher<0>("xxxx000xx1x0xxxxxxxxxxxx1111xxxx", &Visitor::STRD_imm) }, - { "STRD (reg)", MakeMatcher<0>("xxxx000xx0x0xxxxxxxx00001111xxxx", &Visitor::STRD_reg) }, - { "STRH (imm)", MakeMatcher<0>("xxxx000xx1x0xxxxxxxxxxxx1011xxxx", &Visitor::STRH_imm) }, - { "STRH (reg)", MakeMatcher<0>("xxxx000xx0x0xxxxxxxx00001011xxxx", &Visitor::STRH_reg) }, - { "STRHT (A1)", MakeMatcher<0>("xxxx0000x110xxxxxxxxxxxx1011xxxx", &Visitor::STRHT) }, - { "STRHT (A2)", MakeMatcher<0>("xxxx0000x010xxxxxxxx00001011xxxx", &Visitor::STRHT) }, - { "STRT (A1)", MakeMatcher<0>("xxxx0100x010xxxxxxxxxxxxxxxxxxxx", &Visitor::STRT) }, - { "STRT (A2)", MakeMatcher<0>("xxxx0110x010xxxxxxxxxxxxxxx0xxxx", &Visitor::STRT) }, + { "LDR (imm)", MakeMatcher<0>("----010--0-1--------------------", &Visitor::LDR_imm) }, + { "LDR (reg)", MakeMatcher<0>("----011--0-1---------------0----", &Visitor::LDR_reg) }, + { "LDRB (imm)", MakeMatcher<0>("----010--1-1--------------------", &Visitor::LDRB_imm) }, + { "LDRB (reg)", MakeMatcher<0>("----011--1-1---------------0----", &Visitor::LDRB_reg) }, + { "LDRBT (A1)", MakeMatcher<0>("----0100-111--------------------", &Visitor::LDRBT) }, + { "LDRBT (A2)", MakeMatcher<0>("----0110-111---------------0----", &Visitor::LDRBT) }, + { "LDRD (imm)", MakeMatcher<0>("----000--1-0------------1101----", &Visitor::LDRD_imm) }, + { "LDRD (reg)", MakeMatcher<0>("----000--0-0--------00001101----", &Visitor::LDRD_reg) }, + { "LDRH (imm)", MakeMatcher<0>("----000--1-1------------1011----", &Visitor::LDRH_imm) }, + { "LDRH (reg)", MakeMatcher<0>("----000--0-1--------00001011----", &Visitor::LDRH_reg) }, + { "LDRHT (A1)", MakeMatcher<0>("----0000-111------------1011----", &Visitor::LDRHT) }, + { "LDRHT (A2)", MakeMatcher<0>("----0000-011--------00001011----", &Visitor::LDRHT) }, + { "LDRSB (imm)", MakeMatcher<0>("----000--1-1------------1101----", &Visitor::LDRSB_imm) }, + { "LDRSB (reg)", MakeMatcher<0>("----000--0-1--------00001101----", &Visitor::LDRSB_reg) }, + { "LDRSBT (A1)", MakeMatcher<0>("----0000-111------------1101----", &Visitor::LDRSBT) }, + { "LDRSBT (A2)", MakeMatcher<0>("----0000-011--------00001101----", &Visitor::LDRSBT) }, + { "LDRSH (imm)", MakeMatcher<0>("----000--1-1------------1111----", &Visitor::LDRSH_imm) }, + { "LDRSH (reg)", MakeMatcher<0>("----000--0-1--------00001111----", &Visitor::LDRSH_reg) }, + { "LDRSHT (A1)", MakeMatcher<0>("----0000-111------------1111----", &Visitor::LDRSHT) }, + { "LDRSHT (A2)", MakeMatcher<0>("----0000-011--------00001111----", &Visitor::LDRSHT) }, + { "LDRT (A1)", MakeMatcher<0>("----0100-011--------------------", &Visitor::LDRT) }, + { "LDRT (A2)", MakeMatcher<0>("----0110-011---------------0----", &Visitor::LDRT) }, + { "STR (imm)", MakeMatcher<0>("----010--0-0--------------------", &Visitor::STR_imm) }, + { "STR (reg)", MakeMatcher<0>("----011--0-0---------------0----", &Visitor::STR_reg) }, + { "STRB (imm)", MakeMatcher<0>("----010--1-0--------------------", &Visitor::STRB_imm) }, + { "STRB (reg)", MakeMatcher<0>("----011--1-0---------------0----", &Visitor::STRB_reg) }, + { "STRBT (A1)", MakeMatcher<0>("----0100-110--------------------", &Visitor::STRBT) }, + { "STRBT (A2)", MakeMatcher<0>("----0110-110---------------0----", &Visitor::STRBT) }, + { "STRD (imm)", MakeMatcher<0>("----000--1-0------------1111----", &Visitor::STRD_imm) }, + { "STRD (reg)", MakeMatcher<0>("----000--0-0--------00001111----", &Visitor::STRD_reg) }, + { "STRH (imm)", MakeMatcher<0>("----000--1-0------------1011----", &Visitor::STRH_imm) }, + { "STRH (reg)", MakeMatcher<0>("----000--0-0--------00001011----", &Visitor::STRH_reg) }, + { "STRHT (A1)", MakeMatcher<0>("----0000-110------------1011----", &Visitor::STRHT) }, + { "STRHT (A2)", MakeMatcher<0>("----0000-010--------00001011----", &Visitor::STRHT) }, + { "STRT (A1)", MakeMatcher<0>("----0100-010--------------------", &Visitor::STRT) }, + { "STRT (A2)", MakeMatcher<0>("----0110-010---------------0----", &Visitor::STRT) }, // Load/Store Multiple instructions - { "LDMIA/LDMFD", MakeMatcher<0>("xxxx100010x1xxxxxxxxxxxxxxxxxxxx", &Visitor::LDM) }, - { "LDMDA/LDMFA", MakeMatcher<0>("xxxx100000x1xxxxxxxxxxxxxxxxxxxx", &Visitor::LDM) }, - { "LDMDB/LDMEA", MakeMatcher<0>("xxxx100100x1xxxxxxxxxxxxxxxxxxxx", &Visitor::LDM) }, - { "LDMIB/LDMED", MakeMatcher<0>("xxxx100110x1xxxxxxxxxxxxxxxxxxxx", &Visitor::LDM) }, - { "LDM (exc ret)", MakeMatcher<0>("xxxx100xx1x1xxxx1xxxxxxxxxxxxxxx", &Visitor::LDM) }, - { "LDM (usr reg)", MakeMatcher<0>("xxxx100xx1x1xxxx0xxxxxxxxxxxxxxx", &Visitor::LDM) }, - { "POP", MakeMatcher<0>("xxxx100010111101xxxxxxxxxxxxxxxx", &Visitor::LDM) }, - { "POP", MakeMatcher<0>("xxxx010010011101xxxx000000000100", &Visitor::LDM) }, - { "PUSH", MakeMatcher<0>("xxxx100100101101xxxxxxxxxxxxxxxx", &Visitor::STM) }, - { "PUSH", MakeMatcher<0>("xxxx010100101101xxxx000000000100", &Visitor::STM) }, - { "STMIA/STMEA", MakeMatcher<0>("xxxx100010x0xxxxxxxxxxxxxxxxxxxx", &Visitor::STM) }, - { "STMDA/STMED", MakeMatcher<0>("xxxx100000x0xxxxxxxxxxxxxxxxxxxx", &Visitor::STM) }, - { "STMDB/STMFD", MakeMatcher<0>("xxxx100100x0xxxxxxxxxxxxxxxxxxxx", &Visitor::STM) }, - { "STMIB/STMFA", MakeMatcher<0>("xxxx100110x0xxxxxxxxxxxxxxxxxxxx", &Visitor::STM) }, - { "STMIB (usr reg)", MakeMatcher<0>("xxxx100xx100xxxxxxxxxxxxxxxxxxxx", &Visitor::STM) }, + { "LDMIA/LDMFD", MakeMatcher<0>("----100010-1--------------------", &Visitor::LDM) }, + { "LDMDA/LDMFA", MakeMatcher<0>("----100000-1--------------------", &Visitor::LDM) }, + { "LDMDB/LDMEA", MakeMatcher<0>("----100100-1--------------------", &Visitor::LDM) }, + { "LDMIB/LDMED", MakeMatcher<0>("----100110-1--------------------", &Visitor::LDM) }, + { "LDM (exc ret)", MakeMatcher<0>("----100--1-1----1---------------", &Visitor::LDM) }, + { "LDM (usr reg)", MakeMatcher<0>("----100--1-1----0---------------", &Visitor::LDM) }, + { "POP", MakeMatcher<0>("----100010111101----------------", &Visitor::LDM) }, + { "POP", MakeMatcher<0>("----010010011101----000000000100", &Visitor::LDM) }, + { "PUSH", MakeMatcher<0>("----100100101101----------------", &Visitor::STM) }, + { "PUSH", MakeMatcher<0>("----010100101101----000000000100", &Visitor::STM) }, + { "STMIA/STMEA", MakeMatcher<0>("----100010-0--------------------", &Visitor::STM) }, + { "STMDA/STMED", MakeMatcher<0>("----100000-0--------------------", &Visitor::STM) }, + { "STMDB/STMFD", MakeMatcher<0>("----100100-0--------------------", &Visitor::STM) }, + { "STMIB/STMFA", MakeMatcher<0>("----100110-0--------------------", &Visitor::STM) }, + { "STMIB (usr reg)", MakeMatcher<0>("----100--100--------------------", &Visitor::STM) }, // Miscellaneous instructions - { "CLZ", MakeMatcher<0>("xxxx000101101111xxxx11110001xxxx", &Visitor::CLZ) }, - { "NOP", MakeMatcher<0>("xxxx0011001000001111000000000000", &Visitor::NOP) }, - { "SEL", MakeMatcher<0>("xxxx01101000xxxxxxxx11111011xxxx", &Visitor::SEL) }, + { "CLZ", MakeMatcher<0>("----000101101111----11110001----", &Visitor::CLZ) }, + { "NOP", MakeMatcher<0>("----0011001000001111000000000000", &Visitor::NOP) }, + { "SEL", MakeMatcher<0>("----01101000--------11111011----", &Visitor::SEL) }, // Unsigned Sum of Absolute Differences instructions - { "USAD8", MakeMatcher<0>("xxxx01111000xxxx1111xxxx0001xxxx", &Visitor::USAD8) }, - { "USADA8", MakeMatcher<0>("xxxx01111000xxxxxxxxxxxx0001xxxx", &Visitor::USADA8) }, + { "USAD8", MakeMatcher<0>("----01111000----1111----0001----", &Visitor::USAD8) }, + { "USADA8", MakeMatcher<0>("----01111000------------0001----", &Visitor::USADA8) }, // Packing instructions - { "PKH", MakeMatcher<0>("xxxx01101000xxxxxxxxxxxxxx01xxxx", &Visitor::PKH) }, + { "PKH", MakeMatcher<0>("----01101000--------------01----", &Visitor::PKH) }, // Reversal instructions - { "RBIT", MakeMatcher<0>("xxxx011011111111xxxx11110011xxxx", &Visitor::RBIT) }, - { "REV", MakeMatcher<0>("xxxx011010111111xxxx11110011xxxx", &Visitor::REV) }, - { "REV16", MakeMatcher<0>("xxxx011010111111xxxx11111011xxxx", &Visitor::REV16) }, - { "REVSH", MakeMatcher<0>("xxxx011011111111xxxx11111011xxxx", &Visitor::REVSH) }, + { "RBIT", MakeMatcher<0>("----011011111111----11110011----", &Visitor::RBIT) }, + { "REV", MakeMatcher<0>("----011010111111----11110011----", &Visitor::REV) }, + { "REV16", MakeMatcher<0>("----011010111111----11111011----", &Visitor::REV16) }, + { "REVSH", MakeMatcher<0>("----011011111111----11111011----", &Visitor::REVSH) }, // Saturation instructions - { "SSAT", MakeMatcher<0>("xxxx0110101xxxxxxxxxxxxxxx01xxxx", &Visitor::SSAT) }, - { "SSAT16", MakeMatcher<0>("xxxx01101010xxxxxxxx11110011xxxx", &Visitor::SSAT16) }, - { "USAT", MakeMatcher<0>("xxxx0110111xxxxxxxxxxxxxxx01xxxx", &Visitor::USAT) }, - { "USAT16", MakeMatcher<0>("xxxx01101110xxxxxxxx11110011xxxx", &Visitor::USAT16) }, + { "SSAT", MakeMatcher<0>("----0110101---------------01----", &Visitor::SSAT) }, + { "SSAT16", MakeMatcher<0>("----01101010--------11110011----", &Visitor::SSAT16) }, + { "USAT", MakeMatcher<0>("----0110111---------------01----", &Visitor::USAT) }, + { "USAT16", MakeMatcher<0>("----01101110--------11110011----", &Visitor::USAT16) }, // Multiply (Normal) instructions - { "MLA", MakeMatcher<0>("xxxx0000001xxxxxxxxxxxxx1001xxxx", &Visitor::MLA) }, - { "MLS", MakeMatcher<0>("xxxx00000110xxxxxxxxxxxx1001xxxx", &Visitor::MLS) }, - { "MUL", MakeMatcher<0>("xxxx0000000xxxxx0000xxxx1001xxxx", &Visitor::MUL) }, + { "MLA", MakeMatcher<0>("----0000001-------------1001----", &Visitor::MLA) }, + { "MLS", MakeMatcher<0>("----00000110------------1001----", &Visitor::MLS) }, + { "MUL", MakeMatcher<0>("----0000000-----0000----1001----", &Visitor::MUL) }, // Multiply (Long) instructions - { "SMLAL", MakeMatcher<0>("xxxx0000111xxxxxxxxxxxxx1001xxxx", &Visitor::SMLAL) }, - { "SMULL", MakeMatcher<0>("xxxx0000110xxxxxxxxxxxxx1001xxxx", &Visitor::SMULL) }, - { "UMAAL", MakeMatcher<0>("xxxx00000100xxxxxxxxxxxx1001xxxx", &Visitor::UMAAL) }, - { "UMLAL", MakeMatcher<0>("xxxx0000101xxxxxxxxxxxxx1001xxxx", &Visitor::UMLAL) }, - { "UMULL", MakeMatcher<0>("xxxx0000100xxxxxxxxxxxxx1001xxxx", &Visitor::UMULL) }, + { "SMLAL", MakeMatcher<0>("----0000111-------------1001----", &Visitor::SMLAL) }, + { "SMULL", MakeMatcher<0>("----0000110-------------1001----", &Visitor::SMULL) }, + { "UMAAL", MakeMatcher<0>("----00000100------------1001----", &Visitor::UMAAL) }, + { "UMLAL", MakeMatcher<0>("----0000101-------------1001----", &Visitor::UMLAL) }, + { "UMULL", MakeMatcher<0>("----0000100-------------1001----", &Visitor::UMULL) }, // Multiply (Halfword) instructions - { "SMLALXY", MakeMatcher<0>("xxxx00010100xxxxxxxxxxxx1xx0xxxx", &Visitor::SMLALxy) }, - { "SMLAXY", MakeMatcher<0>("xxxx00010000xxxxxxxxxxxx1xx0xxxx", &Visitor::SMLAxy) }, - { "SMULXY", MakeMatcher<0>("xxxx00010110xxxx0000xxxx1xx0xxxx", &Visitor::SMULxy) }, + { "SMLALXY", MakeMatcher<0>("----00010100------------1--0----", &Visitor::SMLALxy) }, + { "SMLAXY", MakeMatcher<0>("----00010000------------1--0----", &Visitor::SMLAxy) }, + { "SMULXY", MakeMatcher<0>("----00010110----0000----1--0----", &Visitor::SMULxy) }, // Multiply (Word by Halfword) instructions - { "SMLAWY", MakeMatcher<0>("xxxx00010010xxxxxxxxxxxx1x00xxxx", &Visitor::SMLAWy) }, - { "SMULWY", MakeMatcher<0>("xxxx00010010xxxx0000xxxx1x10xxxx", &Visitor::SMULWy) }, + { "SMLAWY", MakeMatcher<0>("----00010010------------1-00----", &Visitor::SMLAWy) }, + { "SMULWY", MakeMatcher<0>("----00010010----0000----1-10----", &Visitor::SMULWy) }, // Multiply (Most Significant Word) instructions - { "SMMUL", MakeMatcher<0>("xxxx01110101xxxx1111xxxx00x1xxxx", &Visitor::SMMUL) }, - { "SMMLA", MakeMatcher<0>("xxxx01110101xxxxxxxxxxxx00x1xxxx", &Visitor::SMMLA) }, - { "SMMLS", MakeMatcher<0>("xxxx01110101xxxxxxxxxxxx11x1xxxx", &Visitor::SMMLS) }, + { "SMMUL", MakeMatcher<0>("----01110101----1111----00-1----", &Visitor::SMMUL) }, + { "SMMLA", MakeMatcher<0>("----01110101------------00-1----", &Visitor::SMMLA) }, + { "SMMLS", MakeMatcher<0>("----01110101------------11-1----", &Visitor::SMMLS) }, // Multiply (Dual) instructions - { "SMLAD", MakeMatcher<0>("xxxx01110000xxxxxxxxxxxx00x1xxxx", &Visitor::SMLAD) }, - { "SMLALD", MakeMatcher<0>("xxxx01110100xxxxxxxxxxxx00x1xxxx", &Visitor::SMLALD) }, - { "SMLSD", MakeMatcher<0>("xxxx01110000xxxxxxxxxxxx01x1xxxx", &Visitor::SMLSD) }, - { "SMLSLD", MakeMatcher<0>("xxxx01110100xxxxxxxxxxxx01x1xxxx", &Visitor::SMLSLD) }, - { "SMUAD", MakeMatcher<0>("xxxx01110000xxxx1111xxxx00x1xxxx", &Visitor::SMUAD) }, - { "SMUSD", MakeMatcher<0>("xxxx01110000xxxx1111xxxx01x1xxxx", &Visitor::SMUSD) }, + { "SMLAD", MakeMatcher<0>("----01110000------------00-1----", &Visitor::SMLAD) }, + { "SMLALD", MakeMatcher<0>("----01110100------------00-1----", &Visitor::SMLALD) }, + { "SMLSD", MakeMatcher<0>("----01110000------------01-1----", &Visitor::SMLSD) }, + { "SMLSLD", MakeMatcher<0>("----01110100------------01-1----", &Visitor::SMLSLD) }, + { "SMUAD", MakeMatcher<0>("----01110000----1111----00-1----", &Visitor::SMUAD) }, + { "SMUSD", MakeMatcher<0>("----01110000----1111----01-1----", &Visitor::SMUSD) }, // Parallel Add/Subtract (Modulo) instructions - { "SADD8", MakeMatcher<0>("xxxx01100001xxxxxxxx11111001xxxx", &Visitor::SADD8) }, - { "SADD16", MakeMatcher<0>("xxxx01100001xxxxxxxx11110001xxxx", &Visitor::SADD16) }, - { "SASX", MakeMatcher<0>("xxxx01100001xxxxxxxx11110011xxxx", &Visitor::SASX) }, - { "SSAX", MakeMatcher<0>("xxxx01100001xxxxxxxx11110101xxxx", &Visitor::SSAX) }, - { "SSUB8", MakeMatcher<0>("xxxx01100001xxxxxxxx11111111xxxx", &Visitor::SSUB8) }, - { "SSUB16", MakeMatcher<0>("xxxx01100001xxxxxxxx11110111xxxx", &Visitor::SSUB16) }, - { "UADD8", MakeMatcher<0>("xxxx01100101xxxxxxxx11111001xxxx", &Visitor::UADD8) }, - { "UADD16", MakeMatcher<0>("xxxx01100101xxxxxxxx11110001xxxx", &Visitor::UADD16) }, - { "UASX", MakeMatcher<0>("xxxx01100101xxxxxxxx11110011xxxx", &Visitor::UASX) }, - { "USAX", MakeMatcher<0>("xxxx01100101xxxxxxxx11110101xxxx", &Visitor::USAX) }, - { "USUB8", MakeMatcher<0>("xxxx01100101xxxxxxxx11111111xxxx", &Visitor::USUB8) }, - { "USUB16", MakeMatcher<0>("xxxx01100101xxxxxxxx11110111xxxx", &Visitor::USUB16) }, + { "SADD8", MakeMatcher<0>("----01100001--------11111001----", &Visitor::SADD8) }, + { "SADD16", MakeMatcher<0>("----01100001--------11110001----", &Visitor::SADD16) }, + { "SASX", MakeMatcher<0>("----01100001--------11110011----", &Visitor::SASX) }, + { "SSAX", MakeMatcher<0>("----01100001--------11110101----", &Visitor::SSAX) }, + { "SSUB8", MakeMatcher<0>("----01100001--------11111111----", &Visitor::SSUB8) }, + { "SSUB16", MakeMatcher<0>("----01100001--------11110111----", &Visitor::SSUB16) }, + { "UADD8", MakeMatcher<0>("----01100101--------11111001----", &Visitor::UADD8) }, + { "UADD16", MakeMatcher<0>("----01100101--------11110001----", &Visitor::UADD16) }, + { "UASX", MakeMatcher<0>("----01100101--------11110011----", &Visitor::UASX) }, + { "USAX", MakeMatcher<0>("----01100101--------11110101----", &Visitor::USAX) }, + { "USUB8", MakeMatcher<0>("----01100101--------11111111----", &Visitor::USUB8) }, + { "USUB16", MakeMatcher<0>("----01100101--------11110111----", &Visitor::USUB16) }, // Parallel Add/Subtract (Saturating) instructions - { "QADD8", MakeMatcher<0>("xxxx01100010xxxxxxxx11111001xxxx", &Visitor::QADD8) }, - { "QADD16", MakeMatcher<0>("xxxx01100010xxxxxxxx11110001xxxx", &Visitor::QADD16) }, - { "QASX", MakeMatcher<0>("xxxx01100010xxxxxxxx11110011xxxx", &Visitor::QASX) }, - { "QSAX", MakeMatcher<0>("xxxx01100010xxxxxxxx11110101xxxx", &Visitor::QSAX) }, - { "QSUB8", MakeMatcher<0>("xxxx01100010xxxxxxxx11111111xxxx", &Visitor::QSUB8) }, - { "QSUB16", MakeMatcher<0>("xxxx01100010xxxxxxxx11110111xxxx", &Visitor::QSUB16) }, - { "UQADD8", MakeMatcher<0>("xxxx01100110xxxxxxxx11111001xxxx", &Visitor::UQADD8) }, - { "UQADD16", MakeMatcher<0>("xxxx01100110xxxxxxxx11110001xxxx", &Visitor::UQADD16) }, - { "UQASX", MakeMatcher<0>("xxxx01100110xxxxxxxx11110011xxxx", &Visitor::UQASX) }, - { "UQSAX", MakeMatcher<0>("xxxx01100110xxxxxxxx11110101xxxx", &Visitor::UQSAX) }, - { "UQSUB8", MakeMatcher<0>("xxxx01100110xxxxxxxx11111111xxxx", &Visitor::UQSUB8) }, - { "UQSUB16", MakeMatcher<0>("xxxx01100110xxxxxxxx11110111xxxx", &Visitor::UQSUB16) }, + { "QADD8", MakeMatcher<0>("----01100010--------11111001----", &Visitor::QADD8) }, + { "QADD16", MakeMatcher<0>("----01100010--------11110001----", &Visitor::QADD16) }, + { "QASX", MakeMatcher<0>("----01100010--------11110011----", &Visitor::QASX) }, + { "QSAX", MakeMatcher<0>("----01100010--------11110101----", &Visitor::QSAX) }, + { "QSUB8", MakeMatcher<0>("----01100010--------11111111----", &Visitor::QSUB8) }, + { "QSUB16", MakeMatcher<0>("----01100010--------11110111----", &Visitor::QSUB16) }, + { "UQADD8", MakeMatcher<0>("----01100110--------11111001----", &Visitor::UQADD8) }, + { "UQADD16", MakeMatcher<0>("----01100110--------11110001----", &Visitor::UQADD16) }, + { "UQASX", MakeMatcher<0>("----01100110--------11110011----", &Visitor::UQASX) }, + { "UQSAX", MakeMatcher<0>("----01100110--------11110101----", &Visitor::UQSAX) }, + { "UQSUB8", MakeMatcher<0>("----01100110--------11111111----", &Visitor::UQSUB8) }, + { "UQSUB16", MakeMatcher<0>("----01100110--------11110111----", &Visitor::UQSUB16) }, // Parallel Add/Subtract (Halving) instructions - { "SHADD8", MakeMatcher<0>("xxxx01100011xxxxxxxx11111001xxxx", &Visitor::SHADD8) }, - { "SHADD16", MakeMatcher<0>("xxxx01100011xxxxxxxx11110001xxxx", &Visitor::SHADD16) }, - { "SHASX", MakeMatcher<0>("xxxx01100011xxxxxxxx11110011xxxx", &Visitor::SHASX) }, - { "SHSAX", MakeMatcher<0>("xxxx01100011xxxxxxxx11110101xxxx", &Visitor::SHSAX) }, - { "SHSUB8", MakeMatcher<0>("xxxx01100011xxxxxxxx11111111xxxx", &Visitor::SHSUB8) }, - { "SHSUB16", MakeMatcher<0>("xxxx01100011xxxxxxxx11110111xxxx", &Visitor::SHSUB16) }, - { "UHADD8", MakeMatcher<0>("xxxx01100111xxxxxxxx11111001xxxx", &Visitor::UHADD8) }, - { "UHADD16", MakeMatcher<0>("xxxx01100111xxxxxxxx11110001xxxx", &Visitor::UHADD16) }, - { "UHASX", MakeMatcher<0>("xxxx01100111xxxxxxxx11110011xxxx", &Visitor::UHASX) }, - { "UHSAX", MakeMatcher<0>("xxxx01100111xxxxxxxx11110101xxxx", &Visitor::UHSAX) }, - { "UHSUB8", MakeMatcher<0>("xxxx01100111xxxxxxxx11111111xxxx", &Visitor::UHSUB8) }, - { "UHSUB16", MakeMatcher<0>("xxxx01100111xxxxxxxx11110111xxxx", &Visitor::UHSUB16) }, + { "SHADD8", MakeMatcher<0>("----01100011--------11111001----", &Visitor::SHADD8) }, + { "SHADD16", MakeMatcher<0>("----01100011--------11110001----", &Visitor::SHADD16) }, + { "SHASX", MakeMatcher<0>("----01100011--------11110011----", &Visitor::SHASX) }, + { "SHSAX", MakeMatcher<0>("----01100011--------11110101----", &Visitor::SHSAX) }, + { "SHSUB8", MakeMatcher<0>("----01100011--------11111111----", &Visitor::SHSUB8) }, + { "SHSUB16", MakeMatcher<0>("----01100011--------11110111----", &Visitor::SHSUB16) }, + { "UHADD8", MakeMatcher<0>("----01100111--------11111001----", &Visitor::UHADD8) }, + { "UHADD16", MakeMatcher<0>("----01100111--------11110001----", &Visitor::UHADD16) }, + { "UHASX", MakeMatcher<0>("----01100111--------11110011----", &Visitor::UHASX) }, + { "UHSAX", MakeMatcher<0>("----01100111--------11110101----", &Visitor::UHSAX) }, + { "UHSUB8", MakeMatcher<0>("----01100111--------11111111----", &Visitor::UHSUB8) }, + { "UHSUB16", MakeMatcher<0>("----01100111--------11110111----", &Visitor::UHSUB16) }, // Saturated Add/Subtract instructions - { "QADD", MakeMatcher<0>("xxxx00010000xxxxxxxx00000101xxxx", &Visitor::QADD) }, - { "QSUB", MakeMatcher<0>("xxxx00010010xxxxxxxx00000101xxxx", &Visitor::QSUB) }, - { "QDADD", MakeMatcher<0>("xxxx00010100xxxxxxxx00000101xxxx", &Visitor::QDADD) }, - { "QDSUB", MakeMatcher<0>("xxxx00010110xxxxxxxx00000101xxxx", &Visitor::QDSUB) }, + { "QADD", MakeMatcher<0>("----00010000--------00000101----", &Visitor::QADD) }, + { "QSUB", MakeMatcher<0>("----00010010--------00000101----", &Visitor::QSUB) }, + { "QDADD", MakeMatcher<0>("----00010100--------00000101----", &Visitor::QDADD) }, + { "QDSUB", MakeMatcher<0>("----00010110--------00000101----", &Visitor::QDSUB) }, // Status Register Access instructions - { "CPS", MakeMatcher<0>("xxxx00010000xxx00000000xxx0xxxxx", &Visitor::CPS) }, - { "ERET", MakeMatcher<0>("xxxx0001011000000000000001101110", &Visitor::ERET) }, - { "SETEND", MakeMatcher<0>("1111000100000001000000x000000000", &Visitor::SETEND) }, - { "MRS", MakeMatcher<0>("xxxx000100001111xxxx000000000000", &Visitor::MRS) }, - { "MRS (banked)", MakeMatcher<0>("xxxx00010x00xxxxxxxx001x00000000", &Visitor::MRS) }, - { "MRS (system)", MakeMatcher<0>("xxxx00010x001111xxxx000000000000", &Visitor::MRS) }, - { "MSR (imm)", MakeMatcher<0>("xxxx00110010xx001111xxxxxxxxxxxx", &Visitor::MSR) }, - { "MSR (reg)", MakeMatcher<0>("xxxx00010010xx00111100000000xxxx", &Visitor::MSR) }, - { "MSR (banked)", MakeMatcher<0>("xxxx00010x10xxxx1111001x0000xxxx", &Visitor::MSR) }, - { "MSR (imm special)", MakeMatcher<0>("xxxx00110x10xxxx1111xxxxxxxxxxxx", &Visitor::MSR) }, - { "MSR (reg special)", MakeMatcher<0>("xxxx00010x10xxxx111100000000xxxx", &Visitor::MSR) }, - { "RFE", MakeMatcher<0>("xxxx0001101x0000xxxxxxxxx110xxxx", &Visitor::RFE) }, - { "SRS", MakeMatcher<0>("0000011xx0x00000000000000001xxxx", &Visitor::SRS) }, + { "CPS", MakeMatcher<0>("----00010000---00000000---0-----", &Visitor::CPS) }, + { "ERET", MakeMatcher<0>("----0001011000000000000001101110", &Visitor::ERET) }, + { "SETEND", MakeMatcher<0>("1111000100000001000000-000000000", &Visitor::SETEND) }, + { "MRS", MakeMatcher<0>("----000100001111----000000000000", &Visitor::MRS) }, + { "MRS (banked)", MakeMatcher<0>("----00010-00--------001-00000000", &Visitor::MRS) }, + { "MRS (system)", MakeMatcher<0>("----00010-001111----000000000000", &Visitor::MRS) }, + { "MSR (imm)", MakeMatcher<0>("----00110010--001111------------", &Visitor::MSR) }, + { "MSR (reg)", MakeMatcher<0>("----00010010--00111100000000----", &Visitor::MSR) }, + { "MSR (banked)", MakeMatcher<0>("----00010-10----1111001-0000----", &Visitor::MSR) }, + { "MSR (imm special)", MakeMatcher<0>("----00110-10----1111------------", &Visitor::MSR) }, + { "MSR (reg special)", MakeMatcher<0>("----00010-10----111100000000----", &Visitor::MSR) }, + { "RFE", MakeMatcher<0>("----0001101-0000---------110----", &Visitor::RFE) }, + { "SRS", MakeMatcher<0>("0000011--0-00000000000000001----", &Visitor::SRS) }, }}; const Instruction& DecodeArm(u32 i) { diff --git a/src/core/arm/jit_x64/instructions/data_processing.cpp b/src/core/arm/jit_x64/instructions/data_processing.cpp index 3d2346b6e..aeec093a2 100644 --- a/src/core/arm/jit_x64/instructions/data_processing.cpp +++ b/src/core/arm/jit_x64/instructions/data_processing.cpp @@ -2,11 +2,79 @@ // Licensed under GPLv2 or any later version // Refer to the license.txt file included. +#include "common/common_funcs.h" + #include "core/arm/jit_x64/jit_x64.h" namespace JitX64 { -void JitX64::ADC_imm(Cond cond, bool S, ArmReg Rn, ArmReg Rd, int rotate, ArmImm8 imm8) { CompileInterpretInstruction(); } +using namespace Gen; + +void JitX64::ADC_imm(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, int rotate, ArmImm8 imm8) { + cond_manager.CompileCond((ConditionCode)cond); + + u32 immediate = _rotr(imm8, rotate * 2); + + if (Rd_index == 15) { + X64Reg Rd = reg_alloc.AllocAndLockTemp(); + reg_alloc.LockArm(Rn_index); + + if (Rn_index == 15) { + code->MOV(32, R(Rd), Imm32(GetReg15Value())); + } else { + code->MOV(32, R(Rd), reg_alloc.ArmR(Rd_index)); + } + code->BT(32, MJitStateCFlag(), Imm8(0)); + code->ADC(32, R(Rd), Imm32(immediate)); + + reg_alloc.UnlockArm(Rn_index); + + if (S) + UNIMPLEMENTED(); + + code->MOV(32, MJitStateArmPC(), R(Rd)); + reg_alloc.UnlockTemp(Rd); + current.arm_pc += GetInstSize(); + CompileReturnToDispatch(); + return; + } else if (Rn_index == 15) { + X64Reg Rd = reg_alloc.BindNoLoadAndLockArm(Rd_index); + reg_alloc.MarkDirty(Rd_index); + + code->MOV(32, R(Rd), Imm32(GetReg15Value())); + code->BT(32, MJitStateCFlag(), Imm8(0)); + code->ADC(32, R(Rd), Imm32(immediate)); + + reg_alloc.UnlockArm(Rd_index); + } else if (Rn_index == Rd_index) { + X64Reg Rd = reg_alloc.BindAndLockArm(Rd_index); + reg_alloc.MarkDirty(Rd_index); + + code->BT(32, MJitStateCFlag(), Imm8(0)); + code->ADC(32, R(Rd), Imm32(immediate)); + + reg_alloc.UnlockArm(Rd_index); + } else { + X64Reg Rd = reg_alloc.BindNoLoadAndLockArm(Rd_index); + reg_alloc.MarkDirty(Rd_index); + reg_alloc.LockArm(Rn_index); + + code->MOV(32, R(Rd), reg_alloc.ArmR(Rn_index)); + code->BT(32, MJitStateCFlag(), Imm8(0)); + code->ADC(32, R(Rd), Imm32(immediate)); + + reg_alloc.UnlockArm(Rd_index); + reg_alloc.UnlockArm(Rn_index); + } + + if (S) { + cond_manager.FlagsDirty(); + UpdateFlagsZVCN(); + } + + current.arm_pc += GetInstSize(); +} + void JitX64::ADC_reg(Cond cond, bool S, ArmReg Rn, ArmReg Rd, ArmImm5 imm5, ShiftType shift, ArmReg Rm) { CompileInterpretInstruction(); } void JitX64::ADC_rsr(Cond cond, bool S, ArmReg Rn, ArmReg Rd, ArmReg Rs, ShiftType shift, ArmReg Rm) { CompileInterpretInstruction(); } void JitX64::ADD_imm(Cond cond, bool S, ArmReg Rn, ArmReg Rd, int rotate, ArmImm8 imm8) { CompileInterpretInstruction(); } diff --git a/src/core/arm/jit_x64/jit_x64.cpp b/src/core/arm/jit_x64/jit_x64.cpp index b36690df2..79084f625 100644 --- a/src/core/arm/jit_x64/jit_x64.cpp +++ b/src/core/arm/jit_x64/jit_x64.cpp @@ -66,12 +66,38 @@ CodePtr JitX64::Compile(u32 pc, bool TFlag, bool EFlag) { return bb; } -void JitX64::CompileUpdateCycles() { +void JitX64::CompileUpdateCycles(bool reset_cycles) { // We're just taking one instruction == one cycle. if (instructions_compiled) { code->SUB(32, MJitStateCycleCount(), Imm32(instructions_compiled)); } - instructions_compiled = 0; + if (reset_cycles) { + instructions_compiled = 0; + } +} + +void JitX64::CompileReturnToDispatch() { + if (cond_manager.CurrentCond() == ConditionCode::AL) { + reg_alloc.FlushEverything(); + CompileUpdateCycles(); + code->JMPptr(MJitStateHostReturnRIP()); + + stop_compilation = true; + return; + } + + reg_alloc.FlushEverything(); + CompileUpdateCycles(false); + code->JMPptr(MJitStateHostReturnRIP()); + + cond_manager.Always(); + CompileUpdateCycles(true); + CompileJumpToBB(current.arm_pc); + code->MOV(32, MJitStateArmPC(), Imm32(current.arm_pc)); + code->JMPptr(MJitStateHostReturnRIP()); + + stop_compilation = true; + return; } void JitX64::CompileJumpToBB(u32 new_pc) { diff --git a/src/core/arm/jit_x64/jit_x64.h b/src/core/arm/jit_x64/jit_x64.h index 336c599e7..475cb7c8c 100644 --- a/src/core/arm/jit_x64/jit_x64.h +++ b/src/core/arm/jit_x64/jit_x64.h @@ -65,7 +65,10 @@ private: void CompileSingleThumbInstruction(); /// Updates the cycle count in JitState and sets instructions_compiled to zero. - void CompileUpdateCycles(); + void CompileUpdateCycles(bool reset_cycles = true); + + /// Update MJitStateArmPC and current.TFlag before calling this function. + void CompileReturnToDispatch(); /// If a basic_block starting at ARM pc is compiled -> these locations need to be patched std::unordered_map, LocationDescriptorHash> patch_jmp_locations; @@ -76,6 +79,7 @@ private: private: /// Convenience functions + Gen::OpArg MJitStateCycleCount(); Gen::OpArg MJitStateArmPC(); Gen::OpArg MJitStateHostReturnRIP(); @@ -87,6 +91,25 @@ private: Gen::OpArg MJitStateExclusiveTag(); Gen::OpArg MJitStateExclusiveState(); + FORCE_INLINE u32 GetReg15Value() { return (current.arm_pc & ~0x1) + GetInstSize() * 2; } + + FORCE_INLINE void UpdateFlagsZVCN() { + code->SETcc(Gen::CC_Z, MJitStateZFlag()); + code->SETcc(Gen::CC_C, MJitStateCFlag()); + code->SETcc(Gen::CC_O, MJitStateVFlag()); + code->SETcc(Gen::CC_S, MJitStateNFlag()); + } + + FORCE_INLINE void UpdateFlagsZVN() { + code->SETcc(Gen::CC_Z, MJitStateZFlag()); + code->SETcc(Gen::CC_O, MJitStateVFlag()); + code->SETcc(Gen::CC_S, MJitStateNFlag()); + } + + FORCE_INLINE void UpdateFlagsC_complement() { + code->SETcc(Gen::CC_NC, MJitStateCFlag()); + } + private: struct CondManager { private: diff --git a/src/core/arm/jit_x64/reg_alloc.h b/src/core/arm/jit_x64/reg_alloc.h index c6805890d..37ffb9a85 100644 --- a/src/core/arm/jit_x64/reg_alloc.h +++ b/src/core/arm/jit_x64/reg_alloc.h @@ -68,7 +68,7 @@ public: void UnlockArm(ArmReg arm_reg); /// Flush all ARM registers. void FlushAllArm(); - /// Marks an ARM register as dirty. + /// Marks an ARM register as dirty. If you don't mark something as dirty it won't be flushed. void MarkDirty(ArmReg arm_reg); /// Flush absolutely everything. diff --git a/src/tests/core/arm/jit_x64/fuzz_arm_data_processing.cpp b/src/tests/core/arm/jit_x64/fuzz_arm_data_processing.cpp index d9c3cfbc1..60f8f0f63 100644 --- a/src/tests/core/arm/jit_x64/fuzz_arm_data_processing.cpp +++ b/src/tests/core/arm/jit_x64/fuzz_arm_data_processing.cpp @@ -152,7 +152,7 @@ TEST_CASE("Fuzz ARM data processing instructions", "[JitX64]") { Memory::Write32(i * 4, inst); } - Memory::Write32(NUM_INST * 4, 0b11100011001000000000111100000000); + Memory::Write32(NUM_INST * 4, 0b0011001000001111000000000000); interp.ExecuteInstructions(NUM_INST); jit.ExecuteInstructions(NUM_INST);