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https://github.com/citra-emu/citra.git
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fixup! Addressed comments regarding JitX64::JitX64
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25201712db
commit
9874fae84b
@ -27,8 +27,6 @@ struct JitState {
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ARMul_State cpu_state;
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void* bb;
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u64 save_host_RSP;
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u64 return_RIP;
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@ -72,12 +72,9 @@ void JitX64::ADC_imm(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, int ro
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});
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if (S) {
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cond_manager.FlagsDirty();
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UpdateFlagsZVCN();
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}
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reg_alloc.AssertNoLocked();
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current.arm_pc += GetInstSize();
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if (Rd_index == 15) {
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CompileReturnToDispatch();
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@ -94,12 +91,9 @@ void JitX64::ADD_imm(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, int ro
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});
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if (S) {
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cond_manager.FlagsDirty();
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UpdateFlagsZVCN();
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}
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reg_alloc.AssertNoLocked();
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current.arm_pc += GetInstSize();
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if (Rd_index == 15) {
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CompileReturnToDispatch();
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@ -116,15 +110,12 @@ void JitX64::AND_imm(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, int ro
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});
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if (S) {
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cond_manager.FlagsDirty();
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UpdateFlagsZN();
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if (rotate != 0) {
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code->MOV(32, MJitStateCFlag(), Imm32(immediate & 0x80000000 ? 1 : 0));
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}
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}
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reg_alloc.AssertNoLocked();
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current.arm_pc += GetInstSize();
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if (Rd_index == 15) {
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CompileReturnToDispatch();
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@ -141,15 +132,12 @@ void JitX64::BIC_imm(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, int ro
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});
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if (S) {
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cond_manager.FlagsDirty();
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UpdateFlagsZN();
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if (rotate != 0) {
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code->MOV(32, MJitStateCFlag(), Imm32(immediate & 0x80000000 ? 1 : 0));
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}
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}
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reg_alloc.AssertNoLocked();
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current.arm_pc += GetInstSize();
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if (Rd_index == 15) {
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CompileReturnToDispatch();
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@ -169,15 +157,12 @@ void JitX64::EOR_imm(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, int ro
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});
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if (S) {
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cond_manager.FlagsDirty();
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UpdateFlagsZN();
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if (rotate != 0) {
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code->MOV(32, MJitStateCFlag(), Imm32(immediate & 0x80000000 ? 1 : 0));
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}
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}
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reg_alloc.AssertNoLocked();
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current.arm_pc += GetInstSize();
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if (Rd_index == 15) {
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CompileReturnToDispatch();
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@ -194,7 +179,6 @@ void JitX64::MOV_imm(Cond cond, bool S, ArmReg Rd_index, int rotate, ArmImm8 imm
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reg_alloc.UnlockArm(Rd_index);
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if (S) {
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cond_manager.FlagsDirty();
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Gen::OpArg Rd = reg_alloc.LockArmForRead(Rd_index);
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code->CMP(32, Rd, Imm32(0));
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reg_alloc.UnlockArm(Rd_index);
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@ -204,8 +188,6 @@ void JitX64::MOV_imm(Cond cond, bool S, ArmReg Rd_index, int rotate, ArmImm8 imm
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}
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}
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reg_alloc.AssertNoLocked();
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current.arm_pc += GetInstSize();
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if (Rd_index == 15) {
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CompileReturnToDispatch();
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@ -222,7 +204,6 @@ void JitX64::MVN_imm(Cond cond, bool S, ArmReg Rd_index, int rotate, ArmImm8 imm
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reg_alloc.UnlockArm(Rd_index);
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if (S) {
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cond_manager.FlagsDirty();
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Gen::OpArg Rd = reg_alloc.LockArmForRead(Rd_index);
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code->CMP(32, Rd, Imm32(0));
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reg_alloc.UnlockArm(Rd_index);
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@ -232,8 +213,6 @@ void JitX64::MVN_imm(Cond cond, bool S, ArmReg Rd_index, int rotate, ArmImm8 imm
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}
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}
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reg_alloc.AssertNoLocked();
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current.arm_pc += GetInstSize();
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if (Rd_index == 15) {
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CompileReturnToDispatch();
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@ -250,15 +229,12 @@ void JitX64::ORR_imm(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, int ro
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});
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if (S) {
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cond_manager.FlagsDirty();
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UpdateFlagsZN();
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if (rotate != 0) {
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code->MOV(32, MJitStateCFlag(), Imm32(immediate & 0x80000000 ? 1 : 0));
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}
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}
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reg_alloc.AssertNoLocked();
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current.arm_pc += GetInstSize();
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if (Rd_index == 15) {
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CompileReturnToDispatch();
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@ -283,13 +259,10 @@ void JitX64::RSB_imm(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, int ro
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});
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if (S) {
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cond_manager.FlagsDirty();
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UpdateFlagsZVN();
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UpdateFlagsC_complement();
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}
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reg_alloc.AssertNoLocked();
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current.arm_pc += GetInstSize();
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if (Rd_index == 15) {
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CompileReturnToDispatch();
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@ -317,13 +290,10 @@ void JitX64::RSC_imm(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, int ro
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});
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if (S) {
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cond_manager.FlagsDirty();
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UpdateFlagsZVN();
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UpdateFlagsC_complement();
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}
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reg_alloc.AssertNoLocked();
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current.arm_pc += GetInstSize();
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if (Rd_index == 15) {
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CompileReturnToDispatch();
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@ -342,13 +312,10 @@ void JitX64::SBC_imm(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, int ro
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});
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if (S) {
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cond_manager.FlagsDirty();
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UpdateFlagsZVN();
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UpdateFlagsC_complement();
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}
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reg_alloc.AssertNoLocked();
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current.arm_pc += GetInstSize();
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if (Rd_index == 15) {
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CompileReturnToDispatch();
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@ -365,13 +332,10 @@ void JitX64::SUB_imm(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, int ro
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});
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if (S) {
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cond_manager.FlagsDirty();
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UpdateFlagsZVN();
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UpdateFlagsC_complement();
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}
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reg_alloc.AssertNoLocked();
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current.arm_pc += GetInstSize();
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if (Rd_index == 15) {
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CompileReturnToDispatch();
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@ -397,14 +361,11 @@ void JitX64::TEQ_imm(Cond cond, ArmReg Rn_index, int rotate, ArmImm8 imm8) {
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reg_alloc.UnlockTemp(Rn_tmp);
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cond_manager.FlagsDirty();
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UpdateFlagsZN();
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if (rotate != 0) {
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code->MOV(32, MJitStateCFlag(), Imm32(immediate & 0x80000000 ? 1 : 0));
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}
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reg_alloc.AssertNoLocked();
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current.arm_pc += GetInstSize();
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}
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@ -430,14 +391,11 @@ void JitX64::TST_imm(Cond cond, ArmReg Rn_index, int rotate, ArmImm8 imm8) {
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reg_alloc.UnlockArm(Rn_index);
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}
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cond_manager.FlagsDirty();
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UpdateFlagsZN();
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if (rotate != 0) {
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code->MOV(32, MJitStateCFlag(), Imm32(immediate & 0x80000000 ? 1 : 0));
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}
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reg_alloc.AssertNoLocked();
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current.arm_pc += GetInstSize();
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}
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@ -51,7 +51,6 @@ public:
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cpu->VFlag = (cpu->Cpsr >> 28) & 1;
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cpu->TFlag = (cpu->Cpsr >> 5) & 1;
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jit_state->bb = bb;
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jit_state->cycles_remaining = cycles_to_run;
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jit_state->return_RIP = (u64)CallCodeReturnAddress();
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@ -87,7 +86,7 @@ namespace JitX64 {
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static Gen::RunJittedCode run_jit = {};
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static Gen::BlockOfCode block_of_code = {};
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static JitX64 compiler = { &block_of_code };
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static JitX64 compiler { &block_of_code };
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ARM_Jit::ARM_Jit(PrivilegeMode initial_mode) {
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ASSERT_MSG(initial_mode == PrivilegeMode::USER32MODE, "Unimplemented");
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@ -10,7 +10,7 @@ namespace JitX64 {
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using namespace Gen;
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JitX64::JitX64(XEmitter* code_) : code(code_) {}
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JitX64::JitX64(XEmitter* code_) : code(code_), current(0, false, false) {}
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void JitX64::ClearCache() {
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basic_blocks.clear();
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@ -49,6 +49,8 @@ CodePtr JitX64::Compile(u32 pc, bool TFlag, bool EFlag) {
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} else {
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CompileSingleArmInstruction();
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}
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reg_alloc.AssertNoLocked();
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} while (!stop_compilation && ((current.arm_pc & 0xFFF) != 0));
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if (!stop_compilation) {
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@ -19,6 +19,8 @@ namespace JitX64 {
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using CodePtr = u8*;
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struct LocationDescriptor {
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LocationDescriptor() = delete;
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LocationDescriptor(u32 arm_pc, bool TFlag, bool EFlag) : arm_pc(arm_pc), TFlag(TFlag), EFlag(EFlag) {}
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u32 arm_pc;
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bool TFlag; ///< Thumb / ARM
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bool EFlag; ///< Big / Little Endian
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@ -36,7 +38,7 @@ struct LocationDescriptorHash {
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class JitX64 final : private ArmDecoder::Visitor {
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private:
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Gen::XEmitter* code;
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Gen::XEmitter* code = nullptr;
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RegAlloc reg_alloc;
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@ -45,7 +47,7 @@ private:
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public:
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JitX64() = delete;
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JitX64(Gen::XEmitter* code_);
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explicit JitX64(Gen::XEmitter* code_);
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~JitX64() override {}
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void ClearCache();
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@ -60,7 +62,7 @@ private:
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unsigned instructions_compiled;
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bool stop_compilation;
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size_t GetInstSize() { return current.TFlag ? 2 : 4; }
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size_t GetInstSize() const { return current.TFlag ? 2 : 4; }
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void CompileSingleArmInstruction();
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void CompileSingleThumbInstruction();
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@ -91,27 +93,31 @@ private:
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Gen::OpArg MJitStateExclusiveTag();
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Gen::OpArg MJitStateExclusiveState();
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FORCE_INLINE u32 GetReg15Value() { return (current.arm_pc & ~0x1) + GetInstSize() * 2; }
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u32 GetReg15Value() const { return (current.arm_pc & ~0x1) + GetInstSize() * 2; }
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FORCE_INLINE void UpdateFlagsZVCN() {
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void UpdateFlagsZVCN() {
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cond_manager.FlagsDirty();
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code->SETcc(Gen::CC_Z, MJitStateZFlag());
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code->SETcc(Gen::CC_C, MJitStateCFlag());
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code->SETcc(Gen::CC_O, MJitStateVFlag());
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code->SETcc(Gen::CC_S, MJitStateNFlag());
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}
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FORCE_INLINE void UpdateFlagsZVN() {
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void UpdateFlagsZVN() {
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cond_manager.FlagsDirty();
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code->SETcc(Gen::CC_Z, MJitStateZFlag());
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code->SETcc(Gen::CC_O, MJitStateVFlag());
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code->SETcc(Gen::CC_S, MJitStateNFlag());
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}
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FORCE_INLINE void UpdateFlagsZN() {
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void UpdateFlagsZN() {
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cond_manager.FlagsDirty();
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code->SETcc(Gen::CC_Z, MJitStateZFlag());
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code->SETcc(Gen::CC_S, MJitStateNFlag());
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}
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FORCE_INLINE void UpdateFlagsC_complement() {
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void UpdateFlagsC_complement() {
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cond_manager.FlagsDirty();
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code->SETcc(Gen::CC_NC, MJitStateCFlag());
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}
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