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ARM/Decoder: Fill out more instructions

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This commit is contained in:
MerryMage 2016-04-03 16:14:48 +01:00
parent 8ee5ba3e8f
commit 6eddd09f30
24 changed files with 368 additions and 367 deletions
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170
src/core/arm/decoder/arm.cpp
View File

@ -195,18 +195,18 @@ static const std::array<Instruction, 221> arm_instruction_table = {{
{ "UDF", MakeMatcher<0>("111001111111------------1111----", &Visitor::UDF) }, // all
// Extension instructions
{ "SXTB", MakeMatcher<0>("----011010101111------000111----", &Visitor::SXTB) }, // ARMv6
{ "SXTB16", MakeMatcher<0>("----011010001111------000111----", &Visitor::SXTB16) }, // ARMv6
{ "SXTH", MakeMatcher<0>("----011010111111------000111----", &Visitor::SXTH) }, // ARMv6
{ "SXTAB", MakeMatcher<0>("----01101010----------000111----", &Visitor::SXTAB) }, // ARMv6
{ "SXTAB16", MakeMatcher<0>("----01101000----------000111----", &Visitor::SXTAB16) }, // ARMv6
{ "SXTAH", MakeMatcher<0>("----01101011----------000111----", &Visitor::SXTAH) }, // ARMv6
{ "UXTB", MakeMatcher<0>("----011011101111------000111----", &Visitor::UXTB) }, // ARMv6
{ "UXTB16", MakeMatcher<0>("----011011001111------000111----", &Visitor::UXTB16) }, // ARMv6
{ "UXTH", MakeMatcher<0>("----011011111111------000111----", &Visitor::UXTH) }, // ARMv6
{ "UXTAB", MakeMatcher<0>("----01101110----------000111----", &Visitor::UXTAB) }, // ARMv6
{ "UXTAB16", MakeMatcher<0>("----01101100----------000111----", &Visitor::UXTAB16) }, // ARMv6
{ "UXTAH", MakeMatcher<0>("----01101111----------000111----", &Visitor::UXTAH) }, // ARMv6
{ "SXTB", MakeMatcher<4>("cccc011010101111ddddrr000111mmmm", &Visitor::SXTB) }, // ARMv6
{ "SXTB16", MakeMatcher<4>("cccc011010001111ddddrr000111mmmm", &Visitor::SXTB16) }, // ARMv6
{ "SXTH", MakeMatcher<4>("cccc011010111111ddddrr000111mmmm", &Visitor::SXTH) }, // ARMv6
{ "SXTAB", MakeMatcher<5>("cccc01101010nnnnddddrr000111mmmm", &Visitor::SXTAB) }, // ARMv6
{ "SXTAB16", MakeMatcher<5>("cccc01101000nnnnddddrr000111mmmm", &Visitor::SXTAB16) }, // ARMv6
{ "SXTAH", MakeMatcher<5>("cccc01101011nnnnddddrr000111mmmm", &Visitor::SXTAH) }, // ARMv6
{ "UXTB", MakeMatcher<4>("cccc011011101111ddddrr000111mmmm", &Visitor::UXTB) }, // ARMv6
{ "UXTB16", MakeMatcher<4>("cccc011011001111ddddrr000111mmmm", &Visitor::UXTB16) }, // ARMv6
{ "UXTH", MakeMatcher<4>("cccc011011111111ddddrr000111mmmm", &Visitor::UXTH) }, // ARMv6
{ "UXTAB", MakeMatcher<5>("cccc01101110nnnnddddrr000111mmmm", &Visitor::UXTAB) }, // ARMv6
{ "UXTAB16", MakeMatcher<5>("cccc01101100nnnnddddrr000111mmmm", &Visitor::UXTAB16) }, // ARMv6
{ "UXTAH", MakeMatcher<5>("cccc01101111nnnnddddrr000111mmmm", &Visitor::UXTAH) }, // ARMv6
// Hint instructions
{ "PLD", MakeMatcher<0>("111101---101----1111------------", &Visitor::PLD) }, // ARMv5E
@ -274,109 +274,109 @@ static const std::array<Instruction, 221> arm_instruction_table = {{
{ "STM (usr reg)", MakeMatcher<0>("----100--100--------------------", &Visitor::STM_usr) }, // all
// Miscellaneous instructions
{ "CLZ", MakeMatcher<0>("----000101101111----11110001----", &Visitor::CLZ) }, // ARMv5
{ "CLZ", MakeMatcher<3>("cccc000101101111dddd11110001mmmm", &Visitor::CLZ) }, // ARMv5
{ "NOP", MakeMatcher<0>("----001100100000111100000000----", &Visitor::NOP) }, // ARMv6K
{ "SEL", MakeMatcher<0>("----01101000--------11111011----", &Visitor::SEL) }, // ARMv6
{ "SEL", MakeMatcher<4>("cccc01101000nnnndddd11111011mmmm", &Visitor::SEL) }, // ARMv6
// Unsigned Sum of Absolute Differences instructions
{ "USAD8", MakeMatcher<0>("----01111000----1111----0001----", &Visitor::USAD8) }, // ARMv6
{ "USADA8", MakeMatcher<0>("----01111000------------0001----", &Visitor::USADA8) }, // ARMv6
{ "USAD8", MakeMatcher<4>("cccc01111000dddd1111mmmm0001nnnn", &Visitor::USAD8) }, // ARMv6
{ "USADA8", MakeMatcher<5>("cccc01111000ddddaaaammmm0001nnnn", &Visitor::USADA8) }, // ARMv6
// Packing instructions
{ "PKHBT", MakeMatcher<5>("cccc01101000nnnnddddvvvvv001mmmm", &Visitor::PKHBT) }, // ARMv6K
{ "PKHTB", MakeMatcher<5>("cccc01101000nnnnddddvvvvv101mmmm", &Visitor::PKHTB) }, // ARMv6K
// Reversal instructions
{ "REV", MakeMatcher<0>("----011010111111----11110011----", &Visitor::REV) }, // ARMv6
{ "REV16", MakeMatcher<0>("----011010111111----11111011----", &Visitor::REV16) }, // ARMv6
{ "REVSH", MakeMatcher<0>("----011011111111----11111011----", &Visitor::REVSH) }, // ARMv6
{ "REV", MakeMatcher<3>("cccc011010111111dddd11110011mmmm", &Visitor::REV) }, // ARMv6
{ "REV16", MakeMatcher<3>("cccc011010111111dddd11111011mmmm", &Visitor::REV16) }, // ARMv6
{ "REVSH", MakeMatcher<3>("cccc011011111111dddd11111011mmmm", &Visitor::REVSH) }, // ARMv6
// Saturation instructions
{ "SSAT", MakeMatcher<0>("----0110101---------------01----", &Visitor::SSAT) }, // ARMv6
{ "SSAT16", MakeMatcher<0>("----01101010--------11110011----", &Visitor::SSAT16) }, // ARMv6
{ "USAT", MakeMatcher<0>("----0110111---------------01----", &Visitor::USAT) }, // ARMv6
{ "USAT16", MakeMatcher<0>("----01101110--------11110011----", &Visitor::USAT16) }, // ARMv6
{ "SSAT", MakeMatcher<6>("cccc0110101vvvvvddddvvvvvr01nnnn", &Visitor::SSAT) }, // ARMv6
{ "SSAT16", MakeMatcher<4>("cccc01101010vvvvdddd11110011nnnn", &Visitor::SSAT16) }, // ARMv6
{ "USAT", MakeMatcher<6>("cccc0110111vvvvvddddvvvvvr01nnnn", &Visitor::USAT) }, // ARMv6
{ "USAT16", MakeMatcher<4>("cccc01101110vvvvdddd11110011nnnn", &Visitor::USAT16) }, // ARMv6
// Multiply (Normal) instructions
{ "MLA", MakeMatcher<0>("----0000001-------------1001----", &Visitor::MLA) }, // ARMv2
{ "MUL", MakeMatcher<0>("----0000000-----0000----1001----", &Visitor::MUL) }, // ARMv2
{ "MLA", MakeMatcher<6>("cccc0000001Sddddaaaammmm1001nnnn", &Visitor::MLA) }, // ARMv2
{ "MUL", MakeMatcher<5>("cccc0000000Sdddd0000mmmm1001nnnn", &Visitor::MUL) }, // ARMv2
// Multiply (Long) instructions
{ "SMLAL", MakeMatcher<0>("----0000111-------------1001----", &Visitor::SMLAL) }, // ARMv3M
{ "SMULL", MakeMatcher<0>("----0000110-------------1001----", &Visitor::SMULL) }, // ARMv3M
{ "UMAAL", MakeMatcher<0>("----00000100------------1001----", &Visitor::UMAAL) }, // ARMv6
{ "UMLAL", MakeMatcher<0>("----0000101-------------1001----", &Visitor::UMLAL) }, // ARMv3M
{ "UMULL", MakeMatcher<0>("----0000100-------------1001----", &Visitor::UMULL) }, // ARMv3M
{ "SMLAL", MakeMatcher<6>("cccc0000111Sddddaaaammmm1001nnnn", &Visitor::SMLAL) }, // ARMv3M
{ "SMULL", MakeMatcher<6>("cccc0000110Sddddaaaammmm1001nnnn", &Visitor::SMULL) }, // ARMv3M
{ "UMAAL", MakeMatcher<5>("cccc00000100ddddaaaammmm1001nnnn", &Visitor::UMAAL) }, // ARMv6
{ "UMLAL", MakeMatcher<6>("cccc0000101Sddddaaaammmm1001nnnn", &Visitor::UMLAL) }, // ARMv3M
{ "UMULL", MakeMatcher<6>("cccc0000100Sddddaaaammmm1001nnnn", &Visitor::UMULL) }, // ARMv3M
// Multiply (Halfword) instructions
{ "SMLALXY", MakeMatcher<0>("----00010100------------1--0----", &Visitor::SMLALxy) }, // ARMv5xP
{ "SMLAXY", MakeMatcher<0>("----00010000------------1--0----", &Visitor::SMLAxy) }, // ARMv5xP
{ "SMULXY", MakeMatcher<0>("----00010110----0000----1--0----", &Visitor::SMULxy) }, // ARMv5xP
{ "SMLALXY", MakeMatcher<7>("cccc00010100ddddaaaammmm1xy0nnnn", &Visitor::SMLALxy) }, // ARMv5xP
{ "SMLAXY", MakeMatcher<7>("cccc00010000ddddaaaammmm1xy0nnnn", &Visitor::SMLAxy) }, // ARMv5xP
{ "SMULXY", MakeMatcher<6>("cccc00010110dddd0000mmmm1xy0nnnn", &Visitor::SMULxy) }, // ARMv5xP
// Multiply (Word by Halfword) instructions
{ "SMLAWY", MakeMatcher<0>("----00010010------------1-00----", &Visitor::SMLAWy) }, // ARMv5xP
{ "SMULWY", MakeMatcher<0>("----00010010----0000----1-10----", &Visitor::SMULWy) }, // ARMv5xP
{ "SMLAWY", MakeMatcher<6>("cccc00010010ddddaaaammmm1y00nnnn", &Visitor::SMLAWy) }, // ARMv5xP
{ "SMULWY", MakeMatcher<5>("cccc00010010dddd0000mmmm1y10nnnn", &Visitor::SMULWy) }, // ARMv5xP
// Multiply (Most Significant Word) instructions
{ "SMMUL", MakeMatcher<0>("----01110101----1111----00-1----", &Visitor::SMMUL) }, // ARMv6
{ "SMMLA", MakeMatcher<0>("----01110101------------00-1----", &Visitor::SMMLA) }, // ARMv6
{ "SMMLS", MakeMatcher<0>("----01110101------------11-1----", &Visitor::SMMLS) }, // ARMv6
{ "SMMUL", MakeMatcher<5>("cccc01110101dddd1111mmmm00R1nnnn", &Visitor::SMMUL) }, // ARMv6
{ "SMMLA", MakeMatcher<6>("cccc01110101ddddaaaammmm00R1nnnn", &Visitor::SMMLA) }, // ARMv6
{ "SMMLS", MakeMatcher<6>("cccc01110101ddddaaaammmm11R1nnnn", &Visitor::SMMLS) }, // ARMv6
// Multiply (Dual) instructions
{ "SMLAD", MakeMatcher<0>("----01110000------------00-1----", &Visitor::SMLAD) }, // ARMv6
{ "SMLALD", MakeMatcher<0>("----01110100------------00-1----", &Visitor::SMLALD) }, // ARMv6
{ "SMLSD", MakeMatcher<0>("----01110000------------01-1----", &Visitor::SMLSD) }, // ARMv6
{ "SMLSLD", MakeMatcher<0>("----01110100------------01-1----", &Visitor::SMLSLD) }, // ARMv6
{ "SMUAD", MakeMatcher<0>("----01110000----1111----00-1----", &Visitor::SMUAD) }, // ARMv6
{ "SMUSD", MakeMatcher<0>("----01110000----1111----01-1----", &Visitor::SMUSD) }, // ARMv6
{ "SMLAD", MakeMatcher<6>("cccc01110000ddddaaaammmm00M1nnnn", &Visitor::SMLAD) }, // ARMv6
{ "SMLALD", MakeMatcher<6>("cccc01110100ddddaaaammmm00M1nnnn", &Visitor::SMLALD) }, // ARMv6
{ "SMLSD", MakeMatcher<6>("cccc01110000ddddaaaammmm01M1nnnn", &Visitor::SMLSD) }, // ARMv6
{ "SMLSLD", MakeMatcher<6>("cccc01110100ddddaaaammmm01M1nnnn", &Visitor::SMLSLD) }, // ARMv6
{ "SMUAD", MakeMatcher<5>("cccc01110000dddd1111mmmm00M1nnnn", &Visitor::SMUAD) }, // ARMv6
{ "SMUSD", MakeMatcher<5>("cccc01110000dddd1111mmmm01M1nnnn", &Visitor::SMUSD) }, // ARMv6
// Parallel Add/Subtract (Modulo) instructions
{ "SADD8", MakeMatcher<0>("----01100001--------11111001----", &Visitor::SADD8) }, // ARMv6
{ "SADD16", MakeMatcher<0>("----01100001--------11110001----", &Visitor::SADD16) }, // ARMv6
{ "SASX", MakeMatcher<0>("----01100001--------11110011----", &Visitor::SASX) }, // ARMv6
{ "SSAX", MakeMatcher<0>("----01100001--------11110101----", &Visitor::SSAX) }, // ARMv6
{ "SSUB8", MakeMatcher<0>("----01100001--------11111111----", &Visitor::SSUB8) }, // ARMv6
{ "SSUB16", MakeMatcher<0>("----01100001--------11110111----", &Visitor::SSUB16) }, // ARMv6
{ "UADD8", MakeMatcher<0>("----01100101--------11111001----", &Visitor::UADD8) }, // ARMv6
{ "UADD16", MakeMatcher<0>("----01100101--------11110001----", &Visitor::UADD16) }, // ARMv6
{ "UASX", MakeMatcher<0>("----01100101--------11110011----", &Visitor::UASX) }, // ARMv6
{ "USAX", MakeMatcher<0>("----01100101--------11110101----", &Visitor::USAX) }, // ARMv6
{ "USUB8", MakeMatcher<0>("----01100101--------11111111----", &Visitor::USUB8) }, // ARMv6
{ "USUB16", MakeMatcher<0>("----01100101--------11110111----", &Visitor::USUB16) }, // ARMv6
{ "SADD8", MakeMatcher<4>("cccc01100001nnnndddd11111001mmmm", &Visitor::SADD8) }, // ARMv6
{ "SADD16", MakeMatcher<4>("cccc01100001nnnndddd11110001mmmm", &Visitor::SADD16) }, // ARMv6
{ "SASX", MakeMatcher<4>("cccc01100001nnnndddd11110011mmmm", &Visitor::SASX) }, // ARMv6
{ "SSAX", MakeMatcher<4>("cccc01100001nnnndddd11110101mmmm", &Visitor::SSAX) }, // ARMv6
{ "SSUB8", MakeMatcher<4>("cccc01100001nnnndddd11111111mmmm", &Visitor::SSUB8) }, // ARMv6
{ "SSUB16", MakeMatcher<4>("cccc01100001nnnndddd11110111mmmm", &Visitor::SSUB16) }, // ARMv6
{ "UADD8", MakeMatcher<4>("cccc01100101nnnndddd11111001mmmm", &Visitor::UADD8) }, // ARMv6
{ "UADD16", MakeMatcher<4>("cccc01100101nnnndddd11110001mmmm", &Visitor::UADD16) }, // ARMv6
{ "UASX", MakeMatcher<4>("cccc01100101nnnndddd11110011mmmm", &Visitor::UASX) }, // ARMv6
{ "USAX", MakeMatcher<4>("cccc01100101nnnndddd11110101mmmm", &Visitor::USAX) }, // ARMv6
{ "USUB8", MakeMatcher<4>("cccc01100101nnnndddd11111111mmmm", &Visitor::USUB8) }, // ARMv6
{ "USUB16", MakeMatcher<4>("cccc01100101nnnndddd11110111mmmm", &Visitor::USUB16) }, // ARMv6
// Parallel Add/Subtract (Saturating) instructions
{ "QADD8", MakeMatcher<0>("----01100010--------11111001----", &Visitor::QADD8) }, // ARMv6
{ "QADD16", MakeMatcher<0>("----01100010--------11110001----", &Visitor::QADD16) }, // ARMv6
{ "QASX", MakeMatcher<0>("----01100010--------11110011----", &Visitor::QASX) }, // ARMv6
{ "QSAX", MakeMatcher<0>("----01100010--------11110101----", &Visitor::QSAX) }, // ARMv6
{ "QSUB8", MakeMatcher<0>("----01100010--------11111111----", &Visitor::QSUB8) }, // ARMv6
{ "QSUB16", MakeMatcher<0>("----01100010--------11110111----", &Visitor::QSUB16) }, // ARMv6
{ "UQADD8", MakeMatcher<0>("----01100110--------11111001----", &Visitor::UQADD8) }, // ARMv6
{ "UQADD16", MakeMatcher<0>("----01100110--------11110001----", &Visitor::UQADD16) }, // ARMv6
{ "UQASX", MakeMatcher<0>("----01100110--------11110011----", &Visitor::UQASX) }, // ARMv6
{ "UQSAX", MakeMatcher<0>("----01100110--------11110101----", &Visitor::UQSAX) }, // ARMv6
{ "UQSUB8", MakeMatcher<0>("----01100110--------11111111----", &Visitor::UQSUB8) }, // ARMv6
{ "UQSUB16", MakeMatcher<0>("----01100110--------11110111----", &Visitor::UQSUB16) }, // ARMv6
{ "QADD8", MakeMatcher<4>("cccc01100010nnnndddd11111001mmmm", &Visitor::QADD8) }, // ARMv6
{ "QADD16", MakeMatcher<4>("cccc01100010nnnndddd11110001mmmm", &Visitor::QADD16) }, // ARMv6
{ "QASX", MakeMatcher<4>("cccc01100010nnnndddd11110011mmmm", &Visitor::QASX) }, // ARMv6
{ "QSAX", MakeMatcher<4>("cccc01100010nnnndddd11110101mmmm", &Visitor::QSAX) }, // ARMv6
{ "QSUB8", MakeMatcher<4>("cccc01100010nnnndddd11111111mmmm", &Visitor::QSUB8) }, // ARMv6
{ "QSUB16", MakeMatcher<4>("cccc01100010nnnndddd11110111mmmm", &Visitor::QSUB16) }, // ARMv6
{ "UQADD8", MakeMatcher<4>("cccc01100110nnnndddd11111001mmmm", &Visitor::UQADD8) }, // ARMv6
{ "UQADD16", MakeMatcher<4>("cccc01100110nnnndddd11110001mmmm", &Visitor::UQADD16) }, // ARMv6
{ "UQASX", MakeMatcher<4>("cccc01100110nnnndddd11110011mmmm", &Visitor::UQASX) }, // ARMv6
{ "UQSAX", MakeMatcher<4>("cccc01100110nnnndddd11110101mmmm", &Visitor::UQSAX) }, // ARMv6
{ "UQSUB8", MakeMatcher<4>("cccc01100110nnnndddd11111111mmmm", &Visitor::UQSUB8) }, // ARMv6
{ "UQSUB16", MakeMatcher<4>("cccc01100110nnnndddd11110111mmmm", &Visitor::UQSUB16) }, // ARMv6
// Parallel Add/Subtract (Halving) instructions
{ "SHADD8", MakeMatcher<0>("----01100011--------11111001----", &Visitor::SHADD8) }, // ARMv6
{ "SHADD16", MakeMatcher<0>("----01100011--------11110001----", &Visitor::SHADD16) }, // ARMv6
{ "SHASX", MakeMatcher<0>("----01100011--------11110011----", &Visitor::SHASX) }, // ARMv6
{ "SHSAX", MakeMatcher<0>("----01100011--------11110101----", &Visitor::SHSAX) }, // ARMv6
{ "SHSUB8", MakeMatcher<0>("----01100011--------11111111----", &Visitor::SHSUB8) }, // ARMv6
{ "SHSUB16", MakeMatcher<0>("----01100011--------11110111----", &Visitor::SHSUB16) }, // ARMv6
{ "UHADD8", MakeMatcher<0>("----01100111--------11111001----", &Visitor::UHADD8) }, // ARMv6
{ "UHADD16", MakeMatcher<0>("----01100111--------11110001----", &Visitor::UHADD16) }, // ARMv6
{ "UHASX", MakeMatcher<0>("----01100111--------11110011----", &Visitor::UHASX) }, // ARMv6
{ "UHSAX", MakeMatcher<0>("----01100111--------11110101----", &Visitor::UHSAX) }, // ARMv6
{ "UHSUB8", MakeMatcher<0>("----01100111--------11111111----", &Visitor::UHSUB8) }, // ARMv6
{ "UHSUB16", MakeMatcher<0>("----01100111--------11110111----", &Visitor::UHSUB16) }, // ARMv6
{ "SHADD8", MakeMatcher<4>("cccc01100011nnnndddd11111001mmmm", &Visitor::SHADD8) }, // ARMv6
{ "SHADD16", MakeMatcher<4>("cccc01100011nnnndddd11110001mmmm", &Visitor::SHADD16) }, // ARMv6
{ "SHASX", MakeMatcher<4>("cccc01100011nnnndddd11110011mmmm", &Visitor::SHASX) }, // ARMv6
{ "SHSAX", MakeMatcher<4>("cccc01100011nnnndddd11110101mmmm", &Visitor::SHSAX) }, // ARMv6
{ "SHSUB8", MakeMatcher<4>("cccc01100011nnnndddd11111111mmmm", &Visitor::SHSUB8) }, // ARMv6
{ "SHSUB16", MakeMatcher<4>("cccc01100011nnnndddd11110111mmmm", &Visitor::SHSUB16) }, // ARMv6
{ "UHADD8", MakeMatcher<4>("cccc01100111nnnndddd11111001mmmm", &Visitor::UHADD8) }, // ARMv6
{ "UHADD16", MakeMatcher<4>("cccc01100111nnnndddd11110001mmmm", &Visitor::UHADD16) }, // ARMv6
{ "UHASX", MakeMatcher<4>("cccc01100111nnnndddd11110011mmmm", &Visitor::UHASX) }, // ARMv6
{ "UHSAX", MakeMatcher<4>("cccc01100111nnnndddd11110101mmmm", &Visitor::UHSAX) }, // ARMv6
{ "UHSUB8", MakeMatcher<4>("cccc01100111nnnndddd11111111mmmm", &Visitor::UHSUB8) }, // ARMv6
{ "UHSUB16", MakeMatcher<4>("cccc01100111nnnndddd11110111mmmm", &Visitor::UHSUB16) }, // ARMv6
// Saturated Add/Subtract instructions
{ "QADD", MakeMatcher<0>("----00010000--------00000101----", &Visitor::QADD) }, // ARMv5xP
{ "QSUB", MakeMatcher<0>("----00010010--------00000101----", &Visitor::QSUB) }, // ARMv5xP
{ "QDADD", MakeMatcher<0>("----00010100--------00000101----", &Visitor::QDADD) }, // ARMv5xP
{ "QDSUB", MakeMatcher<0>("----00010110--------00000101----", &Visitor::QDSUB) }, // ARMv5xP
{ "QADD", MakeMatcher<4>("cccc00010000nnnndddd00000101mmmm", &Visitor::QADD) }, // ARMv5xP
{ "QSUB", MakeMatcher<4>("cccc00010010nnnndddd00000101mmmm", &Visitor::QSUB) }, // ARMv5xP
{ "QDADD", MakeMatcher<4>("cccc00010100nnnndddd00000101mmmm", &Visitor::QDADD) }, // ARMv5xP
{ "QDSUB", MakeMatcher<4>("cccc00010110nnnndddd00000101mmmm", &Visitor::QDSUB) }, // ARMv5xP
// Status Register Access instructions
{ "CPS", MakeMatcher<0>("111100010000---00000000---0-----", &Visitor::CPS) }, // ARMv6
@ -395,4 +395,4 @@ boost::optional<const Instruction&> DecodeArm(u32 i) {
return iterator != arm_instruction_table.cend() ? boost::make_optional<const Instruction&>(*iterator) : boost::none;
}
};
} // namespace ArmDecoder

171
src/core/arm/decoder/decoder.h
View File

@ -60,6 +60,7 @@ using Imm24 = u32;
using Register = int;
using RegisterList = u16;
using ShiftType = int;
using SignExtendRotation = int;
class Visitor {
public:
@ -138,18 +139,18 @@ public:
virtual void UDF() = 0;
// Extension functions
virtual void SXTAB() = 0;
virtual void SXTAB16() = 0;
virtual void SXTAH() = 0;
virtual void SXTB() = 0;
virtual void SXTB16() = 0;
virtual void SXTH() = 0;
virtual void UXTAB() = 0;
virtual void UXTAB16() = 0;
virtual void UXTAH() = 0;
virtual void UXTB() = 0;
virtual void UXTB16() = 0;
virtual void UXTH() = 0;
virtual void SXTAB(Cond cond, Register Rn, Register Rd, SignExtendRotation rotate, Register Rm) = 0;
virtual void SXTAB16(Cond cond, Register Rn, Register Rd, SignExtendRotation rotate, Register Rm) = 0;
virtual void SXTAH(Cond cond, Register Rn, Register Rd, SignExtendRotation rotate, Register Rm) = 0;
virtual void SXTB(Cond cond, Register Rd, SignExtendRotation rotate, Register Rm) = 0;
virtual void SXTB16(Cond cond, Register Rd, SignExtendRotation rotate, Register Rm) = 0;
virtual void SXTH(Cond cond, Register Rd, SignExtendRotation rotate, Register Rm) = 0;
virtual void UXTAB(Cond cond, Register Rn, Register Rd, SignExtendRotation rotate, Register Rm) = 0;
virtual void UXTAB16(Cond cond, Register Rn, Register Rd, SignExtendRotation rotate, Register Rm) = 0;
virtual void UXTAH(Cond cond, Register Rn, Register Rd, SignExtendRotation rotate, Register Rm) = 0;
virtual void UXTB(Cond cond, Register Rd, SignExtendRotation rotate, Register Rm) = 0;
virtual void UXTB16(Cond cond, Register Rd, SignExtendRotation rotate, Register Rm) = 0;
virtual void UXTH(Cond cond, Register Rd, SignExtendRotation rotate, Register Rm) = 0;
// Hint instructions
virtual void PLD() = 0;
@ -196,109 +197,109 @@ public:
virtual void STM_usr() = 0;
// Miscellaneous instructions
virtual void CLZ() = 0;
virtual void CLZ(Cond cond, Register Rd, Register Rm) = 0;
virtual void NOP() = 0;
virtual void SEL() = 0;
virtual void SEL(Cond cond, Register Rn, Register Rd, Register Rm) = 0;
// Unsigned sum of absolute difference functions
virtual void USAD8() = 0;
virtual void USADA8() = 0;
virtual void USAD8(Cond cond, Register Rd, Register Rm, Register Rn) = 0;
virtual void USADA8(Cond cond, Register Rd, Register Ra, Register Rm, Register Rn) = 0;
// Packing instructions
virtual void PKHBT(Cond cond, Register Rn, Register Rd, Imm5 imm5, Register Rm) = 0;
virtual void PKHTB(Cond cond, Register Rn, Register Rd, Imm5 imm5, Register Rm) = 0;
// Reversal instructions
virtual void REV() = 0;
virtual void REV16() = 0;
virtual void REVSH() = 0;
virtual void REV(Cond cond, Register Rd, Register Rm) = 0;
virtual void REV16(Cond cond, Register Rd, Register Rm) = 0;
virtual void REVSH(Cond cond, Register Rd, Register Rm) = 0;
// Saturation instructions
virtual void SSAT() = 0;
virtual void SSAT16() = 0;
virtual void USAT() = 0;
virtual void USAT16() = 0;
virtual void SSAT(Cond cond, Imm5 sat_imm, Register Rd, Imm5 imm5, bool sh, Register Rn) = 0;
virtual void SSAT16(Cond cond, Imm4 sat_imm, Register Rd, Register Rn) = 0;
virtual void USAT(Cond cond, Imm5 sat_imm, Register Rd, Imm5 imm5, bool sh, Register Rn) = 0;
virtual void USAT16(Cond cond, Imm4 sat_imm, Register Rd, Register Rn) = 0;
// Multiply (Normal) instructions
virtual void MLA() = 0;
virtual void MUL() = 0;
virtual void MLA(Cond cond, bool S, Register Rd, Register Ra, Register Rm, Register Rn) = 0;
virtual void MUL(Cond cond, bool S, Register Rd, Register Rm, Register Rn) = 0;
// Multiply (Long) instructions
virtual void SMLAL() = 0;
virtual void SMULL() = 0;
virtual void UMAAL() = 0;
virtual void UMLAL() = 0;
virtual void UMULL() = 0;
virtual void SMLAL(Cond cond, bool S, Register RdHi, Register RdLo, Register Rm, Register Rn) = 0;
virtual void SMULL(Cond cond, bool S, Register RdHi, Register RdLo, Register Rm, Register Rn) = 0;
virtual void UMAAL(Cond cond, Register RdHi, Register RdLo, Register Rm, Register Rn) = 0;
virtual void UMLAL(Cond cond, bool S, Register RdHi, Register RdLo, Register Rm, Register Rn) = 0;
virtual void UMULL(Cond cond, bool S, Register RdHi, Register RdLo, Register Rm, Register Rn) = 0;
// Multiply (Halfword) instructions
virtual void SMLALxy() = 0;
virtual void SMLAxy() = 0;
virtual void SMULxy() = 0;
virtual void SMLALxy(Cond cond, Register RdHi, Register RdLo, Register Rm, bool M, bool N, Register Rn) = 0;
virtual void SMLAxy(Cond cond, Register Rd, Register Ra, Register Rm, bool M, bool N, Register Rn) = 0;
virtual void SMULxy(Cond cond, Register Rd, Register Rm, bool M, bool N, Register Rn) = 0;
// Multiply (word by halfword) instructions
virtual void SMLAWy() = 0;
virtual void SMULWy() = 0;
virtual void SMLAWy(Cond cond, Register Rd, Register Ra, Register Rm, bool M, Register Rn) = 0;
virtual void SMULWy(Cond cond, Register Rd, Register Rm, bool M, Register Rn) = 0;
// Multiply (Most significant word) instructions
virtual void SMMLA() = 0;
virtual void SMMLS() = 0;
virtual void SMMUL() = 0;
virtual void SMMLA(Cond cond, Register Rd, Register Ra, Register Rm, bool R, Register Rn) = 0;
virtual void SMMLS(Cond cond, Register Rd, Register Ra, Register Rm, bool R, Register Rn) = 0;
virtual void SMMUL(Cond cond, Register Rd, Register Rm, bool R, Register Rn) = 0;
// Multiply (Dual) instructions
virtual void SMLAD() = 0;
virtual void SMLALD() = 0;
virtual void SMLSD() = 0;
virtual void SMLSLD() = 0;
virtual void SMUAD() = 0;
virtual void SMUSD() = 0;
virtual void SMLAD(Cond cond, Register Rd, Register Ra, Register Rm, bool M, Register Rn) = 0;
virtual void SMLALD(Cond cond, Register RdHi, Register RdLo, Register Rm, bool M, Register Rn) = 0;
virtual void SMLSD(Cond cond, Register Rd, Register Ra, Register Rm, bool M, Register Rn) = 0;
virtual void SMLSLD(Cond cond, Register RdHi, Register RdLo, Register Rm, bool M, Register Rn) = 0;
virtual void SMUAD(Cond cond, Register Rd, Register Rm, bool M, Register Rn) = 0;
virtual void SMUSD(Cond cond, Register Rd, Register Rm, bool M, Register Rn) = 0;
// Parallel Add/Subtract (Modulo arithmetic) instructions
virtual void SADD8() = 0;
virtual void SADD16() = 0;
virtual void SASX() = 0;
virtual void SSAX() = 0;
virtual void SSUB8() = 0;
virtual void SSUB16() = 0;
virtual void UADD8() = 0;
virtual void UADD16() = 0;
virtual void UASX() = 0;
virtual void USAX() = 0;
virtual void USUB8() = 0;
virtual void USUB16() = 0;
virtual void SADD8(Cond cond, Register Rn, Register Rd, Register Rm) = 0;
virtual void SADD16(Cond cond, Register Rn, Register Rd, Register Rm) = 0;
virtual void SASX(Cond cond, Register Rn, Register Rd, Register Rm) = 0;
virtual void SSAX(Cond cond, Register Rn, Register Rd, Register Rm) = 0;
virtual void SSUB8(Cond cond, Register Rn, Register Rd, Register Rm) = 0;
virtual void SSUB16(Cond cond, Register Rn, Register Rd, Register Rm) = 0;
virtual void UADD8(Cond cond, Register Rn, Register Rd, Register Rm) = 0;
virtual void UADD16(Cond cond, Register Rn, Register Rd, Register Rm) = 0;
virtual void UASX(Cond cond, Register Rn, Register Rd, Register Rm) = 0;
virtual void USAX(Cond cond, Register Rn, Register Rd, Register Rm) = 0;
virtual void USUB8(Cond cond, Register Rn, Register Rd, Register Rm) = 0;
virtual void USUB16(Cond cond, Register Rn, Register Rd, Register Rm) = 0;
// Parallel Add/Subtract (Saturating) instructions
virtual void QADD8() = 0;
virtual void QADD16() = 0;
virtual void QASX() = 0;
virtual void QSAX() = 0;
virtual void QSUB8() = 0;
virtual void QSUB16() = 0;
virtual void UQADD8() = 0;
virtual void UQADD16() = 0;
virtual void UQASX() = 0;
virtual void UQSAX() = 0;
virtual void UQSUB8() = 0;
virtual void UQSUB16() = 0;
virtual void QADD8(Cond cond, Register Rn, Register Rd, Register Rm) = 0;
virtual void QADD16(Cond cond, Register Rn, Register Rd, Register Rm) = 0;
virtual void QASX(Cond cond, Register Rn, Register Rd, Register Rm) = 0;
virtual void QSAX(Cond cond, Register Rn, Register Rd, Register Rm) = 0;
virtual void QSUB8(Cond cond, Register Rn, Register Rd, Register Rm) = 0;
virtual void QSUB16(Cond cond, Register Rn, Register Rd, Register Rm) = 0;
virtual void UQADD8(Cond cond, Register Rn, Register Rd, Register Rm) = 0;
virtual void UQADD16(Cond cond, Register Rn, Register Rd, Register Rm) = 0;
virtual void UQASX(Cond cond, Register Rn, Register Rd, Register Rm) = 0;
virtual void UQSAX(Cond cond, Register Rn, Register Rd, Register Rm) = 0;
virtual void UQSUB8(Cond cond, Register Rn, Register Rd, Register Rm) = 0;
virtual void UQSUB16(Cond cond, Register Rn, Register Rd, Register Rm) = 0;
// Parallel Add/Subtract (Halving) instructions
virtual void SHADD8() = 0;
virtual void SHADD16() = 0;
virtual void SHASX() = 0;
virtual void SHSAX() = 0;
virtual void SHSUB8() = 0;
virtual void SHSUB16() = 0;
virtual void UHADD8() = 0;
virtual void UHADD16() = 0;
virtual void UHASX() = 0;
virtual void UHSAX() = 0;
virtual void UHSUB8() = 0;
virtual void UHSUB16() = 0;
virtual void SHADD8(Cond cond, Register Rn, Register Rd, Register Rm) = 0;
virtual void SHADD16(Cond cond, Register Rn, Register Rd, Register Rm) = 0;
virtual void SHASX(Cond cond, Register Rn, Register Rd, Register Rm) = 0;
virtual void SHSAX(Cond cond, Register Rn, Register Rd, Register Rm) = 0;
virtual void SHSUB8(Cond cond, Register Rn, Register Rd, Register Rm) = 0;
virtual void SHSUB16(Cond cond, Register Rn, Register Rd, Register Rm) = 0;
virtual void UHADD8(Cond cond, Register Rn, Register Rd, Register Rm) = 0;
virtual void UHADD16(Cond cond, Register Rn, Register Rd, Register Rm) = 0;
virtual void UHASX(Cond cond, Register Rn, Register Rd, Register Rm) = 0;
virtual void UHSAX(Cond cond, Register Rn, Register Rd, Register Rm) = 0;
virtual void UHSUB8(Cond cond, Register Rn, Register Rd, Register Rm) = 0;
virtual void UHSUB16(Cond cond, Register Rn, Register Rd, Register Rm) = 0;
// Saturated Add/Subtract instructions
virtual void QADD() = 0;
virtual void QSUB() = 0;
virtual void QDADD() = 0;
virtual void QDSUB() = 0;
virtual void QADD(Cond cond, Register Rn, Register Rd, Register Rm) = 0;
virtual void QSUB(Cond cond, Register Rn, Register Rd, Register Rm) = 0;
virtual void QDADD(Cond cond, Register Rn, Register Rd, Register Rm) = 0;
virtual void QDSUB(Cond cond, Register Rn, Register Rd, Register Rm) = 0;
// Synchronization Primitive instructions
virtual void CLREX() = 0;
@ -328,4 +329,4 @@ public:
virtual void thumb_BLX_suffix(bool X, Imm11 imm11) = 0;
};
};
} // namespace ArmDecoder

16
src/core/arm/decoder/thumb.cpp
View File

@ -181,7 +181,7 @@ static const std::array<Instruction, 27> thumb_instruction_table = { {
v->ORR_reg(0xE, /*S=*/true, Rd_Rn, Rd_Rn, 0, 0, Rm_Rs);
break;
case 13: // MUL Rd, Rm
v->MUL();
v->MUL(0xE, /*S=*/true, Rd_Rn, Rd_Rn, Rm_Rs);
break;
case 14: // BIC Rm, Rd
v->BIC_reg(0xE, /*S=*/true, Rd_Rn, Rd_Rn, 0, 0, Rm_Rs);
@ -331,16 +331,16 @@ static const std::array<Instruction, 27> thumb_instruction_table = { {
Register Rd = bits<0, 2>(instruction);
switch (opc) {
case 0: // SXTH Rd, Rm
v->SXTH();
v->SXTH(0xE, Rd, 0, Rm);
break;
case 1: // SXTB Rd, Rm
v->SXTB();
v->SXTB(0xE, Rd, 0, Rm);
break;
case 2: // UXTH Rd, Rm
v->UXTH();
v->UXTH(0xE, Rd, 0, Rm);
break;
case 3: // UXTB Rd, Rm
v->UXTB();
v->UXTB(0xE, Rd, 0, Rm);
break;
default:
UNREACHABLE();
@ -377,16 +377,16 @@ static const std::array<Instruction, 27> thumb_instruction_table = { {
Register Rd = bits<0, 2>(instruction);
switch (opc) {
case 0: // REV Rd, Rn
v->REV();
v->REV(0xE, Rd, Rn);
break;
case 1: // REV16 Rd, Rn
v->REV16();
v->REV16(0xE, Rd, Rn);
break;
case 2: // undefined
v->UDF();
break;
case 3: // REVSH Rd, Rn
v->REVSH();
v->REVSH(0xE, Rd, Rn);
break;
default:
UNREACHABLE();

1
src/core/arm/jit_x64/common.h
View File

@ -21,6 +21,7 @@ using ArmImm12 = ArmDecoder::Imm12;
using ArmImm24 = ArmDecoder::Imm24;
using Cond = ArmDecoder::Cond;
using ShiftType = ArmDecoder::ShiftType;
using SignExtendRotation = ArmDecoder::SignExtendRotation;
struct JitState {
JitState() : cpu_state(PrivilegeMode::USER32MODE) {}

2
src/core/arm/jit_x64/instructions/branch.cpp
View File

@ -122,4 +122,4 @@ void JitX64::BXJ(Cond cond, ArmReg Rm) {
BX(cond, Rm);
}
}
} // namespace JitX64

2
src/core/arm/jit_x64/instructions/coprocessor.cpp
View File

@ -14,4 +14,4 @@ void JitX64::MRC() { CompileInterpretInstruction(); }
void JitX64::MRRC() { CompileInterpretInstruction(); }
void JitX64::STC() { CompileInterpretInstruction(); }
}
} // namespace JitX64

2
src/core/arm/jit_x64/instructions/exception_generating.cpp
View File

@ -65,4 +65,4 @@ void JitX64::UDF() {
current.arm_pc += GetInstSize();
}
}
} // namespace JitX64

26
src/core/arm/jit_x64/instructions/extension.cpp
View File

@ -6,17 +6,17 @@
namespace JitX64 {
void JitX64::SXTAB() { CompileInterpretInstruction(); }
void JitX64::SXTAB16() { CompileInterpretInstruction(); }
void JitX64::SXTAH() { CompileInterpretInstruction(); }
void JitX64::SXTB() { CompileInterpretInstruction(); }
void JitX64::SXTB16() { CompileInterpretInstruction(); }
void JitX64::SXTH() { CompileInterpretInstruction(); }
void JitX64::UXTAB() { CompileInterpretInstruction(); }
void JitX64::UXTAB16() { CompileInterpretInstruction(); }
void JitX64::UXTAH() { CompileInterpretInstruction(); }
void JitX64::UXTB() { CompileInterpretInstruction(); }
void JitX64::UXTB16() { CompileInterpretInstruction(); }
void JitX64::UXTH() { CompileInterpretInstruction(); }
void JitX64::SXTAB(Cond cond, ArmReg Rn, ArmReg Rd, SignExtendRotation rotate, ArmReg Rm) { CompileInterpretInstruction(); }
void JitX64::SXTAB16(Cond cond, ArmReg Rn, ArmReg Rd, SignExtendRotation rotate, ArmReg Rm) { CompileInterpretInstruction(); }
void JitX64::SXTAH(Cond cond, ArmReg Rn, ArmReg Rd, SignExtendRotation rotate, ArmReg Rm) { CompileInterpretInstruction(); }
void JitX64::SXTB(Cond cond, ArmReg Rd, SignExtendRotation rotate, ArmReg Rm) { CompileInterpretInstruction(); }
void JitX64::SXTB16(Cond cond, ArmReg Rd, SignExtendRotation rotate, ArmReg Rm) { CompileInterpretInstruction(); }
void JitX64::SXTH(Cond cond, ArmReg Rd, SignExtendRotation rotate, ArmReg Rm) { CompileInterpretInstruction(); }
void JitX64::UXTAB(Cond cond, ArmReg Rn, ArmReg Rd, SignExtendRotation rotate, ArmReg Rm) { CompileInterpretInstruction(); }
void JitX64::UXTAB16(Cond cond, ArmReg Rn, ArmReg Rd, SignExtendRotation rotate, ArmReg Rm) { CompileInterpretInstruction(); }
void JitX64::UXTAH(Cond cond, ArmReg Rn, ArmReg Rd, SignExtendRotation rotate, ArmReg Rm) { CompileInterpretInstruction(); }
void JitX64::UXTB(Cond cond, ArmReg Rd, SignExtendRotation rotate, ArmReg Rm) { CompileInterpretInstruction(); }
void JitX64::UXTB16(Cond cond, ArmReg Rd, SignExtendRotation rotate, ArmReg Rm) { CompileInterpretInstruction(); }
void JitX64::UXTH(Cond cond, ArmReg Rd, SignExtendRotation rotate, ArmReg Rm) { CompileInterpretInstruction(); }
}
} // namespace JitX64

2
src/core/arm/jit_x64/instructions/hint.cpp
View File

@ -12,4 +12,4 @@ void JitX64::WFI() { CompileInterpretInstruction(); }
void JitX64::WFE() { CompileInterpretInstruction(); }
void JitX64::YIELD() { CompileInterpretInstruction(); }
}
} // namespace JitX64

2
src/core/arm/jit_x64/instructions/load_store.cpp
View File

@ -1031,4 +1031,4 @@ void JitX64::LDM_usr() { CompileInterpretInstruction(); }
void JitX64::LDM_eret() { CompileInterpretInstruction(); }
void JitX64::STM_usr() { CompileInterpretInstruction(); }
}
} // namespace JitX64

6
src/core/arm/jit_x64/instructions/misc.cpp
View File

@ -6,8 +6,8 @@
namespace JitX64 {
void JitX64::CLZ() { CompileInterpretInstruction(); }
void JitX64::CLZ(Cond cond, ArmReg Rd, ArmReg Rm) { CompileInterpretInstruction(); }
void JitX64::NOP() { CompileInterpretInstruction(); }
void JitX64::SEL() { CompileInterpretInstruction(); }
void JitX64::SEL(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) { CompileInterpretInstruction(); }
}
} // namespace JitX64

44
src/core/arm/jit_x64/instructions/multiply.cpp
View File

@ -7,36 +7,36 @@
namespace JitX64 {
// Multiply (Normal) instructions
void JitX64::MLA() { CompileInterpretInstruction(); }
void JitX64::MUL() { CompileInterpretInstruction(); }
void JitX64::MLA(Cond cond, bool S, ArmReg Rd, ArmReg Ra, ArmReg Rm, ArmReg Rn) { CompileInterpretInstruction(); }
void JitX64::MUL(Cond cond, bool S, ArmReg Rd, ArmReg Rm, ArmReg Rn) { CompileInterpretInstruction(); }
// Multiply (Long) instructions
void JitX64::SMLAL() { CompileInterpretInstruction(); }
void JitX64::SMULL() { CompileInterpretInstruction(); }
void JitX64::UMAAL() { CompileInterpretInstruction(); }
void JitX64::UMLAL() { CompileInterpretInstruction(); }
void JitX64::UMULL() { CompileInterpretInstruction(); }
void JitX64::SMLAL(Cond cond, bool S, ArmReg RdHi, ArmReg RdLo, ArmReg Rm, ArmReg Rn) { CompileInterpretInstruction(); }
void JitX64::SMULL(Cond cond, bool S, ArmReg RdHi, ArmReg RdLo, ArmReg Rm, ArmReg Rn) { CompileInterpretInstruction(); }
void JitX64::UMAAL(Cond cond, ArmReg RdHi, ArmReg RdLo, ArmReg Rm, ArmReg Rn) { CompileInterpretInstruction(); }
void JitX64::UMLAL(Cond cond, bool S, ArmReg RdHi, ArmReg RdLo, ArmReg Rm, ArmReg Rn) { CompileInterpretInstruction(); }
void JitX64::UMULL(Cond cond, bool S, ArmReg RdHi, ArmReg RdLo, ArmReg Rm, ArmReg Rn) { CompileInterpretInstruction(); }
// Multiply (Halfword) instructions
void JitX64::SMLALxy() { CompileInterpretInstruction(); }
void JitX64::SMLAxy() { CompileInterpretInstruction(); }
void JitX64::SMULxy() { CompileInterpretInstruction(); }
void JitX64::SMLALxy(Cond cond, ArmReg RdHi, ArmReg RdLo, ArmReg Rm, bool M, bool N, ArmReg Rn) { CompileInterpretInstruction(); }
void JitX64::SMLAxy(Cond cond, ArmReg Rd, ArmReg Ra, ArmReg Rm, bool M, bool N, ArmReg Rn) { CompileInterpretInstruction(); }
void JitX64::SMULxy(Cond cond, ArmReg Rd, ArmReg Rm, bool M, bool N, ArmReg Rn) { CompileInterpretInstruction(); }
// Multiply (word by halfword) instructions
void JitX64::SMLAWy() { CompileInterpretInstruction(); }
void JitX64::SMULWy() { CompileInterpretInstruction(); }
void JitX64::SMLAWy(Cond cond, ArmReg Rd, ArmReg Ra, ArmReg Rm, bool M, ArmReg Rn) { CompileInterpretInstruction(); }
void JitX64::SMULWy(Cond cond, ArmReg Rd, ArmReg Rm, bool M, ArmReg Rn) { CompileInterpretInstruction(); }
// Multiply (Most significant word) instructions
void JitX64::SMMLA() { CompileInterpretInstruction(); }
void JitX64::SMMLS() { CompileInterpretInstruction(); }
void JitX64::SMMUL() { CompileInterpretInstruction(); }
void JitX64::SMMLA(Cond cond, ArmReg Rd, ArmReg Ra, ArmReg Rm, bool R, ArmReg Rn) { CompileInterpretInstruction(); }
void JitX64::SMMLS(Cond cond, ArmReg Rd, ArmReg Ra, ArmReg Rm, bool R, ArmReg Rn) { CompileInterpretInstruction(); }
void JitX64::SMMUL(Cond cond, ArmReg Rd, ArmReg Rm, bool R, ArmReg Rn) { CompileInterpretInstruction(); }
// Multiply (Dual) instructions
void JitX64::SMLAD() { CompileInterpretInstruction(); }
void JitX64::SMLALD() { CompileInterpretInstruction(); }
void JitX64::SMLSD() { CompileInterpretInstruction(); }
void JitX64::SMLSLD() { CompileInterpretInstruction(); }
void JitX64::SMUAD() { CompileInterpretInstruction(); }
void JitX64::SMUSD() { CompileInterpretInstruction(); }
void JitX64::SMLAD(Cond cond, ArmReg Rd, ArmReg Ra, ArmReg Rm, bool M, ArmReg Rn) { CompileInterpretInstruction(); }
void JitX64::SMLALD(Cond cond, ArmReg RdHi, ArmReg RdLo, ArmReg Rm, bool M, ArmReg Rn) { CompileInterpretInstruction(); }
void JitX64::SMLSD(Cond cond, ArmReg Rd, ArmReg Ra, ArmReg Rm, bool M, ArmReg Rn) { CompileInterpretInstruction(); }
void JitX64::SMLSLD(Cond cond, ArmReg RdHi, ArmReg RdLo, ArmReg Rm, bool M, ArmReg Rn) { CompileInterpretInstruction(); }
void JitX64::SMUAD(Cond cond, ArmReg Rd, ArmReg Rm, bool M, ArmReg Rn) { CompileInterpretInstruction(); }
void JitX64::SMUSD(Cond cond, ArmReg Rd, ArmReg Rm, bool M, ArmReg Rn) { CompileInterpretInstruction(); }
}
} // namespace JitX64

2
src/core/arm/jit_x64/instructions/packing.cpp
View File

@ -9,4 +9,4 @@ namespace JitX64 {
void JitX64::PKHBT(Cond cond, ArmReg Rn, ArmReg Rd, ArmImm5 imm5, ArmReg Rm) { CompileInterpretInstruction(); }
void JitX64::PKHTB(Cond cond, ArmReg Rn, ArmReg Rd, ArmImm5 imm5, ArmReg Rm) { CompileInterpretInstruction(); }
}
} // namespace JitX64

26
src/core/arm/jit_x64/instructions/parallel_add_subtract_halving.cpp
View File

@ -6,17 +6,17 @@
namespace JitX64 {
void JitX64::SHADD8() { CompileInterpretInstruction(); }
void JitX64::SHADD16() { CompileInterpretInstruction(); }
void JitX64::SHASX() { CompileInterpretInstruction(); }
void JitX64::SHSAX() { CompileInterpretInstruction(); }
void JitX64::SHSUB8() { CompileInterpretInstruction(); }
void JitX64::SHSUB16() { CompileInterpretInstruction(); }
void JitX64::UHADD8() { CompileInterpretInstruction(); }
void JitX64::UHADD16() { CompileInterpretInstruction(); }
void JitX64::UHASX() { CompileInterpretInstruction(); }
void JitX64::UHSAX() { CompileInterpretInstruction(); }
void JitX64::UHSUB8() { CompileInterpretInstruction(); }
void JitX64::UHSUB16() { CompileInterpretInstruction(); }
void JitX64::SHADD8(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) { CompileInterpretInstruction(); }
void JitX64::SHADD16(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) { CompileInterpretInstruction(); }
void JitX64::SHASX(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) { CompileInterpretInstruction(); }
void JitX64::SHSAX(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) { CompileInterpretInstruction(); }
void JitX64::SHSUB8(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) { CompileInterpretInstruction(); }
void JitX64::SHSUB16(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) { CompileInterpretInstruction(); }
void JitX64::UHADD8(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) { CompileInterpretInstruction(); }
void JitX64::UHADD16(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) { CompileInterpretInstruction(); }
void JitX64::UHASX(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) { CompileInterpretInstruction(); }
void JitX64::UHSAX(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) { CompileInterpretInstruction(); }
void JitX64::UHSUB8(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) { CompileInterpretInstruction(); }
void JitX64::UHSUB16(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) { CompileInterpretInstruction(); }
}
} // namespace JitX64

26
src/core/arm/jit_x64/instructions/parallel_add_subtract_modulo.cpp
View File

@ -6,17 +6,17 @@
namespace JitX64 {
void JitX64::SADD8() { CompileInterpretInstruction(); }
void JitX64::SADD16() { CompileInterpretInstruction(); }
void JitX64::SASX() { CompileInterpretInstruction(); }
void JitX64::SSAX() { CompileInterpretInstruction(); }
void JitX64::SSUB8() { CompileInterpretInstruction(); }
void JitX64::SSUB16() { CompileInterpretInstruction(); }
void JitX64::UADD8() { CompileInterpretInstruction(); }
void JitX64::UADD16() { CompileInterpretInstruction(); }
void JitX64::UASX() { CompileInterpretInstruction(); }
void JitX64::USAX() { CompileInterpretInstruction(); }
void JitX64::USUB8() { CompileInterpretInstruction(); }
void JitX64::USUB16() { CompileInterpretInstruction(); }
void JitX64::SADD8(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) { CompileInterpretInstruction(); }
void JitX64::SADD16(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) { CompileInterpretInstruction(); }
void JitX64::SASX(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) { CompileInterpretInstruction(); }
void JitX64::SSAX(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) { CompileInterpretInstruction(); }
void JitX64::SSUB8(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) { CompileInterpretInstruction(); }
void JitX64::SSUB16(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) { CompileInterpretInstruction(); }
void JitX64::UADD8(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) { CompileInterpretInstruction(); }
void JitX64::UADD16(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) { CompileInterpretInstruction(); }
void JitX64::UASX(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) { CompileInterpretInstruction(); }
void JitX64::USAX(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) { CompileInterpretInstruction(); }
void JitX64::USUB8(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) { CompileInterpretInstruction(); }
void JitX64::USUB16(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) { CompileInterpretInstruction(); }
}
} // namespace JitX64

27
src/core/arm/jit_x64/instructions/parallel_add_subtract_saturating.cpp
View File

@ -6,18 +6,17 @@
namespace JitX64 {
void JitX64::QADD8() { CompileInterpretInstruction(); }
void JitX64::QADD16() { CompileInterpretInstruction(); }
void JitX64::QASX() { CompileInterpretInstruction(); }
void JitX64::QSAX() { CompileInterpretInstruction(); }
void JitX64::QSUB8() { CompileInterpretInstruction(); }
void JitX64::QSUB16() { CompileInterpretInstruction(); }
void JitX64::UQADD8() { CompileInterpretInstruction(); }
void JitX64::UQADD16() { CompileInterpretInstruction(); }
void JitX64::UQASX() { CompileInterpretInstruction(); }
void JitX64::UQSAX() { CompileInterpretInstruction(); }
void JitX64::UQSUB8() { CompileInterpretInstruction(); }
void JitX64::UQSUB16() { CompileInterpretInstruction(); }
void JitX64::QADD8(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) { CompileInterpretInstruction(); }
void JitX64::QADD16(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) { CompileInterpretInstruction(); }
void JitX64::QASX(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) { CompileInterpretInstruction(); }
void JitX64::QSAX(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) { CompileInterpretInstruction(); }
void JitX64::QSUB8(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) { CompileInterpretInstruction(); }
void JitX64::QSUB16(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) { CompileInterpretInstruction(); }
void JitX64::UQADD8(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) { CompileInterpretInstruction(); }
void JitX64::UQADD16(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) { CompileInterpretInstruction(); }
void JitX64::UQASX(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) { CompileInterpretInstruction(); }
void JitX64::UQSAX(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) { CompileInterpretInstruction(); }
void JitX64::UQSUB8(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) { CompileInterpretInstruction(); }
void JitX64::UQSUB16(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) { CompileInterpretInstruction(); }
}
} // namespace JitX64

10
src/core/arm/jit_x64/instructions/qadd_qsub.cpp
View File

@ -6,9 +6,9 @@
namespace JitX64 {
void JitX64::QADD() { CompileInterpretInstruction(); }
void JitX64::QSUB() { CompileInterpretInstruction(); }
void JitX64::QDADD() { CompileInterpretInstruction(); }
void JitX64::QDSUB() { CompileInterpretInstruction(); }
void JitX64::QADD(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) { CompileInterpretInstruction(); }
void JitX64::QSUB(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) { CompileInterpretInstruction(); }
void JitX64::QDADD(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) { CompileInterpretInstruction(); }
void JitX64::QDSUB(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) { CompileInterpretInstruction(); }
}
} // namespace JitX64

8
src/core/arm/jit_x64/instructions/reversal.cpp
View File

@ -6,8 +6,8 @@
namespace JitX64 {
void JitX64::REV() { CompileInterpretInstruction(); }
void JitX64::REV16() { CompileInterpretInstruction(); }
void JitX64::REVSH() { CompileInterpretInstruction(); }
void JitX64::REV(Cond cond, ArmReg Rd, ArmReg Rm) { CompileInterpretInstruction(); }
void JitX64::REV16(Cond cond, ArmReg Rd, ArmReg Rm) { CompileInterpretInstruction(); }
void JitX64::REVSH(Cond cond, ArmReg Rd, ArmReg Rm) { CompileInterpretInstruction(); }
}
} // namespace JitX64

10
src/core/arm/jit_x64/instructions/saturation.cpp
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@ -6,9 +6,9 @@
namespace JitX64 {
void JitX64::SSAT() { CompileInterpretInstruction(); }
void JitX64::SSAT16() { CompileInterpretInstruction(); }
void JitX64::USAT() { CompileInterpretInstruction(); }
void JitX64::USAT16() { CompileInterpretInstruction(); }
void JitX64::SSAT(Cond cond, ArmImm5 sat_imm, ArmReg Rd, ArmImm5 imm5, bool sh, ArmReg Rn) { CompileInterpretInstruction(); }
void JitX64::SSAT16(Cond cond, ArmImm4 sat_imm, ArmReg Rd, ArmReg Rn) { CompileInterpretInstruction(); }
void JitX64::USAT(Cond cond, ArmImm5 sat_imm, ArmReg Rd, ArmImm5 imm5, bool sh, ArmReg Rn) { CompileInterpretInstruction(); }
void JitX64::USAT16(Cond cond, ArmImm4 sat_imm, ArmReg Rd, ArmReg Rn) { CompileInterpretInstruction(); }
}
} // namespace JitX64

2
src/core/arm/jit_x64/instructions/status_register.cpp
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@ -29,4 +29,4 @@ void JitX64::SETEND(bool E) {
void JitX64::SRS() { CompileInterpretInstruction(); }
}
} // namespace JitX64

2
src/core/arm/jit_x64/instructions/synchronisation.cpp
View File

@ -294,4 +294,4 @@ void JitX64::SWPB(Cond cond, ArmReg Rn_index, ArmReg Rd_index, ArmReg Rm_index)
CompileInterpretInstruction();
}
}
} // namespace JitX64

2
src/core/arm/jit_x64/instructions/thumb.cpp
View File

@ -97,4 +97,4 @@ void JitX64::thumb_BLX_suffix(bool X, ArmImm11 imm11) {
thumb_BLX_suffix_executed = true;
}
}
} // namespace JitX64

6
src/core/arm/jit_x64/instructions/usad.cpp
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@ -6,7 +6,7 @@
namespace JitX64 {
void JitX64::USAD8() { CompileInterpretInstruction(); }
void JitX64::USADA8() { CompileInterpretInstruction(); }
void JitX64::USAD8(Cond cond, ArmReg Rd, ArmReg Rm, ArmReg Rn) { CompileInterpretInstruction(); }
void JitX64::USADA8(Cond cond, ArmReg Rd, ArmReg Ra, ArmReg Rm, ArmReg Rn) { CompileInterpretInstruction(); }
}
} // namespace JitX64

170
src/core/arm/jit_x64/jit_x64.h
View File

@ -226,18 +226,18 @@ private:
void UDF() override;
// Extension functions
void SXTAB() override;
void SXTAB16() override;
void SXTAH() override;
void SXTB() override;
void SXTB16() override;
void SXTH() override;
void UXTAB() override;
void UXTAB16() override;
void UXTAH() override;
void UXTB() override;
void UXTB16() override;
void UXTH() override;
void SXTAB(Cond cond, ArmReg Rn, ArmReg Rd, SignExtendRotation rotate, ArmReg Rm) override;
void SXTAB16(Cond cond, ArmReg Rn, ArmReg Rd, SignExtendRotation rotate, ArmReg Rm) override;
void SXTAH(Cond cond, ArmReg Rn, ArmReg Rd, SignExtendRotation rotate, ArmReg Rm) override;
void SXTB(Cond cond, ArmReg Rd, SignExtendRotation rotate, ArmReg Rm) override;
void SXTB16(Cond cond, ArmReg Rd, SignExtendRotation rotate, ArmReg Rm) override;
void SXTH(Cond cond, ArmReg Rd, SignExtendRotation rotate, ArmReg Rm) override;
void UXTAB(Cond cond, ArmReg Rn, ArmReg Rd, SignExtendRotation rotate, ArmReg Rm) override;
void UXTAB16(Cond cond, ArmReg Rn, ArmReg Rd, SignExtendRotation rotate, ArmReg Rm) override;
void UXTAH(Cond cond, ArmReg Rn, ArmReg Rd, SignExtendRotation rotate, ArmReg Rm) override;
void UXTB(Cond cond, ArmReg Rd, SignExtendRotation rotate, ArmReg Rm) override;
void UXTB16(Cond cond, ArmReg Rd, SignExtendRotation rotate, ArmReg Rm) override;
void UXTH(Cond cond, ArmReg Rd, SignExtendRotation rotate, ArmReg Rm) override;
// Hint instructions
void PLD() override;
@ -293,109 +293,109 @@ private:
void STM_usr() override;
// Miscellaneous instructions
void CLZ() override;
void CLZ(Cond cond, ArmReg Rd, ArmReg Rm) override;
void NOP() override;
void SEL() override;
void SEL(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) override;
// Unsigned sum of absolute difference functions
void USAD8() override;
void USADA8() override;
void USAD8(Cond cond, ArmReg Rd, ArmReg Rm, ArmReg Rn) override;
void USADA8(Cond cond, ArmReg Rd, ArmReg Ra, ArmReg Rm, ArmReg Rn) override;
// Packing instructions
void PKHBT(Cond cond, ArmReg Rn, ArmReg Rd, ArmImm5 imm5, ArmReg Rm) override;
void PKHTB(Cond cond, ArmReg Rn, ArmReg Rd, ArmImm5 imm5, ArmReg Rm) override;
// Reversal instructions
void REV() override;
void REV16() override;
void REVSH() override;
void REV(Cond cond, ArmReg Rd, ArmReg Rm) override;
void REV16(Cond cond, ArmReg Rd, ArmReg Rm) override;
void REVSH(Cond cond, ArmReg Rd, ArmReg Rm) override;
// Saturation instructions
void SSAT() override;
void SSAT16() override;
void USAT() override;
void USAT16() override;
void SSAT(Cond cond, ArmImm5 sat_imm, ArmReg Rd, ArmImm5 imm5, bool sh, ArmReg Rn) override;
void SSAT16(Cond cond, ArmImm4 sat_imm, ArmReg Rd, ArmReg Rn) override;
void USAT(Cond cond, ArmImm5 sat_imm, ArmReg Rd, ArmImm5 imm5, bool sh, ArmReg Rn) override;
void USAT16(Cond cond, ArmImm4 sat_imm, ArmReg Rd, ArmReg Rn) override;
// Multiply (Normal) instructions
void MLA() override;
void MUL() override;
void MLA(Cond cond, bool S, ArmReg Rd, ArmReg Ra, ArmReg Rm, ArmReg Rn) override;
void MUL(Cond cond, bool S, ArmReg Rd, ArmReg Rm, ArmReg Rn) override;
// Multiply (Long) instructions
void SMLAL() override;
void SMULL() override;
void UMAAL() override;
void UMLAL() override;
void UMULL() override;
void SMLAL(Cond cond, bool S, ArmReg RdHi, ArmReg RdLo, ArmReg Rm, ArmReg Rn) override;
void SMULL(Cond cond, bool S, ArmReg RdHi, ArmReg RdLo, ArmReg Rm, ArmReg Rn) override;
void UMAAL(Cond cond, ArmReg RdHi, ArmReg RdLo, ArmReg Rm, ArmReg Rn) override;
void UMLAL(Cond cond, bool S, ArmReg RdHi, ArmReg RdLo, ArmReg Rm, ArmReg Rn) override;
void UMULL(Cond cond, bool S, ArmReg RdHi, ArmReg RdLo, ArmReg Rm, ArmReg Rn) override;
// Multiply (Halfword) instructions
void SMLALxy() override;
void SMLAxy() override;
void SMULxy() override;
void SMLALxy(Cond cond, ArmReg RdHi, ArmReg RdLo, ArmReg Rm, bool M, bool N, ArmReg Rn) override;
void SMLAxy(Cond cond, ArmReg Rd, ArmReg Ra, ArmReg Rm, bool M, bool N, ArmReg Rn) override;
void SMULxy(Cond cond, ArmReg Rd, ArmReg Rm, bool M, bool N, ArmReg Rn) override;
// Multiply (word by halfword) instructions
void SMLAWy() override;
void SMULWy() override;
void SMLAWy(Cond cond, ArmReg Rd, ArmReg Ra, ArmReg Rm, bool M, ArmReg Rn) override;
void SMULWy(Cond cond, ArmReg Rd, ArmReg Rm, bool M, ArmReg Rn) override;
// Multiply (Most significant word) instructions
void SMMLA() override;
void SMMLS() override;
void SMMUL() override;
void SMMLA(Cond cond, ArmReg Rd, ArmReg Ra, ArmReg Rm, bool R, ArmReg Rn) override;
void SMMLS(Cond cond, ArmReg Rd, ArmReg Ra, ArmReg Rm, bool R, ArmReg Rn) override;
void SMMUL(Cond cond, ArmReg Rd, ArmReg Rm, bool R, ArmReg Rn) override;
// Multiply (Dual) instructions
void SMLAD() override;
void SMLALD() override;
void SMLSD() override;
void SMLSLD() override;
void SMUAD() override;
void SMUSD() override;
void SMLAD(Cond cond, ArmReg Rd, ArmReg Ra, ArmReg Rm, bool M, ArmReg Rn) override;
void SMLALD(Cond cond, ArmReg RdHi, ArmReg RdLo, ArmReg Rm, bool M, ArmReg Rn) override;
void SMLSD(Cond cond, ArmReg Rd, ArmReg Ra, ArmReg Rm, bool M, ArmReg Rn) override;
void SMLSLD(Cond cond, ArmReg RdHi, ArmReg RdLo, ArmReg Rm, bool M, ArmReg Rn) override;
void SMUAD(Cond cond, ArmReg Rd, ArmReg Rm, bool M, ArmReg Rn) override;
void SMUSD(Cond cond, ArmReg Rd, ArmReg Rm, bool M, ArmReg Rn) override;
// Parallel Add/Subtract (Modulo arithmetic) instructions
void SADD8() override;
void SADD16() override;
void SASX() override;
void SSAX() override;
void SSUB8() override;
void SSUB16() override;
void UADD8() override;
void UADD16() override;
void UASX() override;
void USAX() override;
void USUB8() override;
void USUB16() override;
void SADD8(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) override;
void SADD16(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) override;
void SASX(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) override;
void SSAX(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) override;
void SSUB8(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) override;
void SSUB16(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) override;
void UADD8(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) override;
void UADD16(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) override;
void UASX(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) override;
void USAX(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) override;
void USUB8(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) override;
void USUB16(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) override;
// Parallel Add/Subtract (Saturating) instructions
void QADD8() override;
void QADD16() override;
void QASX() override;
void QSAX() override;
void QSUB8() override;
void QSUB16() override;
void UQADD8() override;
void UQADD16() override;
void UQASX() override;
void UQSAX() override;
void UQSUB8() override;
void UQSUB16() override;
void QADD8(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) override;
void QADD16(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) override;
void QASX(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) override;
void QSAX(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) override;
void QSUB8(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) override;
void QSUB16(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) override;
void UQADD8(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) override;
void UQADD16(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) override;
void UQASX(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) override;
void UQSAX(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) override;
void UQSUB8(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) override;
void UQSUB16(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) override;
// Parallel Add/Subtract (Halving) instructions
void SHADD8() override;
void SHADD16() override;
void SHASX() override;
void SHSAX() override;
void SHSUB8() override;
void SHSUB16() override;
void UHADD8() override;
void UHADD16() override;
void UHASX() override;
void UHSAX() override;
void UHSUB8() override;
void UHSUB16() override;
void SHADD8(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) override;
void SHADD16(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) override;
void SHASX(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) override;
void SHSAX(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) override;
void SHSUB8(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) override;
void SHSUB16(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) override;
void UHADD8(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) override;
void UHADD16(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) override;
void UHASX(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) override;
void UHSAX(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) override;
void UHSUB8(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) override;
void UHSUB16(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) override;
// Saturated Add/Subtract instructions
void QADD() override;
void QSUB() override;
void QDADD() override;
void QDSUB() override;
void QADD(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) override;
void QSUB(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) override;
void QDADD(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) override;
void QDSUB(Cond cond, ArmReg Rn, ArmReg Rd, ArmReg Rm) override;
// Synchronization Primitive instructions
void CLREX() override;
@ -429,4 +429,4 @@ private:
void thumb_BLX_suffix(bool L, ArmImm11 imm11) override;
};
}
} // namespace JitX64