mirror of
https://github.com/citra-emu/citra.git
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399 lines
29 KiB
C++
399 lines
29 KiB
C++
// Copyright 2016 Citra Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <algorithm>
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#include <cstddef>
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#include <cstring>
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#include <boost/optional.hpp>
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#include "common/assert.h"
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#include "common/common_types.h"
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#include "common/make_unique.h"
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#include "core/arm/decoder/decoder.h"
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namespace ArmDecoder {
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namespace Impl {
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// std::integer_sequence and std::make_integer_sequence are only available in C++14
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/// This type represents a sequence of integers
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template<size_t ...>
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struct integer_sequence {};
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/// This metafunction generates a sequence of integers from 0..N
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template<size_t N, size_t ...seq>
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struct make_integer_sequence : make_integer_sequence<N - 1, N - 1, seq...> {};
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// Internal implementation for make_integer_sequence
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template<size_t ...seq>
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struct make_integer_sequence<0, seq...> {
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typedef integer_sequence<seq...> type;
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};
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/**
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* This function takes a member function of Visitor and calls it with the parameters specified in list.
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* @tparam NumArgs Number of arguments that the member function fn has.
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* @param v The Visitor.
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* @param fn Member function to call on v.
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* @param list List of arguments that will be splatted.
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*/
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template<size_t NumArgs, typename Function, typename Container>
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void call(Visitor* v, Function fn, const Container& list) {
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call_impl(typename make_integer_sequence<NumArgs>::type(), v, fn, list);
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}
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// Internal implementation for call
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template<size_t ...seq, typename Function, typename Container>
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void call_impl(integer_sequence<seq...>, Visitor* v, Function fn, const Container& list) {
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(v->*fn)(std::get<seq>(list)...);
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}
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/// Function has NumArgs arguments
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template<size_t NumArgs, typename Function>
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struct MatcherImpl : Matcher {
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std::array<u32, NumArgs> masks = {};
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std::array<size_t, NumArgs> shifts = {};
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Function fn = nullptr;
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virtual void visit(Visitor *v, u32 inst) override {
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std::array<u32, NumArgs> values;
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for (size_t i = 0; i < NumArgs; i++) {
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values[i] = (inst & masks[i]) >> shifts[i];
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}
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call<NumArgs>(v, fn, values);
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}
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};
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}
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template<size_t NumArgs, typename Function>
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static std::unique_ptr<Matcher> MakeMatcher(const char format[32], Function fn) {
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auto ret = Common::make_unique<Impl::MatcherImpl<NumArgs, Function>>();
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ret->fn = fn;
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ret->masks.fill(0);
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ret->shifts.fill(0);
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char ch = 0;
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int arg = -1;
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for (int i = 0; i < 32; i++) {
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const u32 bit = 1 << (31 - i);
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if (format[i] == '0') {
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ret->bit_mask |= bit;
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ch = 0;
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continue;
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} else if (format[i] == '1') {
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ret->bit_mask |= bit;
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ret->expected |= bit;
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ch = 0;
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continue;
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} else if (format[i] == '-') {
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ch = 0;
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continue;
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}
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// Ban some characters
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ASSERT(format[i] != 'I');
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ASSERT(format[i] != 'l');
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ASSERT(format[i] != 'O');
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if (format[i] != ch){
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arg++;
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ASSERT(arg < NumArgs);
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ch = format[i];
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}
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ret->masks[arg] |= bit;
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ret->shifts[arg] = 31 - i;
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}
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ASSERT(arg == NumArgs - 1);
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return std::unique_ptr<Matcher>(std::move(ret));
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}
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static const std::array<Instruction, 221> arm_instruction_table = {{
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// Branch instructions
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{ "BLX (immediate)", MakeMatcher<2>("1111101hvvvvvvvvvvvvvvvvvvvvvvvv", &Visitor::BLX_imm) }, // ARMv5
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{ "BLX (register)", MakeMatcher<2>("cccc000100101111111111110011mmmm", &Visitor::BLX_reg) }, // ARMv5
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{ "B", MakeMatcher<2>("cccc1010vvvvvvvvvvvvvvvvvvvvvvvv", &Visitor::B) }, // all
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{ "BL", MakeMatcher<2>("cccc1011vvvvvvvvvvvvvvvvvvvvvvvv", &Visitor::BL) }, // all
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{ "BX", MakeMatcher<2>("cccc000100101111111111110001mmmm", &Visitor::BX) }, // ARMv4T
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{ "BXJ", MakeMatcher<2>("cccc000100101111111111110010mmmm", &Visitor::BXJ) }, // ARMv5J
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// Coprocessor instructions
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{ "CDP2", MakeMatcher<0>("11111110-------------------1----", &Visitor::CDP) }, // ARMv5 (Generic Coprocessor)
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{ "CDP", MakeMatcher<0>("----1110-------------------0----", &Visitor::CDP) }, // ARMv2 (Generic Coprocessor)
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{ "LDC2", MakeMatcher<0>("1111110----1--------------------", &Visitor::LDC) }, // ARMv5 (Generic Coprocessor)
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{ "LDC", MakeMatcher<0>("----110----1--------------------", &Visitor::LDC) }, // ARMv2 (Generic Coprocessor)
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{ "MCR2", MakeMatcher<0>("----1110---0---------------1----", &Visitor::MCR) }, // ARMv5 (Generic Coprocessor)
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{ "MCR", MakeMatcher<0>("----1110---0---------------1----", &Visitor::MCR) }, // ARMv2 (Generic Coprocessor)
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{ "MCRR2", MakeMatcher<0>("111111000100--------------------", &Visitor::MCRR) }, // ARMv6 (Generic Coprocessor)
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{ "MCRR", MakeMatcher<0>("----11000100--------------------", &Visitor::MCRR) }, // ARMv5E (Generic Coprocessor)
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{ "MRC2", MakeMatcher<0>("11111110---1---------------1----", &Visitor::MRC) }, // ARMv5 (Generic Coprocessor)
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{ "MRC", MakeMatcher<0>("----1110---1---------------1----", &Visitor::MRC) }, // ARMv2 (Generic Coprocessor)
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{ "MRRC2", MakeMatcher<0>("111111000101--------------------", &Visitor::MRRC) }, // ARMv6 (Generic Coprocessor)
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{ "MRRC", MakeMatcher<0>("----11000101--------------------", &Visitor::MRRC) }, // ARMv5E (Generic Coprocessor)
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{ "STC2", MakeMatcher<0>("1111110----0--------------------", &Visitor::STC) }, // ARMv5 (Generic Coprocessor)
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{ "STC", MakeMatcher<0>("----110----0--------------------", &Visitor::STC) }, // ARMv2 (Generic Coprocessor)
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// Data Processing instructions
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{ "ADC (imm)", MakeMatcher<6>("cccc0010101Snnnnddddrrrrvvvvvvvv", &Visitor::ADC_imm) }, // all
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{ "ADC (reg)", MakeMatcher<7>("cccc0000101Snnnnddddvvvvvrr0mmmm", &Visitor::ADC_reg) }, // all
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{ "ADC (rsr)", MakeMatcher<7>("cccc0000101Snnnnddddssss0rr1mmmm", &Visitor::ADC_rsr) }, // all
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{ "ADD (imm)", MakeMatcher<6>("cccc0010100Snnnnddddrrrrvvvvvvvv", &Visitor::ADD_imm) }, // all
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{ "ADD (reg)", MakeMatcher<7>("cccc0000100Snnnnddddvvvvvrr0mmmm", &Visitor::ADD_reg) }, // all
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{ "ADD (rsr)", MakeMatcher<7>("cccc0000100Snnnnddddssss0rr1mmmm", &Visitor::ADD_rsr) }, // all
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{ "AND (imm)", MakeMatcher<6>("cccc0010000Snnnnddddrrrrvvvvvvvv", &Visitor::AND_imm) }, // all
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{ "AND (reg)", MakeMatcher<7>("cccc0000000Snnnnddddvvvvvrr0mmmm", &Visitor::AND_reg) }, // all
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{ "AND (rsr)", MakeMatcher<7>("cccc0000000Snnnnddddssss0rr1mmmm", &Visitor::AND_rsr) }, // all
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{ "BIC (imm)", MakeMatcher<6>("cccc0011110Snnnnddddrrrrvvvvvvvv", &Visitor::BIC_imm) }, // all
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{ "BIC (reg)", MakeMatcher<7>("cccc0001110Snnnnddddvvvvvrr0mmmm", &Visitor::BIC_reg) }, // all
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{ "BIC (rsr)", MakeMatcher<7>("cccc0001110Snnnnddddssss0rr1mmmm", &Visitor::BIC_rsr) }, // all
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{ "CMN (imm)", MakeMatcher<4>("cccc00110111nnnn0000rrrrvvvvvvvv", &Visitor::CMN_imm) }, // all
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{ "CMN (reg)", MakeMatcher<5>("cccc00010111nnnn0000vvvvvrr0mmmm", &Visitor::CMN_reg) }, // all
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{ "CMN (rsr)", MakeMatcher<5>("cccc00010111nnnn0000ssss0rr1mmmm", &Visitor::CMN_rsr) }, // all
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{ "CMP (imm)", MakeMatcher<4>("cccc00110101nnnn0000rrrrvvvvvvvv", &Visitor::CMP_imm) }, // all
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{ "CMP (reg)", MakeMatcher<5>("cccc00010101nnnn0000vvvvvrr0mmmm", &Visitor::CMP_reg) }, // all
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{ "CMP (rsr)", MakeMatcher<5>("cccc00010101nnnn0000ssss0rr1mmmm", &Visitor::CMP_rsr) }, // all
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{ "EOR (imm)", MakeMatcher<6>("cccc0010001Snnnnddddrrrrvvvvvvvv", &Visitor::EOR_imm) }, // all
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{ "EOR (reg)", MakeMatcher<7>("cccc0000001Snnnnddddvvvvvrr0mmmm", &Visitor::EOR_reg) }, // all
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{ "EOR (rsr)", MakeMatcher<7>("cccc0000001Snnnnddddssss0rr1mmmm", &Visitor::EOR_rsr) }, // all
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{ "MOV (imm)", MakeMatcher<5>("cccc0011101S0000ddddrrrrvvvvvvvv", &Visitor::MOV_imm) }, // all
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{ "MOV (reg)", MakeMatcher<6>("cccc0001101S0000ddddvvvvvrr0mmmm", &Visitor::MOV_reg) }, // all
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{ "MOV (rsr)", MakeMatcher<6>("cccc0001101S0000ddddssss0rr1mmmm", &Visitor::MOV_rsr) }, // all
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{ "MVN (imm)", MakeMatcher<5>("cccc0011111S0000ddddrrrrvvvvvvvv", &Visitor::MVN_imm) }, // all
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{ "MVN (reg)", MakeMatcher<6>("cccc0001111S0000ddddvvvvvrr0mmmm", &Visitor::MVN_reg) }, // all
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{ "MVN (rsr)", MakeMatcher<6>("cccc0001111S0000ddddssss0rr1mmmm", &Visitor::MVN_rsr) }, // all
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{ "ORR (imm)", MakeMatcher<6>("cccc0011100Snnnnddddrrrrvvvvvvvv", &Visitor::ORR_imm) }, // all
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{ "ORR (reg)", MakeMatcher<7>("cccc0001100Snnnnddddvvvvvrr0mmmm", &Visitor::ORR_reg) }, // all
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{ "ORR (rsr)", MakeMatcher<7>("cccc0001100Snnnnddddssss0rr1mmmm", &Visitor::ORR_rsr) }, // all
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{ "RSB (imm)", MakeMatcher<6>("cccc0010011Snnnnddddrrrrvvvvvvvv", &Visitor::RSB_imm) }, // all
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{ "RSB (reg)", MakeMatcher<7>("cccc0000011Snnnnddddvvvvvrr0mmmm", &Visitor::RSB_reg) }, // all
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{ "RSB (rsr)", MakeMatcher<7>("cccc0000011Snnnnddddssss0rr1mmmm", &Visitor::RSB_rsr) }, // all
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{ "RSC (imm)", MakeMatcher<6>("cccc0010111Snnnnddddrrrrvvvvvvvv", &Visitor::RSC_imm) }, // all
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{ "RSC (reg)", MakeMatcher<7>("cccc0000111Snnnnddddvvvvvrr0mmmm", &Visitor::RSC_reg) }, // all
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{ "RSC (rsr)", MakeMatcher<7>("cccc0000111Snnnnddddssss0rr1mmmm", &Visitor::RSC_rsr) }, // all
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{ "SBC (imm)", MakeMatcher<6>("cccc0010110Snnnnddddrrrrvvvvvvvv", &Visitor::SBC_imm) }, // all
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{ "SBC (reg)", MakeMatcher<7>("cccc0000110Snnnnddddvvvvvrr0mmmm", &Visitor::SBC_reg) }, // all
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{ "SBC (rsr)", MakeMatcher<7>("cccc0000110Snnnnddddssss0rr1mmmm", &Visitor::SBC_rsr) }, // all
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{ "SUB (imm)", MakeMatcher<6>("cccc0010010Snnnnddddrrrrvvvvvvvv", &Visitor::SUB_imm) }, // all
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{ "SUB (reg)", MakeMatcher<7>("cccc0000010Snnnnddddvvvvvrr0mmmm", &Visitor::SUB_reg) }, // all
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{ "SUB (rsr)", MakeMatcher<7>("cccc0000010Snnnnddddssss0rr1mmmm", &Visitor::SUB_rsr) }, // all
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{ "TEQ (imm)", MakeMatcher<4>("cccc00110011nnnn0000rrrrvvvvvvvv", &Visitor::TEQ_imm) }, // all
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{ "TEQ (reg)", MakeMatcher<5>("cccc00010011nnnn0000vvvvvrr0mmmm", &Visitor::TEQ_reg) }, // all
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{ "TEQ (rsr)", MakeMatcher<5>("cccc00010011nnnn0000ssss0rr1mmmm", &Visitor::TEQ_rsr) }, // all
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{ "TST (imm)", MakeMatcher<4>("cccc00110001nnnn0000rrrrvvvvvvvv", &Visitor::TST_imm) }, // all
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{ "TST (reg)", MakeMatcher<5>("cccc00010001nnnn0000vvvvvrr0mmmm", &Visitor::TST_reg) }, // all
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{ "TST (rsr)", MakeMatcher<5>("cccc00010001nnnn0000ssss0rr1mmmm", &Visitor::TST_rsr) }, // all
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// Exception Generating instructions
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{ "BKPT", MakeMatcher<3>("cccc00010010vvvvvvvvvvvv0111vvvv", &Visitor::BKPT) }, // ARMv5
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{ "SVC", MakeMatcher<2>("cccc1111vvvvvvvvvvvvvvvvvvvvvvvv", &Visitor::SVC) }, // all
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{ "UDF", MakeMatcher<0>("111001111111------------1111----", &Visitor::UDF) }, // all
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// Extension instructions
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{ "SXTB", MakeMatcher<4>("cccc011010101111ddddrr000111mmmm", &Visitor::SXTB) }, // ARMv6
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{ "SXTB16", MakeMatcher<4>("cccc011010001111ddddrr000111mmmm", &Visitor::SXTB16) }, // ARMv6
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{ "SXTH", MakeMatcher<4>("cccc011010111111ddddrr000111mmmm", &Visitor::SXTH) }, // ARMv6
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{ "SXTAB", MakeMatcher<5>("cccc01101010nnnnddddrr000111mmmm", &Visitor::SXTAB) }, // ARMv6
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{ "SXTAB16", MakeMatcher<5>("cccc01101000nnnnddddrr000111mmmm", &Visitor::SXTAB16) }, // ARMv6
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{ "SXTAH", MakeMatcher<5>("cccc01101011nnnnddddrr000111mmmm", &Visitor::SXTAH) }, // ARMv6
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{ "UXTB", MakeMatcher<4>("cccc011011101111ddddrr000111mmmm", &Visitor::UXTB) }, // ARMv6
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{ "UXTB16", MakeMatcher<4>("cccc011011001111ddddrr000111mmmm", &Visitor::UXTB16) }, // ARMv6
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{ "UXTH", MakeMatcher<4>("cccc011011111111ddddrr000111mmmm", &Visitor::UXTH) }, // ARMv6
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{ "UXTAB", MakeMatcher<5>("cccc01101110nnnnddddrr000111mmmm", &Visitor::UXTAB) }, // ARMv6
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{ "UXTAB16", MakeMatcher<5>("cccc01101100nnnnddddrr000111mmmm", &Visitor::UXTAB16) }, // ARMv6
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{ "UXTAH", MakeMatcher<5>("cccc01101111nnnnddddrr000111mmmm", &Visitor::UXTAH) }, // ARMv6
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// Hint instructions
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{ "PLD", MakeMatcher<0>("111101---101----1111------------", &Visitor::PLD) }, // ARMv5E
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{ "SEV", MakeMatcher<0>("----0011001000001111000000000100", &Visitor::SEV) }, // ARMv6K
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{ "WFE", MakeMatcher<0>("----0011001000001111000000000010", &Visitor::WFE) }, // ARMv6K
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{ "WFI", MakeMatcher<0>("----0011001000001111000000000011", &Visitor::WFI) }, // ARMv6K
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{ "YIELD", MakeMatcher<0>("----0011001000001111000000000001", &Visitor::YIELD) }, // ARMv6K
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// Synchronization Primitive instructions
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{ "CLREX", MakeMatcher<0>("11110101011111111111000000011111", &Visitor::CLREX) }, // ARMv6K
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{ "LDREX", MakeMatcher<3>("cccc00011001nnnndddd111110011111", &Visitor::LDREX) }, // ARMv6
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{ "LDREXB", MakeMatcher<3>("cccc00011101nnnndddd111110011111", &Visitor::LDREXB) }, // ARMv6K
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{ "LDREXD", MakeMatcher<3>("cccc00011011nnnndddd111110011111", &Visitor::LDREXD) }, // ARMv6K
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{ "LDREXH", MakeMatcher<3>("cccc00011111nnnndddd111110011111", &Visitor::LDREXH) }, // ARMv6K
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{ "STREX", MakeMatcher<4>("cccc00011000nnnndddd11111001mmmm", &Visitor::STREX) }, // ARMv6
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{ "STREXB", MakeMatcher<4>("cccc00011100nnnndddd11111001mmmm", &Visitor::STREXB) }, // ARMv6K
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{ "STREXD", MakeMatcher<4>("cccc00011010nnnndddd11111001mmmm", &Visitor::STREXD) }, // ARMv6K
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{ "STREXH", MakeMatcher<4>("cccc00011110nnnndddd11111001mmmm", &Visitor::STREXH) }, // ARMv6K
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{ "SWP", MakeMatcher<4>("cccc00010000nnnndddd00001001mmmm", &Visitor::SWP) }, // ARMv2S (Deprecated in ARMv6)
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{ "SWPB", MakeMatcher<4>("cccc00010100nnnndddd00001001mmmm", &Visitor::SWPB) }, // ARMv2S (Deprecated in ARMv6)
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// Load/Store instructions
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{ "LDR (imm)", MakeMatcher<7>("cccc010pu0w1nnnnddddvvvvvvvvvvvv", &Visitor::LDR_imm) },
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{ "LDR (reg)", MakeMatcher<9>("cccc011pu0w1nnnnddddvvvvvrr0mmmm", &Visitor::LDR_reg) },
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{ "LDRB (imm)", MakeMatcher<7>("cccc010pu1w1nnnnddddvvvvvvvvvvvv", &Visitor::LDRB_imm) },
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{ "LDRB (reg)", MakeMatcher<9>("cccc011pu1w1nnnnddddvvvvvrr0mmmm", &Visitor::LDRB_reg) },
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{ "LDRBT (A1)", MakeMatcher<0>("----0100-111--------------------", &Visitor::LDRBT) },
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{ "LDRBT (A2)", MakeMatcher<0>("----0110-111---------------0----", &Visitor::LDRBT) },
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{ "LDRD (imm)", MakeMatcher<8>("cccc000pu1w0nnnnddddvvvv1101vvvv", &Visitor::LDRD_imm) }, // ARMv5E
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{ "LDRD (reg)", MakeMatcher<7>("cccc000pu0w0nnnndddd00001101mmmm", &Visitor::LDRD_reg) }, // ARMv5E
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{ "LDRH (imm)", MakeMatcher<8>("cccc000pu1w1nnnnddddvvvv1011vvvv", &Visitor::LDRH_imm) },
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{ "LDRH (reg)", MakeMatcher<7>("cccc000pu0w1nnnndddd00001011mmmm", &Visitor::LDRH_reg) },
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{ "LDRHT (A1)", MakeMatcher<0>("----0000-111------------1011----", &Visitor::LDRHT) },
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{ "LDRHT (A2)", MakeMatcher<0>("----0000-011--------00001011----", &Visitor::LDRHT) },
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{ "LDRSB (imm)", MakeMatcher<8>("cccc000pu1w1nnnnddddvvvv1101vvvv", &Visitor::LDRSB_imm) },
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{ "LDRSB (reg)", MakeMatcher<7>("cccc000pu0w1nnnndddd00001101mmmm", &Visitor::LDRSB_reg) },
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{ "LDRSBT (A1)", MakeMatcher<0>("----0000-111------------1101----", &Visitor::LDRSBT) },
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{ "LDRSBT (A2)", MakeMatcher<0>("----0000-011--------00001101----", &Visitor::LDRSBT) },
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{ "LDRSH (imm)", MakeMatcher<8>("cccc000pu1w1nnnnddddvvvv1111vvvv", &Visitor::LDRSH_imm) },
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{ "LDRSH (reg)", MakeMatcher<7>("cccc000pu0w1nnnndddd00001111mmmm", &Visitor::LDRSH_reg) },
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{ "LDRSHT (A1)", MakeMatcher<0>("----0000-111------------1111----", &Visitor::LDRSHT) },
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{ "LDRSHT (A2)", MakeMatcher<0>("----0000-011--------00001111----", &Visitor::LDRSHT) },
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{ "LDRT (A1)", MakeMatcher<0>("----0100-011--------------------", &Visitor::LDRT) },
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{ "LDRT (A2)", MakeMatcher<0>("----0110-011---------------0----", &Visitor::LDRT) },
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{ "STR (imm)", MakeMatcher<7>("cccc010pu0w0nnnnddddvvvvvvvvvvvv", &Visitor::STR_imm) },
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{ "STR (reg)", MakeMatcher<9>("cccc011pu0w0nnnnddddvvvvvrr0mmmm", &Visitor::STR_reg) },
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{ "STRB (imm)", MakeMatcher<7>("cccc010pu1w0nnnnddddvvvvvvvvvvvv", &Visitor::STRB_imm) },
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{ "STRB (reg)", MakeMatcher<9>("cccc011pu1w0nnnnddddvvvvvrr0mmmm", &Visitor::STRB_reg) },
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{ "STRBT (A1)", MakeMatcher<0>("----0100-110--------------------", &Visitor::STRBT) },
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{ "STRBT (A2)", MakeMatcher<0>("----0110-110---------------0----", &Visitor::STRBT) },
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{ "STRD (imm)", MakeMatcher<8>("cccc000pu1w0nnnnddddvvvv1111vvvv", &Visitor::STRD_imm) }, // ARMv5E
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{ "STRD (reg)", MakeMatcher<7>("cccc000pu0w0nnnndddd00001111mmmm", &Visitor::STRD_reg) }, // ARMv5E
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{ "STRH (imm)", MakeMatcher<8>("cccc000pu1w0nnnnddddvvvv1011vvvv", &Visitor::STRH_imm) },
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{ "STRH (reg)", MakeMatcher<7>("cccc000pu0w0nnnndddd00001011mmmm", &Visitor::STRH_reg) },
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{ "STRHT (A1)", MakeMatcher<0>("----0000-110------------1011----", &Visitor::STRHT) },
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{ "STRHT (A2)", MakeMatcher<0>("----0000-010--------00001011----", &Visitor::STRHT) },
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{ "STRT (A1)", MakeMatcher<0>("----0100-010--------------------", &Visitor::STRT) },
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{ "STRT (A2)", MakeMatcher<0>("----0110-010---------------0----", &Visitor::STRT) },
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// Load/Store Multiple instructions
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{ "LDM", MakeMatcher<6>("cccc100pu0w1nnnnxxxxxxxxxxxxxxxx", &Visitor::LDM) }, // all
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{ "LDM (usr reg)", MakeMatcher<0>("----100--101--------------------", &Visitor::LDM_usr) }, // all
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{ "LDM (exce ret)", MakeMatcher<0>("----100--1-1----1---------------", &Visitor::LDM_eret) }, // all
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{ "STM", MakeMatcher<6>("cccc100pu0w0nnnnxxxxxxxxxxxxxxxx", &Visitor::STM) }, // all
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{ "STM (usr reg)", MakeMatcher<0>("----100--100--------------------", &Visitor::STM_usr) }, // all
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// Miscellaneous instructions
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{ "CLZ", MakeMatcher<3>("cccc000101101111dddd11110001mmmm", &Visitor::CLZ) }, // ARMv5
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{ "NOP", MakeMatcher<0>("----001100100000111100000000----", &Visitor::NOP) }, // ARMv6K
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{ "SEL", MakeMatcher<4>("cccc01101000nnnndddd11111011mmmm", &Visitor::SEL) }, // ARMv6
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// Unsigned Sum of Absolute Differences instructions
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{ "USAD8", MakeMatcher<4>("cccc01111000dddd1111mmmm0001nnnn", &Visitor::USAD8) }, // ARMv6
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{ "USADA8", MakeMatcher<5>("cccc01111000ddddaaaammmm0001nnnn", &Visitor::USADA8) }, // ARMv6
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// Packing instructions
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{ "PKHBT", MakeMatcher<5>("cccc01101000nnnnddddvvvvv001mmmm", &Visitor::PKHBT) }, // ARMv6K
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{ "PKHTB", MakeMatcher<5>("cccc01101000nnnnddddvvvvv101mmmm", &Visitor::PKHTB) }, // ARMv6K
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// Reversal instructions
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{ "REV", MakeMatcher<3>("cccc011010111111dddd11110011mmmm", &Visitor::REV) }, // ARMv6
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{ "REV16", MakeMatcher<3>("cccc011010111111dddd11111011mmmm", &Visitor::REV16) }, // ARMv6
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{ "REVSH", MakeMatcher<3>("cccc011011111111dddd11111011mmmm", &Visitor::REVSH) }, // ARMv6
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|
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// Saturation instructions
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{ "SSAT", MakeMatcher<6>("cccc0110101vvvvvddddvvvvvr01nnnn", &Visitor::SSAT) }, // ARMv6
|
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{ "SSAT16", MakeMatcher<4>("cccc01101010vvvvdddd11110011nnnn", &Visitor::SSAT16) }, // ARMv6
|
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{ "USAT", MakeMatcher<6>("cccc0110111vvvvvddddvvvvvr01nnnn", &Visitor::USAT) }, // ARMv6
|
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{ "USAT16", MakeMatcher<4>("cccc01101110vvvvdddd11110011nnnn", &Visitor::USAT16) }, // ARMv6
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|
|
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// Multiply (Normal) instructions
|
|
{ "MLA", MakeMatcher<6>("cccc0000001Sddddaaaammmm1001nnnn", &Visitor::MLA) }, // ARMv2
|
|
{ "MUL", MakeMatcher<5>("cccc0000000Sdddd0000mmmm1001nnnn", &Visitor::MUL) }, // ARMv2
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|
|
// Multiply (Long) instructions
|
|
{ "SMLAL", MakeMatcher<6>("cccc0000111Sddddaaaammmm1001nnnn", &Visitor::SMLAL) }, // ARMv3M
|
|
{ "SMULL", MakeMatcher<6>("cccc0000110Sddddaaaammmm1001nnnn", &Visitor::SMULL) }, // ARMv3M
|
|
{ "UMAAL", MakeMatcher<5>("cccc00000100ddddaaaammmm1001nnnn", &Visitor::UMAAL) }, // ARMv6
|
|
{ "UMLAL", MakeMatcher<6>("cccc0000101Sddddaaaammmm1001nnnn", &Visitor::UMLAL) }, // ARMv3M
|
|
{ "UMULL", MakeMatcher<6>("cccc0000100Sddddaaaammmm1001nnnn", &Visitor::UMULL) }, // ARMv3M
|
|
|
|
// Multiply (Halfword) instructions
|
|
{ "SMLALXY", MakeMatcher<7>("cccc00010100ddddaaaammmm1xy0nnnn", &Visitor::SMLALxy) }, // ARMv5xP
|
|
{ "SMLAXY", MakeMatcher<7>("cccc00010000ddddaaaammmm1xy0nnnn", &Visitor::SMLAxy) }, // ARMv5xP
|
|
{ "SMULXY", MakeMatcher<6>("cccc00010110dddd0000mmmm1xy0nnnn", &Visitor::SMULxy) }, // ARMv5xP
|
|
|
|
// Multiply (Word by Halfword) instructions
|
|
{ "SMLAWY", MakeMatcher<6>("cccc00010010ddddaaaammmm1y00nnnn", &Visitor::SMLAWy) }, // ARMv5xP
|
|
{ "SMULWY", MakeMatcher<5>("cccc00010010dddd0000mmmm1y10nnnn", &Visitor::SMULWy) }, // ARMv5xP
|
|
|
|
// Multiply (Most Significant Word) instructions
|
|
{ "SMMUL", MakeMatcher<5>("cccc01110101dddd1111mmmm00R1nnnn", &Visitor::SMMUL) }, // ARMv6
|
|
{ "SMMLA", MakeMatcher<6>("cccc01110101ddddaaaammmm00R1nnnn", &Visitor::SMMLA) }, // ARMv6
|
|
{ "SMMLS", MakeMatcher<6>("cccc01110101ddddaaaammmm11R1nnnn", &Visitor::SMMLS) }, // ARMv6
|
|
|
|
// Multiply (Dual) instructions
|
|
{ "SMLAD", MakeMatcher<6>("cccc01110000ddddaaaammmm00M1nnnn", &Visitor::SMLAD) }, // ARMv6
|
|
{ "SMLALD", MakeMatcher<6>("cccc01110100ddddaaaammmm00M1nnnn", &Visitor::SMLALD) }, // ARMv6
|
|
{ "SMLSD", MakeMatcher<6>("cccc01110000ddddaaaammmm01M1nnnn", &Visitor::SMLSD) }, // ARMv6
|
|
{ "SMLSLD", MakeMatcher<6>("cccc01110100ddddaaaammmm01M1nnnn", &Visitor::SMLSLD) }, // ARMv6
|
|
{ "SMUAD", MakeMatcher<5>("cccc01110000dddd1111mmmm00M1nnnn", &Visitor::SMUAD) }, // ARMv6
|
|
{ "SMUSD", MakeMatcher<5>("cccc01110000dddd1111mmmm01M1nnnn", &Visitor::SMUSD) }, // ARMv6
|
|
|
|
// Parallel Add/Subtract (Modulo) instructions
|
|
{ "SADD8", MakeMatcher<4>("cccc01100001nnnndddd11111001mmmm", &Visitor::SADD8) }, // ARMv6
|
|
{ "SADD16", MakeMatcher<4>("cccc01100001nnnndddd11110001mmmm", &Visitor::SADD16) }, // ARMv6
|
|
{ "SASX", MakeMatcher<4>("cccc01100001nnnndddd11110011mmmm", &Visitor::SASX) }, // ARMv6
|
|
{ "SSAX", MakeMatcher<4>("cccc01100001nnnndddd11110101mmmm", &Visitor::SSAX) }, // ARMv6
|
|
{ "SSUB8", MakeMatcher<4>("cccc01100001nnnndddd11111111mmmm", &Visitor::SSUB8) }, // ARMv6
|
|
{ "SSUB16", MakeMatcher<4>("cccc01100001nnnndddd11110111mmmm", &Visitor::SSUB16) }, // ARMv6
|
|
{ "UADD8", MakeMatcher<4>("cccc01100101nnnndddd11111001mmmm", &Visitor::UADD8) }, // ARMv6
|
|
{ "UADD16", MakeMatcher<4>("cccc01100101nnnndddd11110001mmmm", &Visitor::UADD16) }, // ARMv6
|
|
{ "UASX", MakeMatcher<4>("cccc01100101nnnndddd11110011mmmm", &Visitor::UASX) }, // ARMv6
|
|
{ "USAX", MakeMatcher<4>("cccc01100101nnnndddd11110101mmmm", &Visitor::USAX) }, // ARMv6
|
|
{ "USUB8", MakeMatcher<4>("cccc01100101nnnndddd11111111mmmm", &Visitor::USUB8) }, // ARMv6
|
|
{ "USUB16", MakeMatcher<4>("cccc01100101nnnndddd11110111mmmm", &Visitor::USUB16) }, // ARMv6
|
|
|
|
// Parallel Add/Subtract (Saturating) instructions
|
|
{ "QADD8", MakeMatcher<4>("cccc01100010nnnndddd11111001mmmm", &Visitor::QADD8) }, // ARMv6
|
|
{ "QADD16", MakeMatcher<4>("cccc01100010nnnndddd11110001mmmm", &Visitor::QADD16) }, // ARMv6
|
|
{ "QASX", MakeMatcher<4>("cccc01100010nnnndddd11110011mmmm", &Visitor::QASX) }, // ARMv6
|
|
{ "QSAX", MakeMatcher<4>("cccc01100010nnnndddd11110101mmmm", &Visitor::QSAX) }, // ARMv6
|
|
{ "QSUB8", MakeMatcher<4>("cccc01100010nnnndddd11111111mmmm", &Visitor::QSUB8) }, // ARMv6
|
|
{ "QSUB16", MakeMatcher<4>("cccc01100010nnnndddd11110111mmmm", &Visitor::QSUB16) }, // ARMv6
|
|
{ "UQADD8", MakeMatcher<4>("cccc01100110nnnndddd11111001mmmm", &Visitor::UQADD8) }, // ARMv6
|
|
{ "UQADD16", MakeMatcher<4>("cccc01100110nnnndddd11110001mmmm", &Visitor::UQADD16) }, // ARMv6
|
|
{ "UQASX", MakeMatcher<4>("cccc01100110nnnndddd11110011mmmm", &Visitor::UQASX) }, // ARMv6
|
|
{ "UQSAX", MakeMatcher<4>("cccc01100110nnnndddd11110101mmmm", &Visitor::UQSAX) }, // ARMv6
|
|
{ "UQSUB8", MakeMatcher<4>("cccc01100110nnnndddd11111111mmmm", &Visitor::UQSUB8) }, // ARMv6
|
|
{ "UQSUB16", MakeMatcher<4>("cccc01100110nnnndddd11110111mmmm", &Visitor::UQSUB16) }, // ARMv6
|
|
|
|
// Parallel Add/Subtract (Halving) instructions
|
|
{ "SHADD8", MakeMatcher<4>("cccc01100011nnnndddd11111001mmmm", &Visitor::SHADD8) }, // ARMv6
|
|
{ "SHADD16", MakeMatcher<4>("cccc01100011nnnndddd11110001mmmm", &Visitor::SHADD16) }, // ARMv6
|
|
{ "SHASX", MakeMatcher<4>("cccc01100011nnnndddd11110011mmmm", &Visitor::SHASX) }, // ARMv6
|
|
{ "SHSAX", MakeMatcher<4>("cccc01100011nnnndddd11110101mmmm", &Visitor::SHSAX) }, // ARMv6
|
|
{ "SHSUB8", MakeMatcher<4>("cccc01100011nnnndddd11111111mmmm", &Visitor::SHSUB8) }, // ARMv6
|
|
{ "SHSUB16", MakeMatcher<4>("cccc01100011nnnndddd11110111mmmm", &Visitor::SHSUB16) }, // ARMv6
|
|
{ "UHADD8", MakeMatcher<4>("cccc01100111nnnndddd11111001mmmm", &Visitor::UHADD8) }, // ARMv6
|
|
{ "UHADD16", MakeMatcher<4>("cccc01100111nnnndddd11110001mmmm", &Visitor::UHADD16) }, // ARMv6
|
|
{ "UHASX", MakeMatcher<4>("cccc01100111nnnndddd11110011mmmm", &Visitor::UHASX) }, // ARMv6
|
|
{ "UHSAX", MakeMatcher<4>("cccc01100111nnnndddd11110101mmmm", &Visitor::UHSAX) }, // ARMv6
|
|
{ "UHSUB8", MakeMatcher<4>("cccc01100111nnnndddd11111111mmmm", &Visitor::UHSUB8) }, // ARMv6
|
|
{ "UHSUB16", MakeMatcher<4>("cccc01100111nnnndddd11110111mmmm", &Visitor::UHSUB16) }, // ARMv6
|
|
|
|
// Saturated Add/Subtract instructions
|
|
{ "QADD", MakeMatcher<4>("cccc00010000nnnndddd00000101mmmm", &Visitor::QADD) }, // ARMv5xP
|
|
{ "QSUB", MakeMatcher<4>("cccc00010010nnnndddd00000101mmmm", &Visitor::QSUB) }, // ARMv5xP
|
|
{ "QDADD", MakeMatcher<4>("cccc00010100nnnndddd00000101mmmm", &Visitor::QDADD) }, // ARMv5xP
|
|
{ "QDSUB", MakeMatcher<4>("cccc00010110nnnndddd00000101mmmm", &Visitor::QDSUB) }, // ARMv5xP
|
|
|
|
// Status Register Access instructions
|
|
{ "CPS", MakeMatcher<0>("111100010000---00000000---0-----", &Visitor::CPS) }, // ARMv6
|
|
{ "SETEND", MakeMatcher<1>("1111000100000001000000e000000000", &Visitor::SETEND) }, // ARMv6
|
|
{ "MRS", MakeMatcher<0>("----00010-00--------00--00000000", &Visitor::MRS) }, // ARMv3
|
|
{ "MSR", MakeMatcher<0>("----00-10-10----1111------------", &Visitor::MSR) }, // ARMv3
|
|
{ "RFE", MakeMatcher<0>("----0001101-0000---------110----", &Visitor::RFE) }, // ARMv6
|
|
{ "SRS", MakeMatcher<0>("0000011--0-00000000000000001----", &Visitor::SRS) }, // ARMv6
|
|
}};
|
|
|
|
boost::optional<const Instruction&> DecodeArm(u32 i) {
|
|
auto iterator = std::find_if(arm_instruction_table.cbegin(), arm_instruction_table.cend(), [i](const Instruction& instruction) {
|
|
return instruction.Match(i);
|
|
});
|
|
|
|
return iterator != arm_instruction_table.cend() ? boost::make_optional<const Instruction&>(*iterator) : boost::none;
|
|
}
|
|
|
|
} // namespace ArmDecoder
|