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citra 2017-10-19 19:39:06 +01:00
parent adcbdb2b5f
commit 4806b2c242
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src/video_core/command_processor.cpp
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@ -424,7 +424,7 @@ static void WritePicaReg(u32 id, u32 value, u32 mask) {
auto& thread_pool = Common::ThreadPool::GetPool();
std::vector<std::future<void>> futures;
constexpr unsigned int MIN_VERTICES_PER_THREAD = 10;
constexpr unsigned int MIN_VERTICES_PER_THREAD = 15;
unsigned int vs_threads = regs.pipeline.num_vertices / MIN_VERTICES_PER_THREAD;
vs_threads = std::min(vs_threads, std::thread::hardware_concurrency() - 1);