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722 lines
32 KiB
C++
722 lines
32 KiB
C++
// Copyright 2014 Citra Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <array>
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#include <cstddef>
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#include <future>
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#include <memory>
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#include <utility>
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#include "common/assert.h"
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#include "common/logging/log.h"
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#include "common/microprofile.h"
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#include "common/thread_pool.h"
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#include "common/vector_math.h"
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#include "core/hle/service/gsp_gpu.h"
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#include "core/hw/gpu.h"
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#include "core/memory.h"
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#include "core/tracer/recorder.h"
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#include "video_core/command_processor.h"
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#include "video_core/debug_utils/debug_utils.h"
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#include "video_core/pica_state.h"
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#include "video_core/pica_types.h"
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#include "video_core/primitive_assembly.h"
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#include "video_core/rasterizer_interface.h"
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#include "video_core/regs.h"
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#include "video_core/regs_pipeline.h"
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#include "video_core/regs_texturing.h"
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#include "video_core/renderer_base.h"
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#include "video_core/shader/shader.h"
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#include "video_core/vertex_loader.h"
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#include "video_core/video_core.h"
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namespace Pica {
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namespace CommandProcessor {
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static int vs_float_regs_counter = 0;
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static u32 vs_uniform_write_buffer[4];
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static int gs_float_regs_counter = 0;
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static u32 gs_uniform_write_buffer[4];
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static int default_attr_counter = 0;
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static u32 default_attr_write_buffer[3];
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// Expand a 4-bit mask to 4-byte mask, e.g. 0b0101 -> 0x00FF00FF
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static const u32 expand_bits_to_bytes[] = {
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0x00000000, 0x000000ff, 0x0000ff00, 0x0000ffff, 0x00ff0000, 0x00ff00ff, 0x00ffff00, 0x00ffffff,
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0xff000000, 0xff0000ff, 0xff00ff00, 0xff00ffff, 0xffff0000, 0xffff00ff, 0xffffff00, 0xffffffff,
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};
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MICROPROFILE_DEFINE(GPU_Drawing, "GPU", "Drawing", MP_RGB(50, 50, 240));
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static const char* GetShaderSetupTypeName(Shader::ShaderSetup& setup) {
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if (&setup == &g_state.vs) {
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return "vertex shader";
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}
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if (&setup == &g_state.gs) {
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return "geometry shader";
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}
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return "unknown shader";
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}
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static void WriteUniformBoolReg(Shader::ShaderSetup& setup, u32 value) {
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for (unsigned i = 0; i < setup.uniforms.b.size(); ++i)
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setup.uniforms.b[i] = (value & (1 << i)) != 0;
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}
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static void WriteUniformIntReg(Shader::ShaderSetup& setup, unsigned index,
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const Math::Vec4<u8>& values) {
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ASSERT(index < setup.uniforms.i.size());
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setup.uniforms.i[index] = values;
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LOG_TRACE(HW_GPU, "Set %s integer uniform %d to %02x %02x %02x %02x",
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GetShaderSetupTypeName(setup), index, values.x, values.y, values.z, values.w);
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}
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static void WriteUniformFloatReg(ShaderRegs& config, Shader::ShaderSetup& setup,
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int& float_regs_counter, u32 uniform_write_buffer[4], u32 value) {
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auto& uniform_setup = config.uniform_setup;
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// TODO: Does actual hardware indeed keep an intermediate buffer or does
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// it directly write the values?
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uniform_write_buffer[float_regs_counter++] = value;
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// Uniforms are written in a packed format such that four float24 values are encoded in
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// three 32-bit numbers. We write to internal memory once a full such vector is
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// written.
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if ((float_regs_counter >= 4 && uniform_setup.IsFloat32()) ||
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(float_regs_counter >= 3 && !uniform_setup.IsFloat32())) {
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float_regs_counter = 0;
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auto& uniform = setup.uniforms.f[uniform_setup.index];
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if (uniform_setup.index >= 96) {
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LOG_ERROR(HW_GPU, "Invalid %s float uniform index %d", GetShaderSetupTypeName(setup),
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(int)uniform_setup.index);
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} else {
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// NOTE: The destination component order indeed is "backwards"
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if (uniform_setup.IsFloat32()) {
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for (auto i : {0, 1, 2, 3})
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uniform[3 - i] = float24::FromFloat32(*(float*)(&uniform_write_buffer[i]));
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} else {
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// TODO: Untested
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uniform.w = float24::FromRaw(uniform_write_buffer[0] >> 8);
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uniform.z = float24::FromRaw(((uniform_write_buffer[0] & 0xFF) << 16) |
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((uniform_write_buffer[1] >> 16) & 0xFFFF));
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uniform.y = float24::FromRaw(((uniform_write_buffer[1] & 0xFFFF) << 8) |
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((uniform_write_buffer[2] >> 24) & 0xFF));
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uniform.x = float24::FromRaw(uniform_write_buffer[2] & 0xFFFFFF);
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}
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LOG_TRACE(HW_GPU, "Set %s float uniform %x to (%f %f %f %f)",
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GetShaderSetupTypeName(setup), (int)uniform_setup.index,
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uniform.x.ToFloat32(), uniform.y.ToFloat32(), uniform.z.ToFloat32(),
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uniform.w.ToFloat32());
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// TODO: Verify that this actually modifies the register!
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uniform_setup.index.Assign(uniform_setup.index + 1);
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}
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}
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}
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static void WritePicaReg(u32 id, u32 value, u32 mask) {
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auto& regs = g_state.regs;
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if (id >= Regs::NUM_REGS) {
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LOG_ERROR(HW_GPU,
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"Commandlist tried to write to invalid register 0x%03X (value: %08X, mask: %X)",
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id, value, mask);
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return;
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}
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// TODO: Figure out how register masking acts on e.g. vs.uniform_setup.set_value
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u32 old_value = regs.reg_array[id];
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const u32 write_mask = expand_bits_to_bytes[mask];
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regs.reg_array[id] = (old_value & ~write_mask) | (value & write_mask);
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// Double check for is_pica_tracing to avoid call overhead
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if (DebugUtils::IsPicaTracing()) {
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DebugUtils::OnPicaRegWrite({(u16)id, (u16)mask, regs.reg_array[id]});
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}
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if (g_debug_context)
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g_debug_context->OnEvent(DebugContext::Event::PicaCommandLoaded,
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reinterpret_cast<void*>(&id));
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switch (id) {
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// Trigger IRQ
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case PICA_REG_INDEX(trigger_irq):
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Service::GSP::SignalInterrupt(Service::GSP::InterruptId::P3D);
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break;
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case PICA_REG_INDEX(pipeline.triangle_topology):
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g_state.primitive_assembler.Reconfigure(regs.pipeline.triangle_topology);
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break;
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case PICA_REG_INDEX(pipeline.restart_primitive):
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g_state.primitive_assembler.Reset();
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break;
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case PICA_REG_INDEX(pipeline.vs_default_attributes_setup.index):
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g_state.immediate.current_attribute = 0;
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g_state.immediate.reset_geometry_pipeline = true;
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default_attr_counter = 0;
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break;
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// Load default vertex input attributes
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case PICA_REG_INDEX_WORKAROUND(pipeline.vs_default_attributes_setup.set_value[0], 0x233):
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case PICA_REG_INDEX_WORKAROUND(pipeline.vs_default_attributes_setup.set_value[1], 0x234):
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case PICA_REG_INDEX_WORKAROUND(pipeline.vs_default_attributes_setup.set_value[2], 0x235): {
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// TODO: Does actual hardware indeed keep an intermediate buffer or does
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// it directly write the values?
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default_attr_write_buffer[default_attr_counter++] = value;
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// Default attributes are written in a packed format such that four float24 values are
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// encoded in
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// three 32-bit numbers. We write to internal memory once a full such vector is
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// written.
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if (default_attr_counter >= 3) {
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default_attr_counter = 0;
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auto& setup = regs.pipeline.vs_default_attributes_setup;
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if (setup.index >= 16) {
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LOG_ERROR(HW_GPU, "Invalid VS default attribute index %d", (int)setup.index);
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break;
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}
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Math::Vec4<float24> attribute;
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// NOTE: The destination component order indeed is "backwards"
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attribute.w = float24::FromRaw(default_attr_write_buffer[0] >> 8);
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attribute.z = float24::FromRaw(((default_attr_write_buffer[0] & 0xFF) << 16) |
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((default_attr_write_buffer[1] >> 16) & 0xFFFF));
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attribute.y = float24::FromRaw(((default_attr_write_buffer[1] & 0xFFFF) << 8) |
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((default_attr_write_buffer[2] >> 24) & 0xFF));
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attribute.x = float24::FromRaw(default_attr_write_buffer[2] & 0xFFFFFF);
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LOG_TRACE(HW_GPU, "Set default VS attribute %x to (%f %f %f %f)", (int)setup.index,
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attribute.x.ToFloat32(), attribute.y.ToFloat32(), attribute.z.ToFloat32(),
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attribute.w.ToFloat32());
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// TODO: Verify that this actually modifies the register!
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if (setup.index < 15) {
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g_state.input_default_attributes.attr[setup.index] = attribute;
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setup.index++;
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} else {
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// Put each attribute into an immediate input buffer. When all specified immediate
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// attributes are present, the Vertex Shader is invoked and everything is sent to
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// the primitive assembler.
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auto& immediate_input = g_state.immediate.input_vertex;
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auto& immediate_attribute_id = g_state.immediate.current_attribute;
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immediate_input.attr[immediate_attribute_id] = attribute;
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if (immediate_attribute_id < regs.pipeline.max_input_attrib_index) {
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immediate_attribute_id += 1;
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} else {
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MICROPROFILE_SCOPE(GPU_Drawing);
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immediate_attribute_id = 0;
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auto* shader_engine = Shader::GetEngine();
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shader_engine->SetupBatch(g_state.vs, regs.vs.main_offset);
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// Send to vertex shader
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if (g_debug_context)
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g_debug_context->OnEvent(DebugContext::Event::VertexShaderInvocation,
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static_cast<void*>(&immediate_input));
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Shader::UnitState shader_unit;
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Shader::AttributeBuffer output{};
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shader_unit.LoadInput(regs.vs, immediate_input);
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shader_engine->Run(g_state.vs, shader_unit);
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shader_unit.WriteOutput(regs.vs, output);
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// Send to geometry pipeline
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if (g_state.immediate.reset_geometry_pipeline) {
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g_state.geometry_pipeline.Reconfigure();
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g_state.immediate.reset_geometry_pipeline = false;
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}
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ASSERT(!g_state.geometry_pipeline.NeedIndexInput());
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g_state.geometry_pipeline.Setup(shader_engine);
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g_state.geometry_pipeline.SubmitVertex(output);
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// TODO: If drawing after every immediate mode triangle kills performance,
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// change it to flush triangles whenever a drawing config register changes
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// See: https://github.com/citra-emu/citra/pull/2866#issuecomment-327011550
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VideoCore::g_renderer->Rasterizer()->DrawTriangles();
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if (g_debug_context) {
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g_debug_context->OnEvent(DebugContext::Event::FinishedPrimitiveBatch,
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nullptr);
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}
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}
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}
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}
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break;
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}
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case PICA_REG_INDEX(pipeline.gpu_mode):
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// This register likely just enables vertex processing and doesn't need any special handling
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break;
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case PICA_REG_INDEX_WORKAROUND(pipeline.command_buffer.trigger[0], 0x23c):
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case PICA_REG_INDEX_WORKAROUND(pipeline.command_buffer.trigger[1], 0x23d): {
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unsigned index =
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static_cast<unsigned>(id - PICA_REG_INDEX(pipeline.command_buffer.trigger[0]));
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u32* head_ptr = (u32*)Memory::GetPhysicalPointer(
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regs.pipeline.command_buffer.GetPhysicalAddress(index));
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g_state.cmd_list.head_ptr = g_state.cmd_list.current_ptr = head_ptr;
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g_state.cmd_list.length = regs.pipeline.command_buffer.GetSize(index) / sizeof(u32);
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break;
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}
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// It seems like these trigger vertex rendering
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case PICA_REG_INDEX(pipeline.trigger_draw):
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case PICA_REG_INDEX(pipeline.trigger_draw_indexed): {
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MICROPROFILE_SCOPE(GPU_Drawing);
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const bool is_indexed = (id == PICA_REG_INDEX(pipeline.trigger_draw_indexed));
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#if PICA_LOG_TEV
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DebugUtils::DumpTevStageConfig(regs.GetTevStages());
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#endif
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if (g_debug_context)
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g_debug_context->OnEvent(DebugContext::Event::IncomingPrimitiveBatch, nullptr);
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struct CachedVertex {
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explicit CachedVertex() : batch(0), lock{ ATOMIC_FLAG_INIT } {}
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CachedVertex(const CachedVertex& other) : CachedVertex() {}
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union {
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Shader::AttributeBuffer output_attr; // GS used
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Shader::OutputVertex output_vertex; // No GS
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};
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std::atomic<u32> batch;
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std::atomic_flag lock;
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};
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static std::vector<CachedVertex> vs_output(0x10000);
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if (!is_indexed && vs_output.size() < regs.pipeline.num_vertices)
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vs_output.resize(regs.pipeline.num_vertices);
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// used as a mean to invalidate data from the previous batch without clearing it
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static u32 batch_id = std::numeric_limits<u32>::max();
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++batch_id;
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if (batch_id == 0) { // reset cache when id overflows for safety
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++batch_id;
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for (auto& entry : vs_output)
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entry.batch = 0;
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}
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// Processes information about internal vertex attributes to figure out how a vertex is
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// loaded.
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// Later, these can be compiled and cached.
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const u32 base_address = regs.pipeline.vertex_attributes.GetPhysicalBaseAddress();
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VertexLoader loader(regs.pipeline);
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const auto& index_info = regs.pipeline.index_array;
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const u8* index_address_8 = Memory::GetPhysicalPointer(base_address + index_info.offset);
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if (!index_address_8) {
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LOG_CRITICAL(HW_GPU, "Invalid index_address_8 %08x", index_address_8);
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return;
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}
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const u16* index_address_16 = reinterpret_cast<const u16*>(index_address_8);
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bool index_u16 = index_info.format != 0;
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auto VertexIndex = [&](unsigned int index) {
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// Indexed rendering doesn't use the start offset
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return is_indexed ? (index_u16 ? index_address_16[index] : index_address_8[index])
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: (index + regs.pipeline.vertex_offset);
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};
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PrimitiveAssembler<Shader::OutputVertex>& primitive_assembler = g_state.primitive_assembler;
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if (g_debug_context && g_debug_context->recorder) {
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for (int i = 0; i < 3; ++i) {
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const auto texture = regs.texturing.GetTextures()[i];
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if (!texture.enabled)
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continue;
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u8* texture_data = Memory::GetPhysicalPointer(texture.config.GetPhysicalAddress());
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g_debug_context->recorder->MemoryAccessed(
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texture_data, Pica::TexturingRegs::NibblesPerPixel(texture.format) *
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texture.config.width / 2 * texture.config.height,
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texture.config.GetPhysicalAddress());
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}
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}
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DebugUtils::MemoryAccessTracker memory_accesses;
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auto* shader_engine = Shader::GetEngine();
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shader_engine->SetupBatch(g_state.vs, regs.vs.main_offset);
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const bool use_gs = regs.pipeline.use_gs == PipelineRegs::UseGS::Yes;
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auto VSUnitLoop = [&](u32 thread_id, auto num_threads) {
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constexpr bool single_thread = std::is_same_v<std::integral_constant<u32, 1>, decltype(num_threads)>;
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Shader::UnitState shader_unit;
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for (unsigned int index = thread_id; index < regs.pipeline.num_vertices; index += num_threads) {
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unsigned int vertex = VertexIndex(index);
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auto& cached_vertex = vs_output[is_indexed ? vertex : index];
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// -1 is a common special value used for primitive restart. Since it's unknown if
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// the PICA supports it, and it would mess up the caching, guard against it here.
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ASSERT(vertex != -1);
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if (is_indexed) {
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if (g_debug_context && Pica::g_debug_context->recorder) {
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int size = index_u16 ? 2 : 1;
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memory_accesses.AddAccess(base_address + index_info.offset + size * index,
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size);
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}
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if (!single_thread) {
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// Try locking this vertex
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if (cached_vertex.lock.test_and_set(std::memory_order_acquire)) {
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// Another thread is processing this vertex
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continue;
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}
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// Vertex is not being processed and is from the correct batch
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else if (cached_vertex.batch.load(std::memory_order_acquire) == batch_id) {
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// Unlock
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cached_vertex.lock.clear(std::memory_order_release);
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continue;
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}
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}
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else if (cached_vertex.batch.load(std::memory_order_relaxed) == batch_id) {
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continue;
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}
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}
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Shader::AttributeBuffer attribute_buffer;
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Shader::AttributeBuffer& output_attr = use_gs ? cached_vertex.output_attr : attribute_buffer;
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// Initialize data for the current vertex
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loader.LoadVertex(base_address, index, vertex, attribute_buffer, memory_accesses);
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// Send to vertex shader
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if (g_debug_context)
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g_debug_context->OnEvent(DebugContext::Event::VertexShaderInvocation, &attribute_buffer);
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shader_unit.LoadInput(regs.vs, attribute_buffer);
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shader_engine->Run(g_state.vs, shader_unit);
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shader_unit.WriteOutput(regs.vs, output_attr);
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if (!use_gs)
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cached_vertex.output_vertex = Shader::OutputVertex::FromAttributeBuffer(regs.rasterizer, output_attr);
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if (!single_thread) {
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cached_vertex.batch.store(batch_id, std::memory_order_release);
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if (is_indexed) {
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cached_vertex.lock.clear(std::memory_order_release);
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}
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}
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else if (is_indexed) {
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cached_vertex.batch.store(batch_id, std::memory_order_relaxed);
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}
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}
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};
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auto& thread_pool = Common::ThreadPool::GetPool();
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std::vector<std::future<void>> futures;
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constexpr unsigned int MIN_VERTICES_PER_THREAD = 15;
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unsigned int vs_threads = regs.pipeline.num_vertices / MIN_VERTICES_PER_THREAD;
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vs_threads = std::min(vs_threads, std::thread::hardware_concurrency() - 1);
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if (!vs_threads) {
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VSUnitLoop(0, std::integral_constant<u32, 1>{});
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} else {
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for (unsigned int thread_id = 0; thread_id < vs_threads; ++thread_id) {
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futures.emplace_back(thread_pool.push(VSUnitLoop, thread_id, vs_threads));
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}
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}
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g_state.geometry_pipeline.Reconfigure();
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g_state.geometry_pipeline.Setup(shader_engine);
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if (g_state.geometry_pipeline.NeedIndexInput())
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ASSERT(is_indexed);
|
|
|
|
for (unsigned int index = 0; index < regs.pipeline.num_vertices; ++index) {
|
|
unsigned int vertex = VertexIndex(index);
|
|
auto& cached_vertex = vs_output[is_indexed ? vertex : index];
|
|
|
|
if (use_gs && is_indexed && g_state.geometry_pipeline.NeedIndexInput()) {
|
|
g_state.geometry_pipeline.SubmitIndex(vertex);
|
|
continue;
|
|
}
|
|
|
|
// Synchronize threads
|
|
if (vs_threads) {
|
|
while (cached_vertex.batch.load(std::memory_order_acquire) != batch_id) {
|
|
std::this_thread::yield();
|
|
}
|
|
}
|
|
|
|
if (use_gs) {
|
|
// Send to geometry pipeline
|
|
g_state.geometry_pipeline.SubmitVertex(cached_vertex.output_attr);
|
|
} else {
|
|
primitive_assembler.SubmitVertex(cached_vertex.output_vertex,
|
|
std::bind(&std::decay_t<decltype(*VideoCore::g_renderer->Rasterizer())>::AddTriangle,
|
|
VideoCore::g_renderer->Rasterizer(),
|
|
std::placeholders::_1, std::placeholders::_2, std::placeholders::_3));
|
|
}
|
|
}
|
|
|
|
for (auto& future : futures)
|
|
future.get();
|
|
|
|
for (auto& range : memory_accesses.ranges) {
|
|
g_debug_context->recorder->MemoryAccessed(Memory::GetPhysicalPointer(range.first),
|
|
range.second, range.first);
|
|
}
|
|
|
|
VideoCore::g_renderer->Rasterizer()->DrawTriangles();
|
|
|
|
if (g_debug_context) {
|
|
g_debug_context->OnEvent(DebugContext::Event::FinishedPrimitiveBatch, nullptr);
|
|
}
|
|
|
|
break;
|
|
}
|
|
|
|
case PICA_REG_INDEX(gs.bool_uniforms):
|
|
WriteUniformBoolReg(g_state.gs, g_state.regs.gs.bool_uniforms.Value());
|
|
break;
|
|
|
|
case PICA_REG_INDEX_WORKAROUND(gs.int_uniforms[0], 0x281):
|
|
case PICA_REG_INDEX_WORKAROUND(gs.int_uniforms[1], 0x282):
|
|
case PICA_REG_INDEX_WORKAROUND(gs.int_uniforms[2], 0x283):
|
|
case PICA_REG_INDEX_WORKAROUND(gs.int_uniforms[3], 0x284): {
|
|
unsigned index = (id - PICA_REG_INDEX_WORKAROUND(gs.int_uniforms[0], 0x281));
|
|
auto values = regs.gs.int_uniforms[index];
|
|
WriteUniformIntReg(g_state.gs, index,
|
|
Math::Vec4<u8>(values.x, values.y, values.z, values.w));
|
|
break;
|
|
}
|
|
|
|
case PICA_REG_INDEX_WORKAROUND(gs.uniform_setup.set_value[0], 0x291):
|
|
case PICA_REG_INDEX_WORKAROUND(gs.uniform_setup.set_value[1], 0x292):
|
|
case PICA_REG_INDEX_WORKAROUND(gs.uniform_setup.set_value[2], 0x293):
|
|
case PICA_REG_INDEX_WORKAROUND(gs.uniform_setup.set_value[3], 0x294):
|
|
case PICA_REG_INDEX_WORKAROUND(gs.uniform_setup.set_value[4], 0x295):
|
|
case PICA_REG_INDEX_WORKAROUND(gs.uniform_setup.set_value[5], 0x296):
|
|
case PICA_REG_INDEX_WORKAROUND(gs.uniform_setup.set_value[6], 0x297):
|
|
case PICA_REG_INDEX_WORKAROUND(gs.uniform_setup.set_value[7], 0x298): {
|
|
WriteUniformFloatReg(g_state.regs.gs, g_state.gs, gs_float_regs_counter,
|
|
gs_uniform_write_buffer, value);
|
|
break;
|
|
}
|
|
|
|
case PICA_REG_INDEX_WORKAROUND(gs.program.set_word[0], 0x29c):
|
|
case PICA_REG_INDEX_WORKAROUND(gs.program.set_word[1], 0x29d):
|
|
case PICA_REG_INDEX_WORKAROUND(gs.program.set_word[2], 0x29e):
|
|
case PICA_REG_INDEX_WORKAROUND(gs.program.set_word[3], 0x29f):
|
|
case PICA_REG_INDEX_WORKAROUND(gs.program.set_word[4], 0x2a0):
|
|
case PICA_REG_INDEX_WORKAROUND(gs.program.set_word[5], 0x2a1):
|
|
case PICA_REG_INDEX_WORKAROUND(gs.program.set_word[6], 0x2a2):
|
|
case PICA_REG_INDEX_WORKAROUND(gs.program.set_word[7], 0x2a3): {
|
|
u32& offset = g_state.regs.gs.program.offset;
|
|
if (offset >= 4096) {
|
|
LOG_ERROR(HW_GPU, "Invalid GS program offset %u", offset);
|
|
} else {
|
|
g_state.gs.program_code[offset] = value;
|
|
offset++;
|
|
}
|
|
break;
|
|
}
|
|
|
|
case PICA_REG_INDEX_WORKAROUND(gs.swizzle_patterns.set_word[0], 0x2a6):
|
|
case PICA_REG_INDEX_WORKAROUND(gs.swizzle_patterns.set_word[1], 0x2a7):
|
|
case PICA_REG_INDEX_WORKAROUND(gs.swizzle_patterns.set_word[2], 0x2a8):
|
|
case PICA_REG_INDEX_WORKAROUND(gs.swizzle_patterns.set_word[3], 0x2a9):
|
|
case PICA_REG_INDEX_WORKAROUND(gs.swizzle_patterns.set_word[4], 0x2aa):
|
|
case PICA_REG_INDEX_WORKAROUND(gs.swizzle_patterns.set_word[5], 0x2ab):
|
|
case PICA_REG_INDEX_WORKAROUND(gs.swizzle_patterns.set_word[6], 0x2ac):
|
|
case PICA_REG_INDEX_WORKAROUND(gs.swizzle_patterns.set_word[7], 0x2ad): {
|
|
u32& offset = g_state.regs.gs.swizzle_patterns.offset;
|
|
if (offset >= g_state.gs.swizzle_data.size()) {
|
|
LOG_ERROR(HW_GPU, "Invalid GS swizzle pattern offset %u", offset);
|
|
} else {
|
|
g_state.gs.swizzle_data[offset] = value;
|
|
offset++;
|
|
}
|
|
break;
|
|
}
|
|
|
|
case PICA_REG_INDEX(vs.bool_uniforms):
|
|
// TODO (wwylele): does regs.pipeline.gs_unit_exclusive_configuration affect this?
|
|
WriteUniformBoolReg(g_state.vs, g_state.regs.vs.bool_uniforms.Value());
|
|
break;
|
|
|
|
case PICA_REG_INDEX_WORKAROUND(vs.int_uniforms[0], 0x2b1):
|
|
case PICA_REG_INDEX_WORKAROUND(vs.int_uniforms[1], 0x2b2):
|
|
case PICA_REG_INDEX_WORKAROUND(vs.int_uniforms[2], 0x2b3):
|
|
case PICA_REG_INDEX_WORKAROUND(vs.int_uniforms[3], 0x2b4): {
|
|
// TODO (wwylele): does regs.pipeline.gs_unit_exclusive_configuration affect this?
|
|
unsigned index = (id - PICA_REG_INDEX_WORKAROUND(vs.int_uniforms[0], 0x2b1));
|
|
auto values = regs.vs.int_uniforms[index];
|
|
WriteUniformIntReg(g_state.vs, index,
|
|
Math::Vec4<u8>(values.x, values.y, values.z, values.w));
|
|
break;
|
|
}
|
|
|
|
case PICA_REG_INDEX_WORKAROUND(vs.uniform_setup.set_value[0], 0x2c1):
|
|
case PICA_REG_INDEX_WORKAROUND(vs.uniform_setup.set_value[1], 0x2c2):
|
|
case PICA_REG_INDEX_WORKAROUND(vs.uniform_setup.set_value[2], 0x2c3):
|
|
case PICA_REG_INDEX_WORKAROUND(vs.uniform_setup.set_value[3], 0x2c4):
|
|
case PICA_REG_INDEX_WORKAROUND(vs.uniform_setup.set_value[4], 0x2c5):
|
|
case PICA_REG_INDEX_WORKAROUND(vs.uniform_setup.set_value[5], 0x2c6):
|
|
case PICA_REG_INDEX_WORKAROUND(vs.uniform_setup.set_value[6], 0x2c7):
|
|
case PICA_REG_INDEX_WORKAROUND(vs.uniform_setup.set_value[7], 0x2c8): {
|
|
// TODO (wwylele): does regs.pipeline.gs_unit_exclusive_configuration affect this?
|
|
WriteUniformFloatReg(g_state.regs.vs, g_state.vs, vs_float_regs_counter,
|
|
vs_uniform_write_buffer, value);
|
|
break;
|
|
}
|
|
|
|
case PICA_REG_INDEX_WORKAROUND(vs.program.set_word[0], 0x2cc):
|
|
case PICA_REG_INDEX_WORKAROUND(vs.program.set_word[1], 0x2cd):
|
|
case PICA_REG_INDEX_WORKAROUND(vs.program.set_word[2], 0x2ce):
|
|
case PICA_REG_INDEX_WORKAROUND(vs.program.set_word[3], 0x2cf):
|
|
case PICA_REG_INDEX_WORKAROUND(vs.program.set_word[4], 0x2d0):
|
|
case PICA_REG_INDEX_WORKAROUND(vs.program.set_word[5], 0x2d1):
|
|
case PICA_REG_INDEX_WORKAROUND(vs.program.set_word[6], 0x2d2):
|
|
case PICA_REG_INDEX_WORKAROUND(vs.program.set_word[7], 0x2d3): {
|
|
u32& offset = g_state.regs.vs.program.offset;
|
|
if (offset >= 512) {
|
|
LOG_ERROR(HW_GPU, "Invalid VS program offset %u", offset);
|
|
} else {
|
|
g_state.vs.program_code[offset] = value;
|
|
if (!g_state.regs.pipeline.gs_unit_exclusive_configuration) {
|
|
g_state.gs.program_code[offset] = value;
|
|
}
|
|
offset++;
|
|
}
|
|
break;
|
|
}
|
|
|
|
case PICA_REG_INDEX_WORKAROUND(vs.swizzle_patterns.set_word[0], 0x2d6):
|
|
case PICA_REG_INDEX_WORKAROUND(vs.swizzle_patterns.set_word[1], 0x2d7):
|
|
case PICA_REG_INDEX_WORKAROUND(vs.swizzle_patterns.set_word[2], 0x2d8):
|
|
case PICA_REG_INDEX_WORKAROUND(vs.swizzle_patterns.set_word[3], 0x2d9):
|
|
case PICA_REG_INDEX_WORKAROUND(vs.swizzle_patterns.set_word[4], 0x2da):
|
|
case PICA_REG_INDEX_WORKAROUND(vs.swizzle_patterns.set_word[5], 0x2db):
|
|
case PICA_REG_INDEX_WORKAROUND(vs.swizzle_patterns.set_word[6], 0x2dc):
|
|
case PICA_REG_INDEX_WORKAROUND(vs.swizzle_patterns.set_word[7], 0x2dd): {
|
|
u32& offset = g_state.regs.vs.swizzle_patterns.offset;
|
|
if (offset >= g_state.vs.swizzle_data.size()) {
|
|
LOG_ERROR(HW_GPU, "Invalid VS swizzle pattern offset %u", offset);
|
|
} else {
|
|
g_state.vs.swizzle_data[offset] = value;
|
|
if (!g_state.regs.pipeline.gs_unit_exclusive_configuration) {
|
|
g_state.gs.swizzle_data[offset] = value;
|
|
}
|
|
offset++;
|
|
}
|
|
break;
|
|
}
|
|
|
|
case PICA_REG_INDEX_WORKAROUND(lighting.lut_data[0], 0x1c8):
|
|
case PICA_REG_INDEX_WORKAROUND(lighting.lut_data[1], 0x1c9):
|
|
case PICA_REG_INDEX_WORKAROUND(lighting.lut_data[2], 0x1ca):
|
|
case PICA_REG_INDEX_WORKAROUND(lighting.lut_data[3], 0x1cb):
|
|
case PICA_REG_INDEX_WORKAROUND(lighting.lut_data[4], 0x1cc):
|
|
case PICA_REG_INDEX_WORKAROUND(lighting.lut_data[5], 0x1cd):
|
|
case PICA_REG_INDEX_WORKAROUND(lighting.lut_data[6], 0x1ce):
|
|
case PICA_REG_INDEX_WORKAROUND(lighting.lut_data[7], 0x1cf): {
|
|
auto& lut_config = regs.lighting.lut_config;
|
|
|
|
ASSERT_MSG(lut_config.index < 256, "lut_config.index exceeded maximum value of 255!");
|
|
|
|
g_state.lighting.luts[lut_config.type][lut_config.index].raw = value;
|
|
lut_config.index.Assign(lut_config.index + 1);
|
|
break;
|
|
}
|
|
|
|
case PICA_REG_INDEX_WORKAROUND(texturing.fog_lut_data[0], 0xe8):
|
|
case PICA_REG_INDEX_WORKAROUND(texturing.fog_lut_data[1], 0xe9):
|
|
case PICA_REG_INDEX_WORKAROUND(texturing.fog_lut_data[2], 0xea):
|
|
case PICA_REG_INDEX_WORKAROUND(texturing.fog_lut_data[3], 0xeb):
|
|
case PICA_REG_INDEX_WORKAROUND(texturing.fog_lut_data[4], 0xec):
|
|
case PICA_REG_INDEX_WORKAROUND(texturing.fog_lut_data[5], 0xed):
|
|
case PICA_REG_INDEX_WORKAROUND(texturing.fog_lut_data[6], 0xee):
|
|
case PICA_REG_INDEX_WORKAROUND(texturing.fog_lut_data[7], 0xef): {
|
|
g_state.fog.lut[regs.texturing.fog_lut_offset % 128].raw = value;
|
|
regs.texturing.fog_lut_offset.Assign(regs.texturing.fog_lut_offset + 1);
|
|
break;
|
|
}
|
|
|
|
case PICA_REG_INDEX_WORKAROUND(texturing.proctex_lut_data[0], 0xb0):
|
|
case PICA_REG_INDEX_WORKAROUND(texturing.proctex_lut_data[1], 0xb1):
|
|
case PICA_REG_INDEX_WORKAROUND(texturing.proctex_lut_data[2], 0xb2):
|
|
case PICA_REG_INDEX_WORKAROUND(texturing.proctex_lut_data[3], 0xb3):
|
|
case PICA_REG_INDEX_WORKAROUND(texturing.proctex_lut_data[4], 0xb4):
|
|
case PICA_REG_INDEX_WORKAROUND(texturing.proctex_lut_data[5], 0xb5):
|
|
case PICA_REG_INDEX_WORKAROUND(texturing.proctex_lut_data[6], 0xb6):
|
|
case PICA_REG_INDEX_WORKAROUND(texturing.proctex_lut_data[7], 0xb7): {
|
|
auto& index = regs.texturing.proctex_lut_config.index;
|
|
auto& pt = g_state.proctex;
|
|
|
|
switch (regs.texturing.proctex_lut_config.ref_table.Value()) {
|
|
case TexturingRegs::ProcTexLutTable::Noise:
|
|
pt.noise_table[index % pt.noise_table.size()].raw = value;
|
|
break;
|
|
case TexturingRegs::ProcTexLutTable::ColorMap:
|
|
pt.color_map_table[index % pt.color_map_table.size()].raw = value;
|
|
break;
|
|
case TexturingRegs::ProcTexLutTable::AlphaMap:
|
|
pt.alpha_map_table[index % pt.alpha_map_table.size()].raw = value;
|
|
break;
|
|
case TexturingRegs::ProcTexLutTable::Color:
|
|
pt.color_table[index % pt.color_table.size()].raw = value;
|
|
break;
|
|
case TexturingRegs::ProcTexLutTable::ColorDiff:
|
|
pt.color_diff_table[index % pt.color_diff_table.size()].raw = value;
|
|
break;
|
|
}
|
|
index.Assign(index + 1);
|
|
break;
|
|
}
|
|
default:
|
|
break;
|
|
}
|
|
|
|
VideoCore::g_renderer->Rasterizer()->NotifyPicaRegisterChanged(id);
|
|
|
|
if (g_debug_context)
|
|
g_debug_context->OnEvent(DebugContext::Event::PicaCommandProcessed,
|
|
reinterpret_cast<void*>(&id));
|
|
}
|
|
|
|
void ProcessCommandList(const u32* list, u32 size) {
|
|
g_state.cmd_list.head_ptr = g_state.cmd_list.current_ptr = list;
|
|
g_state.cmd_list.length = size / sizeof(u32);
|
|
|
|
while (g_state.cmd_list.current_ptr < g_state.cmd_list.head_ptr + g_state.cmd_list.length) {
|
|
|
|
// Align read pointer to 8 bytes
|
|
if ((g_state.cmd_list.head_ptr - g_state.cmd_list.current_ptr) % 2 != 0)
|
|
++g_state.cmd_list.current_ptr;
|
|
|
|
u32 value = *g_state.cmd_list.current_ptr++;
|
|
const CommandHeader header = {*g_state.cmd_list.current_ptr++};
|
|
|
|
WritePicaReg(header.cmd_id, value, header.parameter_mask);
|
|
|
|
for (unsigned i = 0; i < header.extra_data_length; ++i) {
|
|
u32 cmd = header.cmd_id + (header.group_commands ? i + 1 : 0);
|
|
WritePicaReg(cmd, *g_state.cmd_list.current_ptr++, header.parameter_mask);
|
|
}
|
|
}
|
|
}
|
|
|
|
} // namespace CommandProcessor
|
|
|
|
} // namespace Pica
|