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477d616f7d
Constant buffer values on the shader IR were using different offsets if the access direct or indirect. cbuf34 has a non-multiplied offset while cbuf36 does. On shader decoding this commit multiplies it by four on cbuf34 queries.
55 lines
1.8 KiB
C++
55 lines
1.8 KiB
C++
// Copyright 2018 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "common/assert.h"
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#include "common/common_types.h"
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#include "video_core/engines/shader_bytecode.h"
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#include "video_core/shader/shader_ir.h"
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namespace VideoCommon::Shader {
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using Tegra::Shader::Instruction;
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using Tegra::Shader::OpCode;
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u32 ShaderIR::DecodeShift(BasicBlock& bb, const BasicBlock& code, u32 pc) {
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const Instruction instr = {program_code[pc]};
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const auto opcode = OpCode::Decode(instr);
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const Node op_a = GetRegister(instr.gpr8);
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const Node op_b = [&]() {
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if (instr.is_b_imm) {
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return Immediate(instr.alu.GetSignedImm20_20());
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} else if (instr.is_b_gpr) {
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return GetRegister(instr.gpr20);
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} else {
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return GetConstBuffer(instr.cbuf34.index, instr.cbuf34.GetOffset());
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}
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}();
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switch (opcode->get().GetId()) {
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case OpCode::Id::SHR_C:
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case OpCode::Id::SHR_R:
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case OpCode::Id::SHR_IMM: {
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const Node value = SignedOperation(OperationCode::IArithmeticShiftRight,
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instr.shift.is_signed, PRECISE, op_a, op_b);
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SetInternalFlagsFromInteger(bb, value, instr.generates_cc);
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SetRegister(bb, instr.gpr0, value);
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break;
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}
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case OpCode::Id::SHL_C:
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case OpCode::Id::SHL_R:
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case OpCode::Id::SHL_IMM: {
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const Node value = Operation(OperationCode::ILogicalShiftLeft, PRECISE, op_a, op_b);
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SetInternalFlagsFromInteger(bb, value, instr.generates_cc);
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SetRegister(bb, instr.gpr0, value);
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break;
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}
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default:
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UNIMPLEMENTED_MSG("Unhandled shift instruction: {}", opcode->get().GetName());
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}
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return pc;
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}
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} // namespace VideoCommon::Shader
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