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Prepare Pica regs for GS
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@ -1078,7 +1078,7 @@ struct Regs {
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// Number of vertices to render
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u32 num_vertices;
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INSERT_PADDING_WORDS(0x1);
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BitField<0, 2, u32> using_geometry_shader;
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// The index of the first vertex to render
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u32 vertex_offset;
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@ -1126,7 +1126,14 @@ struct Regs {
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}
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} command_buffer;
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INSERT_PADDING_WORDS(0x07);
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INSERT_PADDING_WORDS(0x06);
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enum class VSComMode : u32 {
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Shared = 0,
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Exclusive = 1
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};
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VSComMode vs_com_mode;
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enum class GPUMode : u32 {
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Drawing = 0,
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@ -1135,7 +1142,17 @@ struct Regs {
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GPUMode gpu_mode;
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INSERT_PADDING_WORDS(0x18);
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INSERT_PADDING_WORDS(0x4);
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BitField<0, 4, u32> vs_outmap_total1;
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INSERT_PADDING_WORDS(0x6);
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BitField<0, 4, u32> vs_outmap_total2;
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BitField<0, 4, u32> gsh_misc0;
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INSERT_PADDING_WORDS(0xB);
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enum class TriangleTopology : u32 {
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List = 0,
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@ -1144,7 +1161,10 @@ struct Regs {
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Shader = 3, // Programmable setup unit implemented in a geometry shader
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};
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union {
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BitField<0, 4, u32> vs_outmap_count;
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BitField<8, 2, TriangleTopology> triangle_topology;
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};
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u32 restart_primitive;
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@ -1163,8 +1183,9 @@ struct Regs {
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INSERT_PADDING_WORDS(0x4);
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union {
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// Number of input attributes to shader unit - 1
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BitField<0, 4, u32> num_input_attributes;
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BitField<0, 4, u32> num_input_attributes; // Number of input attributes to shader unit - 1
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BitField<8, 4, u32> use_subdivision;
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BitField<24, 8, u32> use_geometry_shader;
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};
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// Offset to shader program entry point (in words)
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@ -1332,7 +1353,11 @@ ASSERT_REG_POSITION(trigger_draw, 0x22e);
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ASSERT_REG_POSITION(trigger_draw_indexed, 0x22f);
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ASSERT_REG_POSITION(vs_default_attributes_setup, 0x232);
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ASSERT_REG_POSITION(command_buffer, 0x238);
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ASSERT_REG_POSITION(vs_com_mode, 0x244);
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ASSERT_REG_POSITION(gpu_mode, 0x245);
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ASSERT_REG_POSITION(vs_outmap_total1, 0x24A);
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ASSERT_REG_POSITION(vs_outmap_total2, 0x251);
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ASSERT_REG_POSITION(gsh_misc0, 0x252);
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ASSERT_REG_POSITION(triangle_topology, 0x25e);
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ASSERT_REG_POSITION(restart_primitive, 0x25f);
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ASSERT_REG_POSITION(gs, 0x280);
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