OpenPunk/citra
1
0
Fork 0
mirror of https://github.com/citra-emu/citra.git synced 2024-11-14 17:10:06 +00:00
Code Issues Projects Releases Wiki Activity

Dyncom: Move cream cache to ARMul_State.

Browse Source
This commit is contained in:
bunnei 2015-04-27 22:44:05 -04:00
parent c7dc799e19
commit bab5abaf46
4 changed files with 18 additions and 25 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/core/arm/dyncom/arm_dyncom.cpp
View File

@ -2,6 +2,8 @@
// Licensed under GPLv2 or any later version
// Refer to the license.txt file included.
#include "common/make_unique.h"
#include "core/arm/skyeye_common/armemu.h"
#include "core/arm/skyeye_common/vfp/vfp.h"
@ -17,7 +19,7 @@ const static cpu_config_t s_arm11_cpu_info = {
};
ARM_DynCom::ARM_DynCom(PrivilegeMode initial_mode) {
state = std::unique_ptr<ARMul_State>(new ARMul_State);
state = Common::make_unique<ARMul_State>();
ARMul_NewState(state.get());
ARMul_SelectProcessor(state.get(), ARM_v6_Prop | ARM_v5_Prop | ARM_v5e_Prop);

31
src/core/arm/dyncom/arm_dyncom_interpreter.cpp
View File

@ -6,7 +6,6 @@
#include <algorithm>
#include <cstdio>
#include <unordered_map>
#include "common/logging/log.h"
#include "common/profiler.h"
@ -3533,25 +3532,6 @@ const transop_fp_t arm_instruction_trans[] = {
INTERPRETER_TRANSLATE(blx_1_thumb)
};
typedef std::unordered_map<u32, int> bb_map;
static bb_map CreamCache;
static void insert_bb(unsigned int addr, int start) {
CreamCache[addr] = start;
}
static int find_bb(unsigned int addr, int& start) {
int ret = -1;
bb_map::const_iterator it = CreamCache.find(addr);
if (it != CreamCache.end()) {
start = static_cast<int>(it->second);
ret = 0;
} else {
ret = -1;
}
return ret;
}
enum {
FETCH_SUCCESS,
FETCH_FAILURE
@ -3674,7 +3654,9 @@ translated:
}
ret = inst_base->br;
};
insert_bb(pc_start, bb_start);
cpu->instruction_cache[pc_start] = bb_start;
return KEEP_GOING;
}
@ -4001,9 +3983,14 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
phys_addr = cpu->Reg[15];
if (find_bb(cpu->Reg[15], ptr) == -1)
// Find the cached instruction cream, otherwise translate it...
auto itr = cpu->instruction_cache.find(cpu->Reg[15]);
if (itr != cpu->instruction_cache.end()) {
ptr = itr->second;
} else {
if (InterpreterTranslate(cpu, ptr, cpu->Reg[15]) == FETCH_EXCEPTION)
goto END;
}
inst_base = (arm_inst *)&inst_buf[ptr];
GOTO_NEXT_INST;

2
src/core/arm/interpreter/arminit.cpp
View File

@ -26,8 +26,6 @@
\***************************************************************************/
ARMul_State* ARMul_NewState(ARMul_State* state)
{
memset(state, 0, sizeof(ARMul_State));
state->Emulate = RUN;
state->Mode = USER32MODE;

6
src/core/arm/skyeye_common/armdefs.h
View File

@ -17,6 +17,8 @@
#pragma once
#include <unordered_map>
#include "common/common_types.h"
#include "core/arm/skyeye_common/arm_regformat.h"
#include "core/arm/skyeye_common/skyeye_defs.h"
@ -152,6 +154,10 @@ So, if lateabtSig=1, then it means Late Abort Model(Base Updated Abort Model)
// Added by ksh in 2005-10-1
cpu_config_t* cpu;
// TODO(bunnei): Move this cache to a better place - it should be per codeset (likely per
// process for our purposes), not per ARMul_State (which tracks CPU core state).
std::unordered_map<u32, int> instruction_cache;
};
/***************************************************************************\