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https://github.com/citra-emu/citra.git
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commit
9699194b54
@ -120,20 +120,15 @@ public:
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// A STL-like iterator is required to be able to use range-based for loops.
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class Iterator {
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public:
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Iterator(const Iterator& other) : m_val(other.m_val), m_bit(other.m_bit) {}
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Iterator(IntTy val) : m_val(val), m_bit(0) {}
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Iterator& operator=(Iterator other) {
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new (this) Iterator(other);
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return *this;
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}
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Iterator(const Iterator& other) : m_val(other.m_val) {}
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Iterator(IntTy val) : m_val(val) {}
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int operator*() {
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return m_bit + ComputeLsb();
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// This will never be called when m_val == 0, because that would be the end() iterator
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return LeastSignificantSetBit(m_val);
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}
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Iterator& operator++() {
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int lsb = ComputeLsb();
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m_val >>= lsb + 1;
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m_bit += lsb + 1;
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m_has_lsb = false;
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// Unset least significant set bit
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m_val &= m_val - IntTy(1);
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return *this;
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}
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Iterator operator++(int _) {
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@ -149,17 +144,7 @@ public:
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}
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private:
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int ComputeLsb() {
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if (!m_has_lsb) {
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m_lsb = LeastSignificantSetBit(m_val);
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m_has_lsb = true;
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}
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return m_lsb;
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}
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IntTy m_val;
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int m_bit;
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int m_lsb = -1;
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bool m_has_lsb = false;
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};
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BitSet() : m_val(0) {}
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@ -77,13 +77,18 @@ void UnitState::LoadInput(const ShaderRegs& config, const AttributeBuffer& input
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}
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}
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void UnitState::WriteOutput(const ShaderRegs& config, AttributeBuffer& output) {
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unsigned int output_i = 0;
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for (unsigned int reg : Common::BitSet<u32>(config.output_mask)) {
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output.attr[output_i++] = registers.output[reg];
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static void CopyRegistersToOutput(const Math::Vec4<float24>* regs, u32 mask,
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AttributeBuffer& buffer) {
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int output_i = 0;
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for (int reg : Common::BitSet<u32>(mask)) {
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buffer.attr[output_i++] = regs[reg];
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}
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}
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void UnitState::WriteOutput(const ShaderRegs& config, AttributeBuffer& output) {
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CopyRegistersToOutput(registers.output, config.output_mask, output);
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}
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UnitState::UnitState(GSEmitter* emitter) : emitter_ptr(emitter) {}
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GSEmitter::GSEmitter() {
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@ -94,19 +99,16 @@ GSEmitter::~GSEmitter() {
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delete handlers;
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}
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void GSEmitter::Emit(Math::Vec4<float24> (&vertex)[16]) {
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void GSEmitter::Emit(Math::Vec4<float24> (&output_regs)[16]) {
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ASSERT(vertex_id < 3);
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std::copy(std::begin(vertex), std::end(vertex), buffer[vertex_id].begin());
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// TODO: This should be merged with UnitState::WriteOutput somehow
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CopyRegistersToOutput(output_regs, output_mask, buffer[vertex_id]);
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if (prim_emit) {
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if (winding)
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handlers->winding_setter();
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for (size_t i = 0; i < buffer.size(); ++i) {
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AttributeBuffer output;
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unsigned int output_i = 0;
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for (unsigned int reg : Common::BitSet<u32>(output_mask)) {
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output.attr[output_i++] = buffer[i][reg];
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}
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handlers->vertex_handler(output);
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handlers->vertex_handler(buffer[i]);
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}
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}
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}
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@ -72,7 +72,7 @@ static_assert(sizeof(OutputVertex) == 24 * sizeof(float), "OutputVertex has inva
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* This structure contains state information for primitive emitting in geometry shader.
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*/
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struct GSEmitter {
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std::array<std::array<Math::Vec4<float24>, 16>, 3> buffer;
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std::array<AttributeBuffer, 3> buffer;
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u8 vertex_id;
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bool prim_emit;
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bool winding;
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@ -87,7 +87,7 @@ struct GSEmitter {
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GSEmitter();
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~GSEmitter();
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void Emit(Math::Vec4<float24> (&vertex)[16]);
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void Emit(Math::Vec4<float24> (&output_regs)[16]);
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};
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static_assert(std::is_standard_layout<GSEmitter>::value, "GSEmitter is not standard layout type");
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