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Merge pull request #1022 from aroulin/disas-missing-v6k-instructions
Disassembler: ARMv6K instructions
This commit is contained in:
Lioncash
commit
4821652241
@ -4,6 +4,7 @@
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#include "common/string_util.h"
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#include "core/arm/disassembler/arm_disasm.h"
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#include "core/arm/skyeye_common/armsupp.h"
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static const char *cond_names[] = {
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"eq",
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@ -37,6 +38,7 @@ static const char *opcode_names[] = {
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"blx",
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"bx",
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"cdp",
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"clrex",
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"clz",
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"cmn",
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"cmp",
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@ -46,6 +48,10 @@ static const char *opcode_names[] = {
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"ldr",
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"ldrb",
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"ldrbt",
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"ldrex",
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"ldrexb",
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"ldrexd",
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"ldrexh",
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"ldrh",
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"ldrsb",
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"ldrsh",
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@ -58,11 +64,13 @@ static const char *opcode_names[] = {
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"msr",
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"mul",
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"mvn",
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"nop",
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"orr",
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"pld",
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"rsb",
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"rsc",
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"sbc",
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"sev",
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"smlal",
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"smull",
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"stc",
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@ -70,6 +78,10 @@ static const char *opcode_names[] = {
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"str",
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"strb",
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"strbt",
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"strex",
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"strexb",
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"strexd",
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"strexh",
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"strh",
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"strt",
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"sub",
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@ -80,6 +92,9 @@ static const char *opcode_names[] = {
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"tst",
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"umlal",
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"umull",
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"wfe",
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"wfi",
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"yield",
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"undefined",
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"adc",
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@ -172,6 +187,8 @@ std::string ARM_Disasm::Disassemble(uint32_t addr, uint32_t insn)
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return DisassembleBX(insn);
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case OP_CDP:
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return "cdp";
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case OP_CLREX:
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return "clrex";
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case OP_CLZ:
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return DisassembleCLZ(insn);
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case OP_LDC:
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@ -188,6 +205,15 @@ std::string ARM_Disasm::Disassemble(uint32_t addr, uint32_t insn)
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case OP_STRBT:
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case OP_STRT:
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return DisassembleMem(insn);
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case OP_LDREX:
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case OP_LDREXB:
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case OP_LDREXD:
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case OP_LDREXH:
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case OP_STREX:
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case OP_STREXB:
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case OP_STREXD:
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case OP_STREXH:
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return DisassembleREX(opcode, insn);
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case OP_LDRH:
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case OP_LDRSB:
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case OP_LDRSH:
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@ -204,6 +230,12 @@ std::string ARM_Disasm::Disassemble(uint32_t addr, uint32_t insn)
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return DisassembleMSR(insn);
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case OP_MUL:
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return DisassembleMUL(opcode, insn);
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case OP_NOP:
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case OP_SEV:
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case OP_WFE:
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case OP_WFI:
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case OP_YIELD:
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return DisassembleNoOperands(opcode, insn);
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case OP_PLD:
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return DisassemblePLD(insn);
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case OP_STC:
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@ -646,6 +678,12 @@ std::string ARM_Disasm::DisassembleMSR(uint32_t insn)
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cond_to_str(cond), pd ? "spsr" : "cpsr", flags, rm);
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}
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std::string ARM_Disasm::DisassembleNoOperands(Opcode opcode, uint32_t insn)
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{
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uint32_t cond = BITS(insn, 28, 31);
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return Common::StringFromFormat("%s%s", opcode_names[opcode], cond_to_str(cond));
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}
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std::string ARM_Disasm::DisassemblePLD(uint32_t insn)
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{
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uint8_t is_reg = (insn >> 25) & 0x1;
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@ -669,6 +707,36 @@ std::string ARM_Disasm::DisassemblePLD(uint32_t insn)
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}
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}
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std::string ARM_Disasm::DisassembleREX(Opcode opcode, uint32_t insn) {
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uint32_t rn = BITS(insn, 16, 19);
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uint32_t rd = BITS(insn, 12, 15);
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uint32_t rt = BITS(insn, 0, 3);
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uint32_t cond = BITS(insn, 28, 31);
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switch (opcode) {
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case OP_STREX:
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case OP_STREXB:
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case OP_STREXH:
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return Common::StringFromFormat("%s%s\tr%d, r%d, [r%d]", opcode_names[opcode],
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cond_to_str(cond), rd, rt, rn);
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case OP_STREXD:
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return Common::StringFromFormat("%s%s\tr%d, r%d, r%d, [r%d]", opcode_names[opcode],
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cond_to_str(cond), rd, rt, rt + 1, rn);
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// for LDREX instructions, rd corresponds to Rt from reference manual
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case OP_LDREX:
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case OP_LDREXB:
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case OP_LDREXH:
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return Common::StringFromFormat("%s%s\tr%d, [r%d]", opcode_names[opcode],
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cond_to_str(cond), rd, rn);
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case OP_LDREXD:
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return Common::StringFromFormat("%s%s\tr%d, r%d, [r%d]", opcode_names[opcode],
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cond_to_str(cond), rd, rd + 1, rn);
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default:
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return opcode_names[OP_UNDEFINED];
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}
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}
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std::string ARM_Disasm::DisassembleSWI(uint32_t insn)
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{
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uint8_t cond = (insn >> 28) & 0xf;
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@ -721,12 +789,9 @@ Opcode ARM_Disasm::Decode00(uint32_t insn) {
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}
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uint32_t bits7_4 = (insn >> 4) & 0xf;
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if (bits7_4 == 0x9) {
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if ((insn & 0x0ff00ff0) == 0x01000090) {
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// Swp instruction
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uint8_t bit22 = (insn >> 22) & 0x1;
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if (bit22)
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return OP_SWPB;
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return OP_SWP;
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uint32_t bit24 = BIT(insn, 24);
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if (bit24) {
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return DecodeSyncPrimitive(insn);
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}
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// One of the multiply instructions
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return DecodeMUL(insn);
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@ -739,6 +804,12 @@ Opcode ARM_Disasm::Decode00(uint32_t insn) {
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}
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}
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uint32_t op1 = BITS(insn, 20, 24);
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if (bit25 && (op1 == 0x12 || op1 == 0x16)) {
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// One of the MSR (immediate) and hints instructions
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return DecodeMSRImmAndHints(insn);
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}
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// One of the data processing instructions
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return DecodeALU(insn);
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}
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@ -754,6 +825,10 @@ Opcode ARM_Disasm::Decode01(uint32_t insn) {
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// Pre-load
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return OP_PLD;
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}
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if (insn == 0xf57ff01f) {
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// Clear-Exclusive
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return OP_CLREX;
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}
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if (is_load) {
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if (is_byte) {
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// Load byte
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@ -844,6 +919,35 @@ Opcode ARM_Disasm::Decode11(uint32_t insn) {
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return OP_MCR;
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}
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Opcode ARM_Disasm::DecodeSyncPrimitive(uint32_t insn) {
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uint32_t op = BITS(insn, 20, 23);
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uint32_t bit22 = BIT(insn, 22);
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switch (op) {
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case 0x0:
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if (bit22)
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return OP_SWPB;
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return OP_SWP;
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case 0x8:
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return OP_STREX;
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case 0x9:
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return OP_LDREX;
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case 0xA:
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return OP_STREXD;
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case 0xB:
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return OP_LDREXD;
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case 0xC:
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return OP_STREXB;
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case 0xD:
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return OP_LDREXB;
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case 0xE:
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return OP_STREXH;
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case 0xF:
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return OP_LDREXH;
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default:
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return OP_UNDEFINED;
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}
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}
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Opcode ARM_Disasm::DecodeMUL(uint32_t insn) {
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uint8_t bit24 = (insn >> 24) & 0x1;
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if (bit24 != 0) {
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@ -878,6 +982,31 @@ Opcode ARM_Disasm::DecodeMUL(uint32_t insn) {
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return OP_SMLAL;
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}
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Opcode ARM_Disasm::DecodeMSRImmAndHints(uint32_t insn) {
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uint32_t op = BIT(insn, 22);
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uint32_t op1 = BITS(insn, 16, 19);
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uint32_t op2 = BITS(insn, 0, 7);
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if (op == 0 && op1 == 0) {
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switch (op2) {
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case 0x0:
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return OP_NOP;
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case 0x1:
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return OP_YIELD;
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case 0x2:
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return OP_WFE;
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case 0x3:
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return OP_WFI;
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case 0x4:
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return OP_SEV;
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default:
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return OP_UNDEFINED;
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}
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}
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return OP_MSR;
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}
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Opcode ARM_Disasm::DecodeLDRH(uint32_t insn) {
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uint8_t is_load = (insn >> 20) & 0x1;
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uint8_t bits_65 = (insn >> 5) & 0x3;
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@ -20,6 +20,7 @@ enum Opcode {
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OP_BLX,
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OP_BX,
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OP_CDP,
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OP_CLREX,
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OP_CLZ,
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OP_CMN,
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OP_CMP,
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@ -29,6 +30,10 @@ enum Opcode {
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OP_LDR,
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OP_LDRB,
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OP_LDRBT,
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OP_LDREX,
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OP_LDREXB,
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OP_LDREXD,
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OP_LDREXH,
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OP_LDRH,
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OP_LDRSB,
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OP_LDRSH,
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@ -41,11 +46,13 @@ enum Opcode {
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OP_MSR,
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OP_MUL,
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OP_MVN,
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OP_NOP,
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OP_ORR,
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OP_PLD,
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OP_RSB,
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OP_RSC,
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OP_SBC,
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OP_SEV,
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OP_SMLAL,
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OP_SMULL,
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OP_STC,
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@ -53,6 +60,10 @@ enum Opcode {
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OP_STR,
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OP_STRB,
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OP_STRBT,
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OP_STREX,
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OP_STREXB,
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OP_STREXD,
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OP_STREXH,
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OP_STRH,
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OP_STRT,
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OP_SUB,
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@ -63,6 +74,9 @@ enum Opcode {
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OP_TST,
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OP_UMLAL,
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OP_UMULL,
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OP_WFE,
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OP_WFI,
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OP_YIELD,
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// Define thumb opcodes
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OP_THUMB_UNDEFINED,
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@ -117,7 +131,9 @@ class ARM_Disasm {
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static Opcode Decode01(uint32_t insn);
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static Opcode Decode10(uint32_t insn);
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static Opcode Decode11(uint32_t insn);
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static Opcode DecodeSyncPrimitive(uint32_t insn);
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static Opcode DecodeMUL(uint32_t insn);
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static Opcode DecodeMSRImmAndHints(uint32_t insn);
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static Opcode DecodeLDRH(uint32_t insn);
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static Opcode DecodeALU(uint32_t insn);
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@ -135,7 +151,9 @@ class ARM_Disasm {
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static std::string DisassembleMUL(Opcode opcode, uint32_t insn);
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static std::string DisassembleMRS(uint32_t insn);
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static std::string DisassembleMSR(uint32_t insn);
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static std::string DisassembleNoOperands(Opcode opcode, uint32_t insn);
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static std::string DisassemblePLD(uint32_t insn);
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static std::string DisassembleREX(Opcode opcode, uint32_t insn);
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static std::string DisassembleSWI(uint32_t insn);
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static std::string DisassembleSWP(Opcode opcode, uint32_t insn);
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};
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