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319 lines
11 KiB
C++
319 lines
11 KiB
C++
// Copyright 2018 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <cstring>
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#include <set>
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#include <fmt/format.h>
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#include "common/assert.h"
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#include "common/common_types.h"
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#include "video_core/engines/shader_bytecode.h"
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#include "video_core/engines/shader_header.h"
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#include "video_core/shader/control_flow.h"
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#include "video_core/shader/node_helper.h"
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#include "video_core/shader/shader_ir.h"
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namespace VideoCommon::Shader {
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using Tegra::Shader::Instruction;
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using Tegra::Shader::OpCode;
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namespace {
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/**
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* Returns whether the instruction at the specified offset is a 'sched' instruction.
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* Sched instructions always appear before a sequence of 3 instructions.
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*/
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constexpr bool IsSchedInstruction(u32 offset, u32 main_offset) {
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constexpr u32 SchedPeriod = 4;
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u32 absolute_offset = offset - main_offset;
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return (absolute_offset % SchedPeriod) == 0;
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}
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} // Anonymous namespace
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class ASTDecoder {
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public:
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ASTDecoder(ShaderIR& ir) : ir(ir) {}
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void operator()(ASTProgram& ast) {
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ASTNode current = ast.nodes.GetFirst();
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while (current) {
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Visit(current);
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current = current->GetNext();
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}
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}
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void operator()(ASTIfThen& ast) {
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ASTNode current = ast.nodes.GetFirst();
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while (current) {
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Visit(current);
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current = current->GetNext();
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}
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}
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void operator()(ASTIfElse& ast) {
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ASTNode current = ast.nodes.GetFirst();
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while (current) {
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Visit(current);
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current = current->GetNext();
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}
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}
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void operator()(ASTBlockEncoded& ast) {}
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void operator()(ASTBlockDecoded& ast) {}
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void operator()(ASTVarSet& ast) {}
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void operator()(ASTLabel& ast) {}
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void operator()(ASTGoto& ast) {}
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void operator()(ASTDoWhile& ast) {
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ASTNode current = ast.nodes.GetFirst();
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while (current) {
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Visit(current);
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current = current->GetNext();
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}
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}
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void operator()(ASTReturn& ast) {}
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void operator()(ASTBreak& ast) {}
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void Visit(ASTNode& node) {
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std::visit(*this, *node->GetInnerData());
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if (node->IsBlockEncoded()) {
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auto block = std::get_if<ASTBlockEncoded>(node->GetInnerData());
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NodeBlock bb = ir.DecodeRange(block->start, block->end);
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node->TransformBlockEncoded(std::move(bb));
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}
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}
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private:
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ShaderIR& ir;
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};
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void ShaderIR::Decode() {
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std::memcpy(&header, program_code.data(), sizeof(Tegra::Shader::Header));
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decompiled = false;
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auto info = ScanFlow(program_code, main_offset, settings, locker);
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auto& shader_info = *info;
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coverage_begin = shader_info.start;
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coverage_end = shader_info.end;
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switch (shader_info.settings.depth) {
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case CompileDepth::FlowStack: {
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for (const auto& block : shader_info.blocks) {
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basic_blocks.insert({block.start, DecodeRange(block.start, block.end + 1)});
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}
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break;
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}
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case CompileDepth::NoFlowStack: {
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disable_flow_stack = true;
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const auto insert_block = [this](NodeBlock& nodes, u32 label) {
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if (label == static_cast<u32>(exit_branch)) {
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return;
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}
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basic_blocks.insert({label, nodes});
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};
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const auto& blocks = shader_info.blocks;
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NodeBlock current_block;
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u32 current_label = static_cast<u32>(exit_branch);
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for (auto& block : blocks) {
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if (shader_info.labels.count(block.start) != 0) {
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insert_block(current_block, current_label);
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current_block.clear();
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current_label = block.start;
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}
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if (!block.ignore_branch) {
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DecodeRangeInner(current_block, block.start, block.end);
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InsertControlFlow(current_block, block);
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} else {
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DecodeRangeInner(current_block, block.start, block.end + 1);
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}
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}
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insert_block(current_block, current_label);
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break;
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}
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case CompileDepth::DecompileBackwards:
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case CompileDepth::FullDecompile: {
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program_manager = std::move(shader_info.manager);
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disable_flow_stack = true;
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decompiled = true;
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ASTDecoder decoder{*this};
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ASTNode program = GetASTProgram();
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decoder.Visit(program);
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break;
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}
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default:
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LOG_CRITICAL(HW_GPU, "Unknown decompilation mode!");
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[[fallthrough]];
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case CompileDepth::BruteForce: {
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coverage_begin = main_offset;
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const std::size_t shader_end = program_code.size();
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coverage_end = shader_end;
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for (u32 label = main_offset; label < shader_end; label++) {
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basic_blocks.insert({label, DecodeRange(label, label + 1)});
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}
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break;
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}
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}
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if (settings.depth != shader_info.settings.depth) {
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LOG_WARNING(
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HW_GPU, "Decompiling to this setting \"{}\" failed, downgrading to this setting \"{}\"",
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CompileDepthAsString(settings.depth), CompileDepthAsString(shader_info.settings.depth));
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}
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}
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NodeBlock ShaderIR::DecodeRange(u32 begin, u32 end) {
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NodeBlock basic_block;
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DecodeRangeInner(basic_block, begin, end);
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return basic_block;
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}
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void ShaderIR::DecodeRangeInner(NodeBlock& bb, u32 begin, u32 end) {
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for (u32 pc = begin; pc < (begin > end ? MAX_PROGRAM_LENGTH : end);) {
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pc = DecodeInstr(bb, pc);
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}
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}
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void ShaderIR::InsertControlFlow(NodeBlock& bb, const ShaderBlock& block) {
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const auto apply_conditions = [&](const Condition& cond, Node n) -> Node {
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Node result = n;
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if (cond.cc != ConditionCode::T) {
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result = Conditional(GetConditionCode(cond.cc), {result});
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}
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if (cond.predicate != Pred::UnusedIndex) {
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u32 pred = static_cast<u32>(cond.predicate);
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const bool is_neg = pred > 7;
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if (is_neg) {
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pred -= 8;
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}
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result = Conditional(GetPredicate(pred, is_neg), {result});
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}
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return result;
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};
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if (std::holds_alternative<SingleBranch>(*block.branch)) {
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auto branch = std::get_if<SingleBranch>(block.branch.get());
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if (branch->address < 0) {
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if (branch->kill) {
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Node n = Operation(OperationCode::Discard);
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n = apply_conditions(branch->condition, n);
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bb.push_back(n);
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global_code.push_back(n);
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return;
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}
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Node n = Operation(OperationCode::Exit);
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n = apply_conditions(branch->condition, n);
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bb.push_back(n);
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global_code.push_back(n);
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return;
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}
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Node n = Operation(OperationCode::Branch, Immediate(branch->address));
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n = apply_conditions(branch->condition, n);
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bb.push_back(n);
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global_code.push_back(n);
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return;
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}
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auto multi_branch = std::get_if<MultiBranch>(block.branch.get());
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Node op_a = GetRegister(multi_branch->gpr);
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for (auto& branch_case : multi_branch->branches) {
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Node n = Operation(OperationCode::Branch, Immediate(branch_case.address));
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Node op_b = Immediate(branch_case.cmp_value);
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Node condition =
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GetPredicateComparisonInteger(Tegra::Shader::PredCondition::Equal, false, op_a, op_b);
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auto result = Conditional(condition, {n});
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bb.push_back(result);
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global_code.push_back(result);
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}
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}
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u32 ShaderIR::DecodeInstr(NodeBlock& bb, u32 pc) {
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// Ignore sched instructions when generating code.
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if (IsSchedInstruction(pc, main_offset)) {
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return pc + 1;
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}
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const Instruction instr = {program_code[pc]};
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const auto opcode = OpCode::Decode(instr);
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const u32 nv_address = ConvertAddressToNvidiaSpace(pc);
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// Decoding failure
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if (!opcode) {
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UNIMPLEMENTED_MSG("Unhandled instruction: {0:x}", instr.value);
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bb.push_back(Comment(fmt::format("{:05x} Unimplemented Shader instruction (0x{:016x})",
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nv_address, instr.value)));
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return pc + 1;
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}
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bb.push_back(Comment(
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fmt::format("{:05x} {} (0x{:016x})", nv_address, opcode->get().GetName(), instr.value)));
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using Tegra::Shader::Pred;
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UNIMPLEMENTED_IF_MSG(instr.pred.full_pred == Pred::NeverExecute,
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"NeverExecute predicate not implemented");
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static const std::map<OpCode::Type, u32 (ShaderIR::*)(NodeBlock&, u32)> decoders = {
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{OpCode::Type::Arithmetic, &ShaderIR::DecodeArithmetic},
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{OpCode::Type::ArithmeticImmediate, &ShaderIR::DecodeArithmeticImmediate},
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{OpCode::Type::Bfe, &ShaderIR::DecodeBfe},
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{OpCode::Type::Bfi, &ShaderIR::DecodeBfi},
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{OpCode::Type::Shift, &ShaderIR::DecodeShift},
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{OpCode::Type::ArithmeticInteger, &ShaderIR::DecodeArithmeticInteger},
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{OpCode::Type::ArithmeticIntegerImmediate, &ShaderIR::DecodeArithmeticIntegerImmediate},
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{OpCode::Type::ArithmeticHalf, &ShaderIR::DecodeArithmeticHalf},
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{OpCode::Type::ArithmeticHalfImmediate, &ShaderIR::DecodeArithmeticHalfImmediate},
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{OpCode::Type::Ffma, &ShaderIR::DecodeFfma},
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{OpCode::Type::Hfma2, &ShaderIR::DecodeHfma2},
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{OpCode::Type::Conversion, &ShaderIR::DecodeConversion},
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{OpCode::Type::Warp, &ShaderIR::DecodeWarp},
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{OpCode::Type::Memory, &ShaderIR::DecodeMemory},
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{OpCode::Type::Texture, &ShaderIR::DecodeTexture},
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{OpCode::Type::Image, &ShaderIR::DecodeImage},
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{OpCode::Type::FloatSetPredicate, &ShaderIR::DecodeFloatSetPredicate},
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{OpCode::Type::IntegerSetPredicate, &ShaderIR::DecodeIntegerSetPredicate},
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{OpCode::Type::HalfSetPredicate, &ShaderIR::DecodeHalfSetPredicate},
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{OpCode::Type::PredicateSetRegister, &ShaderIR::DecodePredicateSetRegister},
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{OpCode::Type::PredicateSetPredicate, &ShaderIR::DecodePredicateSetPredicate},
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{OpCode::Type::RegisterSetPredicate, &ShaderIR::DecodeRegisterSetPredicate},
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{OpCode::Type::FloatSet, &ShaderIR::DecodeFloatSet},
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{OpCode::Type::IntegerSet, &ShaderIR::DecodeIntegerSet},
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{OpCode::Type::HalfSet, &ShaderIR::DecodeHalfSet},
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{OpCode::Type::Video, &ShaderIR::DecodeVideo},
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{OpCode::Type::Xmad, &ShaderIR::DecodeXmad},
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};
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std::vector<Node> tmp_block;
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if (const auto decoder = decoders.find(opcode->get().GetType()); decoder != decoders.end()) {
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pc = (this->*decoder->second)(tmp_block, pc);
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} else {
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pc = DecodeOther(tmp_block, pc);
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}
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// Some instructions (like SSY) don't have a predicate field, they are always unconditionally
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// executed.
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const bool can_be_predicated = OpCode::IsPredicatedInstruction(opcode->get().GetId());
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const auto pred_index = static_cast<u32>(instr.pred.pred_index);
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if (can_be_predicated && pred_index != static_cast<u32>(Pred::UnusedIndex)) {
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const Node conditional =
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Conditional(GetPredicate(pred_index, instr.negate_pred != 0), std::move(tmp_block));
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global_code.push_back(conditional);
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bb.push_back(conditional);
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} else {
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for (auto& node : tmp_block) {
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global_code.push_back(node);
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bb.push_back(node);
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}
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}
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return pc + 1;
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}
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} // namespace VideoCommon::Shader
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