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4c5f5c9bf3
fmt now automatically prints the numeric value of an enum class member by default, so we don't need to use casts any more. Reduces the line noise a bit.
288 lines
9.4 KiB
C++
288 lines
9.4 KiB
C++
// Copyright 2020 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "common/assert.h"
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#include "common/logging/log.h"
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#include "common/microprofile.h"
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#include "video_core/engines/maxwell_3d.h"
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#include "video_core/macro/macro_interpreter.h"
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MICROPROFILE_DEFINE(MacroInterp, "GPU", "Execute macro interpreter", MP_RGB(128, 128, 192));
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namespace Tegra {
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MacroInterpreter::MacroInterpreter(Engines::Maxwell3D& maxwell3d_)
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: MacroEngine{maxwell3d_}, maxwell3d{maxwell3d_} {}
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std::unique_ptr<CachedMacro> MacroInterpreter::Compile(const std::vector<u32>& code) {
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return std::make_unique<MacroInterpreterImpl>(maxwell3d, code);
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}
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MacroInterpreterImpl::MacroInterpreterImpl(Engines::Maxwell3D& maxwell3d_,
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const std::vector<u32>& code_)
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: maxwell3d{maxwell3d_}, code{code_} {}
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void MacroInterpreterImpl::Execute(const std::vector<u32>& params, u32 method) {
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MICROPROFILE_SCOPE(MacroInterp);
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Reset();
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registers[1] = params[0];
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num_parameters = params.size();
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if (num_parameters > parameters_capacity) {
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parameters_capacity = num_parameters;
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parameters = std::make_unique<u32[]>(num_parameters);
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}
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std::memcpy(parameters.get(), params.data(), num_parameters * sizeof(u32));
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// Execute the code until we hit an exit condition.
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bool keep_executing = true;
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while (keep_executing) {
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keep_executing = Step(false);
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}
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// Assert the the macro used all the input parameters
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ASSERT(next_parameter_index == num_parameters);
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}
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void MacroInterpreterImpl::Reset() {
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registers = {};
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pc = 0;
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delayed_pc = {};
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method_address.raw = 0;
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num_parameters = 0;
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// The next parameter index starts at 1, because $r1 already has the value of the first
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// parameter.
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next_parameter_index = 1;
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carry_flag = false;
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}
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bool MacroInterpreterImpl::Step(bool is_delay_slot) {
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u32 base_address = pc;
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Macro::Opcode opcode = GetOpcode();
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pc += 4;
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// Update the program counter if we were delayed
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if (delayed_pc) {
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ASSERT(is_delay_slot);
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pc = *delayed_pc;
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delayed_pc = {};
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}
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switch (opcode.operation) {
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case Macro::Operation::ALU: {
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u32 result = GetALUResult(opcode.alu_operation, GetRegister(opcode.src_a),
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GetRegister(opcode.src_b));
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ProcessResult(opcode.result_operation, opcode.dst, result);
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break;
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}
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case Macro::Operation::AddImmediate: {
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ProcessResult(opcode.result_operation, opcode.dst,
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GetRegister(opcode.src_a) + opcode.immediate);
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break;
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}
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case Macro::Operation::ExtractInsert: {
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u32 dst = GetRegister(opcode.src_a);
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u32 src = GetRegister(opcode.src_b);
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src = (src >> opcode.bf_src_bit) & opcode.GetBitfieldMask();
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dst &= ~(opcode.GetBitfieldMask() << opcode.bf_dst_bit);
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dst |= src << opcode.bf_dst_bit;
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ProcessResult(opcode.result_operation, opcode.dst, dst);
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break;
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}
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case Macro::Operation::ExtractShiftLeftImmediate: {
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u32 dst = GetRegister(opcode.src_a);
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u32 src = GetRegister(opcode.src_b);
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u32 result = ((src >> dst) & opcode.GetBitfieldMask()) << opcode.bf_dst_bit;
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ProcessResult(opcode.result_operation, opcode.dst, result);
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break;
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}
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case Macro::Operation::ExtractShiftLeftRegister: {
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u32 dst = GetRegister(opcode.src_a);
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u32 src = GetRegister(opcode.src_b);
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u32 result = ((src >> opcode.bf_src_bit) & opcode.GetBitfieldMask()) << dst;
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ProcessResult(opcode.result_operation, opcode.dst, result);
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break;
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}
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case Macro::Operation::Read: {
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u32 result = Read(GetRegister(opcode.src_a) + opcode.immediate);
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ProcessResult(opcode.result_operation, opcode.dst, result);
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break;
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}
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case Macro::Operation::Branch: {
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ASSERT_MSG(!is_delay_slot, "Executing a branch in a delay slot is not valid");
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u32 value = GetRegister(opcode.src_a);
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bool taken = EvaluateBranchCondition(opcode.branch_condition, value);
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if (taken) {
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// Ignore the delay slot if the branch has the annul bit.
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if (opcode.branch_annul) {
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pc = base_address + opcode.GetBranchTarget();
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return true;
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}
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delayed_pc = base_address + opcode.GetBranchTarget();
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// Execute one more instruction due to the delay slot.
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return Step(true);
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}
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break;
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}
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default:
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UNIMPLEMENTED_MSG("Unimplemented macro operation {}", opcode.operation.Value());
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}
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// An instruction with the Exit flag will not actually
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// cause an exit if it's executed inside a delay slot.
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if (opcode.is_exit && !is_delay_slot) {
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// Exit has a delay slot, execute the next instruction
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Step(true);
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return false;
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}
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return true;
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}
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u32 MacroInterpreterImpl::GetALUResult(Macro::ALUOperation operation, u32 src_a, u32 src_b) {
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switch (operation) {
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case Macro::ALUOperation::Add: {
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const u64 result{static_cast<u64>(src_a) + src_b};
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carry_flag = result > 0xffffffff;
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return static_cast<u32>(result);
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}
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case Macro::ALUOperation::AddWithCarry: {
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const u64 result{static_cast<u64>(src_a) + src_b + (carry_flag ? 1ULL : 0ULL)};
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carry_flag = result > 0xffffffff;
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return static_cast<u32>(result);
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}
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case Macro::ALUOperation::Subtract: {
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const u64 result{static_cast<u64>(src_a) - src_b};
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carry_flag = result < 0x100000000;
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return static_cast<u32>(result);
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}
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case Macro::ALUOperation::SubtractWithBorrow: {
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const u64 result{static_cast<u64>(src_a) - src_b - (carry_flag ? 0ULL : 1ULL)};
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carry_flag = result < 0x100000000;
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return static_cast<u32>(result);
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}
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case Macro::ALUOperation::Xor:
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return src_a ^ src_b;
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case Macro::ALUOperation::Or:
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return src_a | src_b;
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case Macro::ALUOperation::And:
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return src_a & src_b;
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case Macro::ALUOperation::AndNot:
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return src_a & ~src_b;
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case Macro::ALUOperation::Nand:
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return ~(src_a & src_b);
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default:
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UNIMPLEMENTED_MSG("Unimplemented ALU operation {}", operation);
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return 0;
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}
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}
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void MacroInterpreterImpl::ProcessResult(Macro::ResultOperation operation, u32 reg, u32 result) {
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switch (operation) {
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case Macro::ResultOperation::IgnoreAndFetch:
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// Fetch parameter and ignore result.
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SetRegister(reg, FetchParameter());
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break;
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case Macro::ResultOperation::Move:
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// Move result.
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SetRegister(reg, result);
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break;
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case Macro::ResultOperation::MoveAndSetMethod:
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// Move result and use as Method Address.
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SetRegister(reg, result);
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SetMethodAddress(result);
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break;
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case Macro::ResultOperation::FetchAndSend:
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// Fetch parameter and send result.
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SetRegister(reg, FetchParameter());
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Send(result);
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break;
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case Macro::ResultOperation::MoveAndSend:
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// Move and send result.
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SetRegister(reg, result);
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Send(result);
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break;
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case Macro::ResultOperation::FetchAndSetMethod:
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// Fetch parameter and use result as Method Address.
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SetRegister(reg, FetchParameter());
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SetMethodAddress(result);
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break;
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case Macro::ResultOperation::MoveAndSetMethodFetchAndSend:
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// Move result and use as Method Address, then fetch and send parameter.
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SetRegister(reg, result);
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SetMethodAddress(result);
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Send(FetchParameter());
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break;
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case Macro::ResultOperation::MoveAndSetMethodSend:
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// Move result and use as Method Address, then send bits 12:17 of result.
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SetRegister(reg, result);
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SetMethodAddress(result);
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Send((result >> 12) & 0b111111);
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break;
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default:
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UNIMPLEMENTED_MSG("Unimplemented result operation {}", operation);
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}
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}
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bool MacroInterpreterImpl::EvaluateBranchCondition(Macro::BranchCondition cond, u32 value) const {
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switch (cond) {
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case Macro::BranchCondition::Zero:
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return value == 0;
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case Macro::BranchCondition::NotZero:
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return value != 0;
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}
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UNREACHABLE();
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return true;
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}
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Macro::Opcode MacroInterpreterImpl::GetOpcode() const {
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ASSERT((pc % sizeof(u32)) == 0);
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ASSERT(pc < code.size() * sizeof(u32));
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return {code[pc / sizeof(u32)]};
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}
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u32 MacroInterpreterImpl::GetRegister(u32 register_id) const {
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return registers.at(register_id);
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}
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void MacroInterpreterImpl::SetRegister(u32 register_id, u32 value) {
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// Register 0 is hardwired as the zero register.
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// Ensure no writes to it actually occur.
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if (register_id == 0) {
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return;
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}
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registers.at(register_id) = value;
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}
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void MacroInterpreterImpl::SetMethodAddress(u32 address) {
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method_address.raw = address;
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}
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void MacroInterpreterImpl::Send(u32 value) {
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maxwell3d.CallMethodFromMME(method_address.address, value);
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// Increment the method address by the method increment.
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method_address.address.Assign(method_address.address.Value() +
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method_address.increment.Value());
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}
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u32 MacroInterpreterImpl::Read(u32 method) const {
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return maxwell3d.GetRegisterValue(method);
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}
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u32 MacroInterpreterImpl::FetchParameter() {
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ASSERT(next_parameter_index < num_parameters);
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return parameters[next_parameter_index++];
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}
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} // namespace Tegra
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