mirror of https://github.com/yuzu-emu/yuzu.git
473 lines
17 KiB
C++
473 lines
17 KiB
C++
// SPDX-FileCopyrightText: Copyright 2018 yuzu Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include "common/settings.h"
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#include "core/arm/dynarmic/arm_dynarmic.h"
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#include "core/arm/dynarmic/arm_dynarmic_64.h"
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#include "core/arm/dynarmic/dynarmic_exclusive_monitor.h"
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#include "core/core_timing.h"
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#include "core/hle/kernel/k_process.h"
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namespace Core {
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using Vector = Dynarmic::A64::Vector;
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using namespace Common::Literals;
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class DynarmicCallbacks64 : public Dynarmic::A64::UserCallbacks {
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public:
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explicit DynarmicCallbacks64(ArmDynarmic64& parent, const Kernel::KProcess* process)
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: m_parent{parent}, m_memory(process->GetMemory()),
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m_process(process), m_debugger_enabled{parent.m_system.DebuggerEnabled()},
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m_check_memory_access{m_debugger_enabled ||
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!Settings::values.cpuopt_ignore_memory_aborts.GetValue()} {}
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u8 MemoryRead8(u64 vaddr) override {
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CheckMemoryAccess(vaddr, 1, Kernel::DebugWatchpointType::Read);
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return m_memory.Read8(vaddr);
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}
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u16 MemoryRead16(u64 vaddr) override {
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CheckMemoryAccess(vaddr, 2, Kernel::DebugWatchpointType::Read);
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return m_memory.Read16(vaddr);
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}
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u32 MemoryRead32(u64 vaddr) override {
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CheckMemoryAccess(vaddr, 4, Kernel::DebugWatchpointType::Read);
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return m_memory.Read32(vaddr);
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}
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u64 MemoryRead64(u64 vaddr) override {
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CheckMemoryAccess(vaddr, 8, Kernel::DebugWatchpointType::Read);
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return m_memory.Read64(vaddr);
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}
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Vector MemoryRead128(u64 vaddr) override {
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CheckMemoryAccess(vaddr, 16, Kernel::DebugWatchpointType::Read);
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return {m_memory.Read64(vaddr), m_memory.Read64(vaddr + 8)};
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}
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std::optional<u32> MemoryReadCode(u64 vaddr) override {
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if (!m_memory.IsValidVirtualAddressRange(vaddr, sizeof(u32))) {
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return std::nullopt;
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}
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return m_memory.Read32(vaddr);
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}
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void MemoryWrite8(u64 vaddr, u8 value) override {
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if (CheckMemoryAccess(vaddr, 1, Kernel::DebugWatchpointType::Write)) {
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m_memory.Write8(vaddr, value);
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}
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}
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void MemoryWrite16(u64 vaddr, u16 value) override {
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if (CheckMemoryAccess(vaddr, 2, Kernel::DebugWatchpointType::Write)) {
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m_memory.Write16(vaddr, value);
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}
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}
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void MemoryWrite32(u64 vaddr, u32 value) override {
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if (CheckMemoryAccess(vaddr, 4, Kernel::DebugWatchpointType::Write)) {
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m_memory.Write32(vaddr, value);
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}
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}
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void MemoryWrite64(u64 vaddr, u64 value) override {
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if (CheckMemoryAccess(vaddr, 8, Kernel::DebugWatchpointType::Write)) {
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m_memory.Write64(vaddr, value);
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}
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}
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void MemoryWrite128(u64 vaddr, Vector value) override {
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if (CheckMemoryAccess(vaddr, 16, Kernel::DebugWatchpointType::Write)) {
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m_memory.Write64(vaddr, value[0]);
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m_memory.Write64(vaddr + 8, value[1]);
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}
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}
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bool MemoryWriteExclusive8(u64 vaddr, std::uint8_t value, std::uint8_t expected) override {
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return CheckMemoryAccess(vaddr, 1, Kernel::DebugWatchpointType::Write) &&
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m_memory.WriteExclusive8(vaddr, value, expected);
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}
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bool MemoryWriteExclusive16(u64 vaddr, std::uint16_t value, std::uint16_t expected) override {
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return CheckMemoryAccess(vaddr, 2, Kernel::DebugWatchpointType::Write) &&
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m_memory.WriteExclusive16(vaddr, value, expected);
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}
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bool MemoryWriteExclusive32(u64 vaddr, std::uint32_t value, std::uint32_t expected) override {
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return CheckMemoryAccess(vaddr, 4, Kernel::DebugWatchpointType::Write) &&
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m_memory.WriteExclusive32(vaddr, value, expected);
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}
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bool MemoryWriteExclusive64(u64 vaddr, std::uint64_t value, std::uint64_t expected) override {
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return CheckMemoryAccess(vaddr, 8, Kernel::DebugWatchpointType::Write) &&
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m_memory.WriteExclusive64(vaddr, value, expected);
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}
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bool MemoryWriteExclusive128(u64 vaddr, Vector value, Vector expected) override {
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return CheckMemoryAccess(vaddr, 16, Kernel::DebugWatchpointType::Write) &&
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m_memory.WriteExclusive128(vaddr, value, expected);
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}
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void InterpreterFallback(u64 pc, std::size_t num_instructions) override {
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m_parent.LogBacktrace(m_process);
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LOG_ERROR(Core_ARM,
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"Unimplemented instruction @ 0x{:X} for {} instructions (instr = {:08X})", pc,
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num_instructions, m_memory.Read32(pc));
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ReturnException(pc, PrefetchAbort);
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}
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void InstructionCacheOperationRaised(Dynarmic::A64::InstructionCacheOperation op,
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u64 value) override {
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switch (op) {
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case Dynarmic::A64::InstructionCacheOperation::InvalidateByVAToPoU: {
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static constexpr u64 ICACHE_LINE_SIZE = 64;
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const u64 cache_line_start = value & ~(ICACHE_LINE_SIZE - 1);
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m_parent.InvalidateCacheRange(cache_line_start, ICACHE_LINE_SIZE);
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break;
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}
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case Dynarmic::A64::InstructionCacheOperation::InvalidateAllToPoU:
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m_parent.ClearInstructionCache();
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break;
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case Dynarmic::A64::InstructionCacheOperation::InvalidateAllToPoUInnerSharable:
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default:
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LOG_DEBUG(Core_ARM, "Unprocesseed instruction cache operation: {}", op);
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break;
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}
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m_parent.m_jit->HaltExecution(Dynarmic::HaltReason::CacheInvalidation);
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}
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void ExceptionRaised(u64 pc, Dynarmic::A64::Exception exception) override {
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switch (exception) {
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case Dynarmic::A64::Exception::WaitForInterrupt:
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case Dynarmic::A64::Exception::WaitForEvent:
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case Dynarmic::A64::Exception::SendEvent:
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case Dynarmic::A64::Exception::SendEventLocal:
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case Dynarmic::A64::Exception::Yield:
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return;
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case Dynarmic::A64::Exception::NoExecuteFault:
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LOG_CRITICAL(Core_ARM, "Cannot execute instruction at unmapped address {:#016x}", pc);
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ReturnException(pc, PrefetchAbort);
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return;
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default:
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if (m_debugger_enabled) {
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ReturnException(pc, InstructionBreakpoint);
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return;
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}
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m_parent.LogBacktrace(m_process);
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LOG_CRITICAL(Core_ARM, "ExceptionRaised(exception = {}, pc = {:08X}, code = {:08X})",
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static_cast<std::size_t>(exception), pc, m_memory.Read32(pc));
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}
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}
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void CallSVC(u32 svc) override {
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m_parent.m_svc = svc;
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m_parent.m_jit->HaltExecution(SupervisorCall);
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}
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void AddTicks(u64 ticks) override {
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ASSERT_MSG(!m_parent.m_uses_wall_clock, "Dynarmic ticking disabled");
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// Divide the number of ticks by the amount of CPU cores. TODO(Subv): This yields only a
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// rough approximation of the amount of executed ticks in the system, it may be thrown off
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// if not all cores are doing a similar amount of work. Instead of doing this, we should
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// device a way so that timing is consistent across all cores without increasing the ticks 4
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// times.
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u64 amortized_ticks = ticks / Core::Hardware::NUM_CPU_CORES;
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// Always execute at least one tick.
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amortized_ticks = std::max<u64>(amortized_ticks, 1);
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m_parent.m_system.CoreTiming().AddTicks(amortized_ticks);
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}
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u64 GetTicksRemaining() override {
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ASSERT_MSG(!m_parent.m_uses_wall_clock, "Dynarmic ticking disabled");
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return std::max<s64>(m_parent.m_system.CoreTiming().GetDowncount(), 0);
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}
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u64 GetCNTPCT() override {
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return m_parent.m_system.CoreTiming().GetClockTicks();
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}
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bool CheckMemoryAccess(u64 addr, u64 size, Kernel::DebugWatchpointType type) {
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if (!m_check_memory_access) {
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return true;
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}
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if (!m_memory.IsValidVirtualAddressRange(addr, size)) {
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LOG_CRITICAL(Core_ARM, "Stopping execution due to unmapped memory access at {:#x}",
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addr);
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m_parent.m_jit->HaltExecution(PrefetchAbort);
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return false;
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}
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if (!m_debugger_enabled) {
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return true;
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}
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const auto match{m_parent.MatchingWatchpoint(addr, size, type)};
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if (match) {
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m_parent.m_halted_watchpoint = match;
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m_parent.m_jit->HaltExecution(DataAbort);
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return false;
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}
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return true;
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}
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void ReturnException(u64 pc, Dynarmic::HaltReason hr) {
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m_parent.GetContext(m_parent.m_breakpoint_context);
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m_parent.m_breakpoint_context.pc = pc;
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m_parent.m_jit->HaltExecution(hr);
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}
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ArmDynarmic64& m_parent;
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Core::Memory::Memory& m_memory;
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u64 m_tpidrro_el0{};
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u64 m_tpidr_el0{};
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const Kernel::KProcess* m_process{};
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const bool m_debugger_enabled{};
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const bool m_check_memory_access{};
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static constexpr u64 MinimumRunCycles = 10000U;
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};
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std::shared_ptr<Dynarmic::A64::Jit> ArmDynarmic64::MakeJit(Common::PageTable* page_table,
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std::size_t address_space_bits) const {
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Dynarmic::A64::UserConfig config;
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// Callbacks
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config.callbacks = m_cb.get();
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// Memory
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if (page_table) {
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config.page_table = reinterpret_cast<void**>(page_table->pointers.data());
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config.page_table_address_space_bits = address_space_bits;
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config.page_table_pointer_mask_bits = Common::PageTable::ATTRIBUTE_BITS;
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config.silently_mirror_page_table = false;
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config.absolute_offset_page_table = true;
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config.detect_misaligned_access_via_page_table = 16 | 32 | 64 | 128;
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config.only_detect_misalignment_via_page_table_on_page_boundary = true;
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config.fastmem_pointer = page_table->fastmem_arena;
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config.fastmem_address_space_bits = address_space_bits;
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config.silently_mirror_fastmem = false;
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config.fastmem_exclusive_access = config.fastmem_pointer != nullptr;
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config.recompile_on_exclusive_fastmem_failure = true;
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}
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// Multi-process state
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config.processor_id = m_core_index;
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config.global_monitor = &m_exclusive_monitor.monitor;
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// System registers
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config.tpidrro_el0 = &m_cb->m_tpidrro_el0;
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config.tpidr_el0 = &m_cb->m_tpidr_el0;
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config.dczid_el0 = 4;
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config.ctr_el0 = 0x8444c004;
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config.cntfrq_el0 = Hardware::CNTFREQ;
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// Unpredictable instructions
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config.define_unpredictable_behaviour = true;
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// Timing
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config.wall_clock_cntpct = m_uses_wall_clock;
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config.enable_cycle_counting = !m_uses_wall_clock;
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// Code cache size
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#ifdef ARCHITECTURE_arm64
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config.code_cache_size = 128_MiB;
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#else
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config.code_cache_size = 512_MiB;
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#endif
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// Allow memory fault handling to work
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if (m_system.DebuggerEnabled()) {
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config.check_halt_on_memory_access = true;
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}
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// null_jit
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if (!page_table) {
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// Don't waste too much memory on null_jit
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config.code_cache_size = 8_MiB;
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}
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// Safe optimizations
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if (Settings::values.cpu_debug_mode) {
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if (!Settings::values.cpuopt_page_tables) {
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config.page_table = nullptr;
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}
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if (!Settings::values.cpuopt_block_linking) {
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config.optimizations &= ~Dynarmic::OptimizationFlag::BlockLinking;
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}
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if (!Settings::values.cpuopt_return_stack_buffer) {
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config.optimizations &= ~Dynarmic::OptimizationFlag::ReturnStackBuffer;
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}
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if (!Settings::values.cpuopt_fast_dispatcher) {
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config.optimizations &= ~Dynarmic::OptimizationFlag::FastDispatch;
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}
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if (!Settings::values.cpuopt_context_elimination) {
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config.optimizations &= ~Dynarmic::OptimizationFlag::GetSetElimination;
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}
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if (!Settings::values.cpuopt_const_prop) {
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config.optimizations &= ~Dynarmic::OptimizationFlag::ConstProp;
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}
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if (!Settings::values.cpuopt_misc_ir) {
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config.optimizations &= ~Dynarmic::OptimizationFlag::MiscIROpt;
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}
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if (!Settings::values.cpuopt_reduce_misalign_checks) {
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config.only_detect_misalignment_via_page_table_on_page_boundary = false;
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}
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if (!Settings::values.cpuopt_fastmem) {
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config.fastmem_pointer = nullptr;
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config.fastmem_exclusive_access = false;
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}
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if (!Settings::values.cpuopt_fastmem_exclusives) {
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config.fastmem_exclusive_access = false;
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}
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if (!Settings::values.cpuopt_recompile_exclusives) {
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config.recompile_on_exclusive_fastmem_failure = false;
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}
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if (!Settings::values.cpuopt_ignore_memory_aborts) {
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config.check_halt_on_memory_access = true;
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}
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} else {
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// Unsafe optimizations
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if (Settings::values.cpu_accuracy.GetValue() == Settings::CpuAccuracy::Unsafe) {
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config.unsafe_optimizations = true;
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if (Settings::values.cpuopt_unsafe_unfuse_fma) {
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config.optimizations |= Dynarmic::OptimizationFlag::Unsafe_UnfuseFMA;
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}
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if (Settings::values.cpuopt_unsafe_reduce_fp_error) {
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config.optimizations |= Dynarmic::OptimizationFlag::Unsafe_ReducedErrorFP;
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}
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if (Settings::values.cpuopt_unsafe_inaccurate_nan) {
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config.optimizations |= Dynarmic::OptimizationFlag::Unsafe_InaccurateNaN;
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}
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if (Settings::values.cpuopt_unsafe_fastmem_check) {
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config.fastmem_address_space_bits = 64;
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}
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if (Settings::values.cpuopt_unsafe_ignore_global_monitor) {
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config.optimizations |= Dynarmic::OptimizationFlag::Unsafe_IgnoreGlobalMonitor;
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}
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}
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// Curated optimizations
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if (Settings::values.cpu_accuracy.GetValue() == Settings::CpuAccuracy::Auto) {
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config.unsafe_optimizations = true;
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config.optimizations |= Dynarmic::OptimizationFlag::Unsafe_UnfuseFMA;
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config.fastmem_address_space_bits = 64;
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config.optimizations |= Dynarmic::OptimizationFlag::Unsafe_IgnoreGlobalMonitor;
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}
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// Paranoia mode for debugging optimizations
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if (Settings::values.cpu_accuracy.GetValue() == Settings::CpuAccuracy::Paranoid) {
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config.unsafe_optimizations = false;
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config.optimizations = Dynarmic::no_optimizations;
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}
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}
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return std::make_shared<Dynarmic::A64::Jit>(config);
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}
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HaltReason ArmDynarmic64::RunThread(Kernel::KThread* thread) {
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m_jit->ClearExclusiveState();
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return TranslateHaltReason(m_jit->Run());
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}
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HaltReason ArmDynarmic64::StepThread(Kernel::KThread* thread) {
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m_jit->ClearExclusiveState();
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return TranslateHaltReason(m_jit->Step());
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}
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u32 ArmDynarmic64::GetSvcNumber() const {
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return m_svc;
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}
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void ArmDynarmic64::GetSvcArguments(std::span<uint64_t, 8> args) const {
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Dynarmic::A64::Jit& j = *m_jit;
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for (size_t i = 0; i < 8; i++) {
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args[i] = j.GetRegister(i);
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}
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}
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void ArmDynarmic64::SetSvcArguments(std::span<const uint64_t, 8> args) {
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Dynarmic::A64::Jit& j = *m_jit;
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for (size_t i = 0; i < 8; i++) {
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j.SetRegister(i, args[i]);
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}
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}
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const Kernel::DebugWatchpoint* ArmDynarmic64::HaltedWatchpoint() const {
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return m_halted_watchpoint;
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}
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void ArmDynarmic64::RewindBreakpointInstruction() {
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this->SetContext(m_breakpoint_context);
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}
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ArmDynarmic64::ArmDynarmic64(System& system, bool uses_wall_clock, const Kernel::KProcess* process,
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DynarmicExclusiveMonitor& exclusive_monitor, std::size_t core_index)
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: ArmInterface{uses_wall_clock}, m_system{system}, m_exclusive_monitor{exclusive_monitor},
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m_cb(std::make_unique<DynarmicCallbacks64>(*this, process)), m_core_index{core_index} {
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auto& page_table = process->GetPageTable().GetBasePageTable();
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auto& page_table_impl = page_table.GetImpl();
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m_jit = MakeJit(&page_table_impl, page_table.GetAddressSpaceWidth());
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}
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ArmDynarmic64::~ArmDynarmic64() = default;
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void ArmDynarmic64::SetTpidrroEl0(u64 value) {
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m_cb->m_tpidrro_el0 = value;
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}
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void ArmDynarmic64::GetContext(Kernel::Svc::ThreadContext& ctx) const {
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Dynarmic::A64::Jit& j = *m_jit;
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auto gpr = j.GetRegisters();
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auto fpr = j.GetVectors();
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// TODO: this is inconvenient
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for (size_t i = 0; i < 29; i++) {
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ctx.r[i] = gpr[i];
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}
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ctx.fp = gpr[29];
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ctx.lr = gpr[30];
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ctx.sp = j.GetSP();
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ctx.pc = j.GetPC();
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ctx.pstate = j.GetPstate();
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ctx.v = fpr;
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ctx.fpcr = j.GetFpcr();
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ctx.fpsr = j.GetFpsr();
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ctx.tpidr = m_cb->m_tpidr_el0;
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}
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void ArmDynarmic64::SetContext(const Kernel::Svc::ThreadContext& ctx) {
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Dynarmic::A64::Jit& j = *m_jit;
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// TODO: this is inconvenient
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std::array<u64, 31> gpr;
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for (size_t i = 0; i < 29; i++) {
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gpr[i] = ctx.r[i];
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}
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gpr[29] = ctx.fp;
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gpr[30] = ctx.lr;
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j.SetRegisters(gpr);
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j.SetSP(ctx.sp);
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j.SetPC(ctx.pc);
|
|
j.SetPstate(ctx.pstate);
|
|
j.SetVectors(ctx.v);
|
|
j.SetFpcr(ctx.fpcr);
|
|
j.SetFpsr(ctx.fpsr);
|
|
m_cb->m_tpidr_el0 = ctx.tpidr;
|
|
}
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|
|
|
void ArmDynarmic64::SignalInterrupt(Kernel::KThread* thread) {
|
|
m_jit->HaltExecution(BreakLoop);
|
|
}
|
|
|
|
void ArmDynarmic64::ClearInstructionCache() {
|
|
m_jit->ClearCache();
|
|
}
|
|
|
|
void ArmDynarmic64::InvalidateCacheRange(u64 addr, std::size_t size) {
|
|
m_jit->InvalidateCacheRange(addr, size);
|
|
}
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|
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} // namespace Core
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