set sampler max lod, min lod, lod bias and max anisotropy
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		@@ -740,9 +740,9 @@ void RasterizerOpenGL::SamplerInfo::Create() {
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    glSamplerParameteri(sampler.handle, GL_TEXTURE_COMPARE_FUNC, GL_NEVER);
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					    glSamplerParameteri(sampler.handle, GL_TEXTURE_COMPARE_FUNC, GL_NEVER);
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}
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					}
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void RasterizerOpenGL::SamplerInfo::SyncWithConfig(const Tegra::Texture::TSCEntry& config) {
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					void RasterizerOpenGL::SamplerInfo::SyncWithConfig(const Tegra::Texture::FullTextureInfo& info) {
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    const GLuint s = sampler.handle;
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					    const GLuint s = sampler.handle;
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					    const Tegra::Texture::TSCEntry& config = info.tsc;
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    if (mag_filter != config.mag_filter) {
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					    if (mag_filter != config.mag_filter) {
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        mag_filter = config.mag_filter;
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					        mag_filter = config.mag_filter;
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        glSamplerParameteri(
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					        glSamplerParameteri(
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@@ -793,6 +793,17 @@ void RasterizerOpenGL::SamplerInfo::SyncWithConfig(const Tegra::Texture::TSCEntr
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            glSamplerParameterfv(s, GL_TEXTURE_BORDER_COLOR, border_color.data());
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					            glSamplerParameterfv(s, GL_TEXTURE_BORDER_COLOR, border_color.data());
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        }
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					        }
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    }
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					    }
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					    if (info.tic.use_header_opt_control == 0) {
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					        glSamplerParameterf(s, GL_TEXTURE_MAX_ANISOTROPY_EXT,
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					                            static_cast<float>(1 << info.tic.max_anisotropy.Value()));
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					        glSamplerParameterf(s, GL_TEXTURE_MIN_LOD,
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					                            static_cast<float>(info.tic.res_min_mip_level.Value()));
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					        glSamplerParameterf(s, GL_TEXTURE_MAX_LOD,
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					                            static_cast<float>(info.tic.res_max_mip_level.Value() == 0
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					                                                   ? 16
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					                                                   : info.tic.res_max_mip_level.Value()));
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					        glSamplerParameterf(s, GL_TEXTURE_LOD_BIAS, info.tic.mip_lod_bias.Value() / 256.f);
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					    }
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}
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					}
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u32 RasterizerOpenGL::SetupConstBuffers(Maxwell::ShaderStage stage, Shader& shader,
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					u32 RasterizerOpenGL::SetupConstBuffers(Maxwell::ShaderStage stage, Shader& shader,
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@@ -890,7 +901,7 @@ u32 RasterizerOpenGL::SetupTextures(Maxwell::ShaderStage stage, Shader& shader,
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            continue;
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					            continue;
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        }
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					        }
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        texture_samplers[current_bindpoint].SyncWithConfig(texture.tsc);
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					        texture_samplers[current_bindpoint].SyncWithConfig(texture);
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        Surface surface = res_cache.GetTextureSurface(texture, entry);
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					        Surface surface = res_cache.GetTextureSurface(texture, entry);
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        if (surface != nullptr) {
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					        if (surface != nullptr) {
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            state.texture_units[current_bindpoint].texture = surface->Texture().handle;
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					            state.texture_units[current_bindpoint].texture = surface->Texture().handle;
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@@ -996,13 +1007,13 @@ void RasterizerOpenGL::SyncStencilTestState() {
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    state.stencil.front.action_depth_pass = MaxwellToGL::StencilOp(regs.stencil_front_op_zpass);
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					    state.stencil.front.action_depth_pass = MaxwellToGL::StencilOp(regs.stencil_front_op_zpass);
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    state.stencil.front.write_mask = regs.stencil_front_mask;
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					    state.stencil.front.write_mask = regs.stencil_front_mask;
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    state.stencil.back.test_func = MaxwellToGL::ComparisonOp(regs.stencil_back_func_func);
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					        state.stencil.back.test_func = MaxwellToGL::ComparisonOp(regs.stencil_back_func_func);
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    state.stencil.back.test_ref = regs.stencil_back_func_ref;
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					        state.stencil.back.test_ref = regs.stencil_back_func_ref;
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    state.stencil.back.test_mask = regs.stencil_back_func_mask;
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					        state.stencil.back.test_mask = regs.stencil_back_func_mask;
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    state.stencil.back.action_stencil_fail = MaxwellToGL::StencilOp(regs.stencil_back_op_fail);
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					        state.stencil.back.action_stencil_fail = MaxwellToGL::StencilOp(regs.stencil_back_op_fail);
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    state.stencil.back.action_depth_fail = MaxwellToGL::StencilOp(regs.stencil_back_op_zfail);
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					        state.stencil.back.action_depth_fail = MaxwellToGL::StencilOp(regs.stencil_back_op_zfail);
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    state.stencil.back.action_depth_pass = MaxwellToGL::StencilOp(regs.stencil_back_op_zpass);
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					        state.stencil.back.action_depth_pass = MaxwellToGL::StencilOp(regs.stencil_back_op_zpass);
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    state.stencil.back.write_mask = regs.stencil_back_mask;
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					        state.stencil.back.write_mask = regs.stencil_back_mask;
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}
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					}
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void RasterizerOpenGL::SyncColorMask() {
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					void RasterizerOpenGL::SyncColorMask() {
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@@ -88,7 +88,7 @@ private:
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        /// SamplerInfo struct.
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					        /// SamplerInfo struct.
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        void Create();
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					        void Create();
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        /// Syncs the sampler object with the config, updating any necessary state.
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					        /// Syncs the sampler object with the config, updating any necessary state.
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        void SyncWithConfig(const Tegra::Texture::TSCEntry& config);
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					        void SyncWithConfig(const Tegra::Texture::FullTextureInfo& info);
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    private:
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					    private:
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        Tegra::Texture::TextureFilter mag_filter;
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					        Tegra::Texture::TextureFilter mag_filter;
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@@ -168,20 +168,29 @@ struct TICEntry {
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        // High 16 bits of the pitch value
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					        // High 16 bits of the pitch value
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        BitField<0, 16, u32> pitch_high;
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					        BitField<0, 16, u32> pitch_high;
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					        BitField<26, 1, u32> use_header_opt_control;
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					        BitField<27, 1, u32> depth_texture;
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        BitField<28, 4, u32> max_mip_level;
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					        BitField<28, 4, u32> max_mip_level;
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    };
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					    };
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    union {
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					    union {
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        BitField<0, 16, u32> width_minus_1;
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					        BitField<0, 16, u32> width_minus_1;
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        BitField<22, 1, u32> srgb_conversion;
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					        BitField<22, 1, u32> srgb_conversion;
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        BitField<23, 4, TextureType> texture_type;
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					        BitField<23, 4, TextureType> texture_type;
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					        BitField<29, 3, u32> border_size;
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    };
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					    };
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    union {
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					    union {
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        BitField<0, 16, u32> height_minus_1;
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					        BitField<0, 16, u32> height_minus_1;
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        BitField<16, 15, u32> depth_minus_1;
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					        BitField<16, 15, u32> depth_minus_1;
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    };
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					    };
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					    union {
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					        BitField<6, 13, u32> mip_lod_bias;
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					        BitField<27, 3, u32> max_anisotropy;
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					    };
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    INSERT_PADDING_BYTES(8);
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					    union {
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					        BitField<0, 4, u32> res_min_mip_level;
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					        BitField<4, 4, u32> res_max_mip_level;
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					    };
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    GPUVAddr Address() const {
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					    GPUVAddr Address() const {
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        return static_cast<GPUVAddr>((static_cast<GPUVAddr>(address_high) << 32) | address_low);
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					        return static_cast<GPUVAddr>((static_cast<GPUVAddr>(address_high) << 32) | address_low);
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