mirror of
https://github.com/yuzu-emu/yuzu.git
synced 2024-11-15 04:10:07 +00:00
MacroHLE: Add HLE replacement for base vertex and base instance.
This commit is contained in:
parent
93ac5a6a6d
commit
aad0cbf024
@ -339,6 +339,10 @@ Id EmitGetAttribute(EmitContext& ctx, IR::Attribute attr, Id vertex) {
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const Id base{ctx.OpLoad(ctx.U32[1], ctx.base_vertex)};
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return ctx.OpBitcast(ctx.F32[1], ctx.OpISub(ctx.U32[1], index, base));
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}
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case IR::Attribute::BaseInstance:
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return ctx.OpBitcast(ctx.F32[1], ctx.OpLoad(ctx.U32[1], ctx.base_instance));
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case IR::Attribute::BaseVertex:
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return ctx.OpBitcast(ctx.F32[1], ctx.OpLoad(ctx.U32[1], ctx.base_vertex));
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case IR::Attribute::FrontFace:
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return ctx.OpSelect(ctx.F32[1], ctx.OpLoad(ctx.U1, ctx.front_face),
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ctx.OpBitcast(ctx.F32[1], ctx.Const(std::numeric_limits<u32>::max())),
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@ -380,6 +384,10 @@ Id EmitGetAttributeU32(EmitContext& ctx, IR::Attribute attr, Id) {
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const Id base{ctx.OpLoad(ctx.U32[1], ctx.base_vertex)};
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return ctx.OpISub(ctx.U32[1], index, base);
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}
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case IR::Attribute::BaseInstance:
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return ctx.OpLoad(ctx.U32[1], ctx.base_instance);
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case IR::Attribute::BaseVertex:
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return ctx.OpLoad(ctx.U32[1], ctx.base_vertex);
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default:
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throw NotImplementedException("Read U32 attribute {}", attr);
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}
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@ -1379,18 +1379,28 @@ void EmitContext::DefineInputs(const IR::Program& program) {
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if (loads[IR::Attribute::InstanceId]) {
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if (profile.support_vertex_instance_id) {
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instance_id = DefineInput(*this, U32[1], true, spv::BuiltIn::InstanceId);
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if (loads[IR::Attribute::BaseInstance]) {
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base_instance = DefineInput(*this, U32[1], true, spv::BuiltIn::BaseVertex);
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}
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} else {
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instance_index = DefineInput(*this, U32[1], true, spv::BuiltIn::InstanceIndex);
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base_instance = DefineInput(*this, U32[1], true, spv::BuiltIn::BaseInstance);
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}
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} else if (loads[IR::Attribute::BaseInstance]) {
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base_instance = DefineInput(*this, U32[1], true, spv::BuiltIn::BaseInstance);
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}
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if (loads[IR::Attribute::VertexId]) {
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if (profile.support_vertex_instance_id) {
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vertex_id = DefineInput(*this, U32[1], true, spv::BuiltIn::VertexId);
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if (loads[IR::Attribute::BaseVertex]) {
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base_vertex = DefineInput(*this, U32[1], true, spv::BuiltIn::BaseVertex);
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}
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} else {
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vertex_index = DefineInput(*this, U32[1], true, spv::BuiltIn::VertexIndex);
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base_vertex = DefineInput(*this, U32[1], true, spv::BuiltIn::BaseVertex);
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}
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} else if (loads[IR::Attribute::BaseVertex]) {
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base_vertex = DefineInput(*this, U32[1], true, spv::BuiltIn::BaseVertex);
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}
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if (loads[IR::Attribute::FrontFace]) {
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front_face = DefineInput(*this, U1, true, spv::BuiltIn::FrontFacing);
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@ -34,6 +34,11 @@ public:
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[[nodiscard]] virtual std::array<u32, 3> WorkgroupSize() const = 0;
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[[nodiscard]] virtual bool HasHLEMacroState() const = 0;
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[[nodiscard]] virtual std::optional<ReplaceConstant> GetReplaceConstBuffer(
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u32 bank, u32 offset) = 0;
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virtual void Dump(u64 hash) = 0;
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[[nodiscard]] const ProgramHeader& SPH() const noexcept {
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@ -446,6 +446,10 @@ std::string NameOf(Attribute attribute) {
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return "ViewportMask";
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case Attribute::FrontFace:
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return "FrontFace";
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case Attribute::BaseInstance:
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return "BaseInstance";
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case Attribute::BaseVertex:
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return "BaseVertex";
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}
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return fmt::format("<reserved attribute {}>", static_cast<int>(attribute));
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}
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@ -219,6 +219,10 @@ enum class Attribute : u64 {
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FixedFncTexture9Q = 231,
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ViewportMask = 232,
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FrontFace = 255,
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// Implementation attributes
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BaseInstance = 256,
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BaseVertex = 257,
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};
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constexpr size_t NUM_GENERICS = 32;
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@ -294,6 +294,14 @@ F32 IREmitter::GetAttribute(IR::Attribute attribute, const U32& vertex) {
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return Inst<F32>(Opcode::GetAttribute, attribute, vertex);
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}
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U32 IREmitter::GetAttributeU32(IR::Attribute attribute) {
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return GetAttributeU32(attribute, Imm32(0));
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}
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U32 IREmitter::GetAttributeU32(IR::Attribute attribute, const U32& vertex) {
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return Inst<U32>(Opcode::GetAttributeU32, attribute, vertex);
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}
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void IREmitter::SetAttribute(IR::Attribute attribute, const F32& value, const U32& vertex) {
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Inst(Opcode::SetAttribute, attribute, value, vertex);
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}
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@ -74,6 +74,8 @@ public:
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[[nodiscard]] F32 GetAttribute(IR::Attribute attribute);
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[[nodiscard]] F32 GetAttribute(IR::Attribute attribute, const U32& vertex);
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[[nodiscard]] U32 GetAttributeU32(IR::Attribute attribute);
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[[nodiscard]] U32 GetAttributeU32(IR::Attribute attribute, const U32& vertex);
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void SetAttribute(IR::Attribute attribute, const F32& value, const U32& vertex);
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[[nodiscard]] F32 GetAttributeIndexed(const U32& phys_address);
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@ -219,7 +219,7 @@ IR::Program TranslateProgram(ObjectPool<IR::Inst>& inst_pool, ObjectPool<IR::Blo
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}
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Optimization::SsaRewritePass(program);
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Optimization::ConstantPropagationPass(program);
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Optimization::ConstantPropagationPass(env, program);
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Optimization::PositionPass(env, program);
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@ -7,6 +7,7 @@
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#include <type_traits>
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#include "common/bit_cast.h"
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#include "shader_recompiler/environment.h"
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#include "shader_recompiler/exception.h"
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#include "shader_recompiler/frontend/ir/ir_emitter.h"
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#include "shader_recompiler/frontend/ir/value.h"
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@ -515,6 +516,8 @@ void FoldBitCast(IR::Inst& inst, IR::Opcode reverse) {
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case IR::Attribute::PrimitiveId:
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case IR::Attribute::InstanceId:
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case IR::Attribute::VertexId:
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case IR::Attribute::BaseVertex:
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case IR::Attribute::BaseInstance:
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break;
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default:
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return;
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@ -644,7 +647,37 @@ void FoldFSwizzleAdd(IR::Block& block, IR::Inst& inst) {
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}
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}
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void ConstantPropagation(IR::Block& block, IR::Inst& inst) {
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void FoldConstBuffer(Environment& env, IR::Block& block, IR::Inst& inst) {
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const IR::Value bank{inst.Arg(0)};
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const IR::Value offset{inst.Arg(1)};
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if (!bank.IsImmediate() || !offset.IsImmediate()) {
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return;
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}
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const auto bank_value = bank.U32();
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const auto offset_value = offset.U32();
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auto replacement = env.GetReplaceConstBuffer(bank_value, offset_value);
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if (!replacement) {
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return;
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}
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const auto new_attribute = [replacement]() {
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switch (*replacement) {
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case ReplaceConstant::BaseInstance:
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return IR::Attribute::BaseInstance;
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case ReplaceConstant::BaseVertex:
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return IR::Attribute::BaseVertex;
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default:
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throw NotImplementedException("Not implemented replacement variable {}", *replacement);
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}
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}();
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IR::IREmitter ir{block, IR::Block::InstructionList::s_iterator_to(inst)};
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if (inst.GetOpcode() == IR::Opcode::GetCbufU32) {
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inst.ReplaceUsesWith(ir.GetAttributeU32(new_attribute));
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} else {
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inst.ReplaceUsesWith(ir.GetAttribute(new_attribute));
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}
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}
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void ConstantPropagation(Environment& env, IR::Block& block, IR::Inst& inst) {
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switch (inst.GetOpcode()) {
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case IR::Opcode::GetRegister:
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return FoldGetRegister(inst);
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@ -789,18 +822,24 @@ void ConstantPropagation(IR::Block& block, IR::Inst& inst) {
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IR::Opcode::CompositeInsertF16x4);
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case IR::Opcode::FSwizzleAdd:
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return FoldFSwizzleAdd(block, inst);
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case IR::Opcode::GetCbufF32:
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case IR::Opcode::GetCbufU32:
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if (env.HasHLEMacroState()) {
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return FoldConstBuffer(env, block, inst);
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}
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break;
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default:
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break;
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}
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}
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} // Anonymous namespace
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void ConstantPropagationPass(IR::Program& program) {
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void ConstantPropagationPass(Environment& env, IR::Program& program) {
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const auto end{program.post_order_blocks.rend()};
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for (auto it = program.post_order_blocks.rbegin(); it != end; ++it) {
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IR::Block* const block{*it};
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for (IR::Inst& inst : block->Instructions()) {
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ConstantPropagation(*block, inst);
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ConstantPropagation(env, *block, inst);
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}
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}
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}
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@ -13,7 +13,7 @@ struct HostTranslateInfo;
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namespace Shader::Optimization {
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void CollectShaderInfoPass(Environment& env, IR::Program& program);
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void ConstantPropagationPass(IR::Program& program);
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void ConstantPropagationPass(Environment& env, IR::Program& program);
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void DeadCodeEliminationPass(IR::Program& program);
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void GlobalMemoryToStorageBufferPass(IR::Program& program);
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void IdentityRemovalPass(IR::Program& program);
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@ -16,6 +16,11 @@
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namespace Shader {
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enum class ReplaceConstant : u32 {
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BaseInstance,
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BaseVertex,
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};
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enum class TextureType : u32 {
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Color1D,
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ColorArray1D,
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@ -11,7 +11,7 @@
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namespace Shader {
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struct VaryingState {
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std::bitset<256> mask{};
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std::bitset<512> mask{};
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void Set(IR::Attribute attribute, bool state = true) {
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mask[static_cast<size_t>(attribute)] = state;
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@ -182,8 +182,14 @@ u32 Maxwell3D::GetMaxCurrentVertices() {
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size_t Maxwell3D::EstimateIndexBufferSize() {
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GPUVAddr start_address = regs.index_buffer.StartAddress();
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GPUVAddr end_address = regs.index_buffer.EndAddress();
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return std::min<size_t>(memory_manager.GetMemoryLayoutSize(start_address),
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static_cast<size_t>(end_address - start_address));
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constexpr std::array<size_t, 4> max_sizes = {
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std::numeric_limits<u8>::max(), std::numeric_limits<u16>::max(),
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std::numeric_limits<u32>::max(), std::numeric_limits<u32>::max()};
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const size_t byte_size = regs.index_buffer.FormatSizeInBytes();
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return std::min<size_t>(
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memory_manager.GetMemoryLayoutSize(start_address, byte_size * max_sizes[byte_size]) /
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byte_size,
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static_cast<size_t>(end_address - start_address));
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}
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u32 Maxwell3D::ProcessShadowRam(u32 method, u32 argument) {
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@ -572,4 +578,9 @@ u32 Maxwell3D::GetRegisterValue(u32 method) const {
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return regs.reg_array[method];
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}
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void Maxwell3D::setHLEReplacementName(u32 bank, u32 offset, HLEReplaceName name) {
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const u64 key = (static_cast<u64>(bank) << 32) | offset;
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replace_table.emplace(key, name);
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}
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} // namespace Tegra::Engines
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@ -3020,6 +3020,23 @@ public:
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/// Store temporary hw register values, used by some calls to restore state after a operation
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Regs shadow_state;
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// None Engine
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enum class EngineHint : u32 {
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None = 0x0,
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OnHLEMacro = 0x1,
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};
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EngineHint engine_state{EngineHint::None};
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enum class HLEReplaceName : u32 {
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BaseVertex = 0x0,
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BaseInstance = 0x1,
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};
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void setHLEReplacementName(u32 bank, u32 offset, HLEReplaceName name);
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std::unordered_map<u64, HLEReplaceName> replace_table;
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static_assert(sizeof(Regs) == Regs::NUM_REGS * sizeof(u32), "Maxwell3D Regs has wrong size");
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static_assert(std::is_trivially_copyable_v<Regs>, "Maxwell3D Regs must be trivially copyable");
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@ -14,26 +14,29 @@
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#include "video_core/rasterizer_interface.h"
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namespace Tegra {
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using Maxwell = Engines::Maxwell3D;
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namespace {
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bool IsTopologySafe(Tegra::Engines::Maxwell3D::Regs::PrimitiveTopology topology) {
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bool IsTopologySafe(Maxwell::Regs::PrimitiveTopology topology) {
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switch (topology) {
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case Tegra::Engines::Maxwell3D::Regs::PrimitiveTopology::Points:
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case Tegra::Engines::Maxwell3D::Regs::PrimitiveTopology::Lines:
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case Tegra::Engines::Maxwell3D::Regs::PrimitiveTopology::LineLoop:
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case Tegra::Engines::Maxwell3D::Regs::PrimitiveTopology::LineStrip:
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case Tegra::Engines::Maxwell3D::Regs::PrimitiveTopology::Triangles:
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case Tegra::Engines::Maxwell3D::Regs::PrimitiveTopology::TriangleStrip:
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case Tegra::Engines::Maxwell3D::Regs::PrimitiveTopology::TriangleFan:
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case Tegra::Engines::Maxwell3D::Regs::PrimitiveTopology::LinesAdjacency:
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case Tegra::Engines::Maxwell3D::Regs::PrimitiveTopology::LineStripAdjacency:
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case Tegra::Engines::Maxwell3D::Regs::PrimitiveTopology::TrianglesAdjacency:
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case Tegra::Engines::Maxwell3D::Regs::PrimitiveTopology::TriangleStripAdjacency:
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case Tegra::Engines::Maxwell3D::Regs::PrimitiveTopology::Patches:
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case Maxwell::Regs::PrimitiveTopology::Points:
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case Maxwell::Regs::PrimitiveTopology::Lines:
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case Maxwell::Regs::PrimitiveTopology::LineLoop:
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case Maxwell::Regs::PrimitiveTopology::LineStrip:
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case Maxwell::Regs::PrimitiveTopology::Triangles:
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case Maxwell::Regs::PrimitiveTopology::TriangleStrip:
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case Maxwell::Regs::PrimitiveTopology::TriangleFan:
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case Maxwell::Regs::PrimitiveTopology::LinesAdjacency:
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case Maxwell::Regs::PrimitiveTopology::LineStripAdjacency:
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case Maxwell::Regs::PrimitiveTopology::TrianglesAdjacency:
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case Maxwell::Regs::PrimitiveTopology::TriangleStripAdjacency:
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case Maxwell::Regs::PrimitiveTopology::Patches:
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return true;
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case Tegra::Engines::Maxwell3D::Regs::PrimitiveTopology::Quads:
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case Tegra::Engines::Maxwell3D::Regs::PrimitiveTopology::QuadStrip:
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case Tegra::Engines::Maxwell3D::Regs::PrimitiveTopology::Polygon:
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case Maxwell::Regs::PrimitiveTopology::Quads:
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case Maxwell::Regs::PrimitiveTopology::QuadStrip:
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case Maxwell::Regs::PrimitiveTopology::Polygon:
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default:
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return false;
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}
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@ -82,8 +85,7 @@ public:
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: HLEMacroImpl(maxwell3d_), extended(extended_) {}
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void Execute(const std::vector<u32>& parameters, [[maybe_unused]] u32 method) override {
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auto topology =
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static_cast<Tegra::Engines::Maxwell3D::Regs::PrimitiveTopology>(parameters[0]);
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auto topology = static_cast<Maxwell::Regs::PrimitiveTopology>(parameters[0]);
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if (!IsTopologySafe(topology)) {
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Fallback(parameters);
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return;
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@ -99,18 +101,16 @@ public:
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params.stride = 0;
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if (extended) {
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maxwell3d.CallMethod(0x8e3, 0x640, true);
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maxwell3d.CallMethod(0x8e4, parameters[4], true);
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maxwell3d.engine_state = Maxwell::EngineHint::OnHLEMacro;
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maxwell3d.setHLEReplacementName(0, 0x640, Maxwell::HLEReplaceName::BaseInstance);
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}
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maxwell3d.draw_manager->DrawArrayIndirect(topology);
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if (extended) {
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maxwell3d.CallMethod(0x8e3, 0x640, true);
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maxwell3d.CallMethod(0x8e4, 0, true);
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maxwell3d.engine_state = Maxwell::EngineHint::None;
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maxwell3d.replace_table.clear();
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}
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maxwell3d.regs.vertex_buffer.first = 0;
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maxwell3d.regs.vertex_buffer.count = 0;
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}
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private:
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@ -134,13 +134,18 @@ private:
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const u32 base_instance = parameters[4];
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if (extended) {
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maxwell3d.CallMethod(0x8e3, 0x640, true);
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maxwell3d.CallMethod(0x8e4, base_instance, true);
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maxwell3d.engine_state = Maxwell::EngineHint::OnHLEMacro;
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maxwell3d.setHLEReplacementName(0, 0x640, Maxwell::HLEReplaceName::BaseInstance);
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}
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maxwell3d.draw_manager->DrawArray(
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static_cast<Tegra::Engines::Maxwell3D::Regs::PrimitiveTopology>(parameters[0]),
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vertex_first, vertex_count, base_instance, instance_count);
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if (extended) {
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maxwell3d.engine_state = Maxwell::EngineHint::None;
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maxwell3d.replace_table.clear();
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}
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}
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bool extended;
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@ -151,8 +156,7 @@ public:
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explicit HLE_DrawIndexedIndirect(Engines::Maxwell3D& maxwell3d_) : HLEMacroImpl(maxwell3d_) {}
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void Execute(const std::vector<u32>& parameters, [[maybe_unused]] u32 method) override {
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auto topology =
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static_cast<Tegra::Engines::Maxwell3D::Regs::PrimitiveTopology>(parameters[0]);
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auto topology = static_cast<Maxwell::Regs::PrimitiveTopology>(parameters[0]);
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if (!IsTopologySafe(topology)) {
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Fallback(parameters);
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return;
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@ -164,16 +168,12 @@ public:
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minimum_limit = std::max(parameters[3], minimum_limit);
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}
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const u32 estimate = static_cast<u32>(maxwell3d.EstimateIndexBufferSize());
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const u32 base_size = std::max(minimum_limit, estimate);
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const u32 element_base = parameters[4];
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const u32 base_instance = parameters[5];
|
||||
maxwell3d.regs.index_buffer.first = 0;
|
||||
maxwell3d.regs.index_buffer.count = base_size; // Use a fixed size, just for mapping
|
||||
const u32 base_size = std::max<u32>(minimum_limit, estimate);
|
||||
maxwell3d.regs.draw.topology.Assign(topology);
|
||||
maxwell3d.dirty.flags[VideoCommon::Dirty::IndexBuffer] = true;
|
||||
maxwell3d.CallMethod(0x8e3, 0x640, true);
|
||||
maxwell3d.CallMethod(0x8e4, element_base, true);
|
||||
maxwell3d.CallMethod(0x8e5, base_instance, true);
|
||||
maxwell3d.engine_state = Maxwell::EngineHint::OnHLEMacro;
|
||||
maxwell3d.setHLEReplacementName(0, 0x640, Maxwell::HLEReplaceName::BaseVertex);
|
||||
maxwell3d.setHLEReplacementName(0, 0x644, Maxwell::HLEReplaceName::BaseInstance);
|
||||
auto& params = maxwell3d.draw_manager->GetIndirectParams();
|
||||
params.is_indexed = true;
|
||||
params.include_count = false;
|
||||
@ -184,9 +184,8 @@ public:
|
||||
params.stride = 0;
|
||||
maxwell3d.dirty.flags[VideoCommon::Dirty::IndexBuffer] = true;
|
||||
maxwell3d.draw_manager->DrawIndexedIndirect(topology, 0, base_size);
|
||||
maxwell3d.CallMethod(0x8e3, 0x640, true);
|
||||
maxwell3d.CallMethod(0x8e4, 0x0, true);
|
||||
maxwell3d.CallMethod(0x8e5, 0x0, true);
|
||||
maxwell3d.engine_state = Maxwell::EngineHint::None;
|
||||
maxwell3d.replace_table.clear();
|
||||
}
|
||||
|
||||
private:
|
||||
@ -197,18 +196,17 @@ private:
|
||||
const u32 base_instance = parameters[5];
|
||||
maxwell3d.regs.vertex_id_base = element_base;
|
||||
maxwell3d.dirty.flags[VideoCommon::Dirty::IndexBuffer] = true;
|
||||
maxwell3d.CallMethod(0x8e3, 0x640, true);
|
||||
maxwell3d.CallMethod(0x8e4, element_base, true);
|
||||
maxwell3d.CallMethod(0x8e5, base_instance, true);
|
||||
maxwell3d.engine_state = Maxwell::EngineHint::OnHLEMacro;
|
||||
maxwell3d.setHLEReplacementName(0, 0x640, Maxwell::HLEReplaceName::BaseVertex);
|
||||
maxwell3d.setHLEReplacementName(0, 0x644, Maxwell::HLEReplaceName::BaseInstance);
|
||||
|
||||
maxwell3d.draw_manager->DrawIndex(
|
||||
static_cast<Tegra::Engines::Maxwell3D::Regs::PrimitiveTopology>(parameters[0]),
|
||||
parameters[3], parameters[1], element_base, base_instance, instance_count);
|
||||
|
||||
maxwell3d.regs.vertex_id_base = 0x0;
|
||||
maxwell3d.CallMethod(0x8e3, 0x640, true);
|
||||
maxwell3d.CallMethod(0x8e4, 0x0, true);
|
||||
maxwell3d.CallMethod(0x8e5, 0x0, true);
|
||||
maxwell3d.engine_state = Maxwell::EngineHint::None;
|
||||
maxwell3d.replace_table.clear();
|
||||
}
|
||||
|
||||
u32 minimum_limit{1 << 18};
|
||||
@ -238,8 +236,7 @@ public:
|
||||
: HLEMacroImpl(maxwell3d_) {}
|
||||
|
||||
void Execute(const std::vector<u32>& parameters, [[maybe_unused]] u32 method) override {
|
||||
const auto topology =
|
||||
static_cast<Tegra::Engines::Maxwell3D::Regs::PrimitiveTopology>(parameters[2]);
|
||||
const auto topology = static_cast<Maxwell::Regs::PrimitiveTopology>(parameters[2]);
|
||||
if (!IsTopologySafe(topology)) {
|
||||
Fallback(parameters);
|
||||
return;
|
||||
@ -277,9 +274,6 @@ public:
|
||||
}
|
||||
const u32 estimate = static_cast<u32>(maxwell3d.EstimateIndexBufferSize());
|
||||
const u32 base_size = std::max(minimum_limit, estimate);
|
||||
|
||||
maxwell3d.regs.index_buffer.first = 0;
|
||||
maxwell3d.regs.index_buffer.count = std::max(highest_limit, base_size);
|
||||
maxwell3d.dirty.flags[VideoCommon::Dirty::IndexBuffer] = true;
|
||||
auto& params = maxwell3d.draw_manager->GetIndirectParams();
|
||||
params.is_indexed = true;
|
||||
@ -290,7 +284,12 @@ public:
|
||||
params.max_draw_counts = draw_count;
|
||||
params.stride = stride;
|
||||
maxwell3d.dirty.flags[VideoCommon::Dirty::IndexBuffer] = true;
|
||||
maxwell3d.draw_manager->DrawIndexedIndirect(topology, 0, highest_limit);
|
||||
maxwell3d.engine_state = Maxwell::EngineHint::OnHLEMacro;
|
||||
maxwell3d.setHLEReplacementName(0, 0x640, Maxwell::HLEReplaceName::BaseVertex);
|
||||
maxwell3d.setHLEReplacementName(0, 0x644, Maxwell::HLEReplaceName::BaseInstance);
|
||||
maxwell3d.draw_manager->DrawIndexedIndirect(topology, 0, base_size);
|
||||
maxwell3d.engine_state = Maxwell::EngineHint::None;
|
||||
maxwell3d.replace_table.clear();
|
||||
}
|
||||
|
||||
private:
|
||||
@ -299,9 +298,8 @@ private:
|
||||
// Clean everything.
|
||||
// Clean everything.
|
||||
maxwell3d.regs.vertex_id_base = 0x0;
|
||||
maxwell3d.CallMethod(0x8e3, 0x640, true);
|
||||
maxwell3d.CallMethod(0x8e4, 0x0, true);
|
||||
maxwell3d.CallMethod(0x8e5, 0x0, true);
|
||||
maxwell3d.engine_state = Maxwell::EngineHint::None;
|
||||
maxwell3d.replace_table.clear();
|
||||
});
|
||||
maxwell3d.RefreshParameters();
|
||||
const u32 start_indirect = parameters[0];
|
||||
@ -310,8 +308,7 @@ private:
|
||||
// Nothing to do.
|
||||
return;
|
||||
}
|
||||
const auto topology =
|
||||
static_cast<Tegra::Engines::Maxwell3D::Regs::PrimitiveTopology>(parameters[2]);
|
||||
const auto topology = static_cast<Maxwell::Regs::PrimitiveTopology>(parameters[2]);
|
||||
maxwell3d.regs.draw.topology.Assign(topology);
|
||||
const u32 padding = parameters[3];
|
||||
const std::size_t max_draws = parameters[4];
|
||||
@ -326,9 +323,9 @@ private:
|
||||
const u32 base_vertex = parameters[base + 3];
|
||||
const u32 base_instance = parameters[base + 4];
|
||||
maxwell3d.regs.vertex_id_base = base_vertex;
|
||||
maxwell3d.CallMethod(0x8e3, 0x640, true);
|
||||
maxwell3d.CallMethod(0x8e4, base_vertex, true);
|
||||
maxwell3d.CallMethod(0x8e5, base_instance, true);
|
||||
maxwell3d.engine_state = Maxwell::EngineHint::OnHLEMacro;
|
||||
maxwell3d.setHLEReplacementName(0, 0x640, Maxwell::HLEReplaceName::BaseVertex);
|
||||
maxwell3d.setHLEReplacementName(0, 0x644, Maxwell::HLEReplaceName::BaseInstance);
|
||||
maxwell3d.dirty.flags[VideoCommon::Dirty::IndexBuffer] = true;
|
||||
maxwell3d.draw_manager->DrawIndex(topology, parameters[base + 2], parameters[base],
|
||||
base_vertex, base_instance, parameters[base + 1]);
|
||||
|
@ -577,7 +577,7 @@ size_t MemoryManager::MaxContinousRange(GPUVAddr gpu_addr, size_t size) const {
|
||||
return range_so_far;
|
||||
}
|
||||
|
||||
size_t MemoryManager::GetMemoryLayoutSize(GPUVAddr gpu_addr) const {
|
||||
size_t MemoryManager::GetMemoryLayoutSize(GPUVAddr gpu_addr, size_t max_size) const {
|
||||
PTEKind base_kind = GetPageKind(gpu_addr);
|
||||
if (base_kind == PTEKind::INVALID) {
|
||||
return 0;
|
||||
@ -596,6 +596,10 @@ size_t MemoryManager::GetMemoryLayoutSize(GPUVAddr gpu_addr) const {
|
||||
return true;
|
||||
}
|
||||
range_so_far += copy_amount;
|
||||
if (range_so_far >= max_size) {
|
||||
result = true;
|
||||
return true;
|
||||
}
|
||||
return false;
|
||||
};
|
||||
auto big_check = [&](std::size_t page_index, std::size_t offset, std::size_t copy_amount) {
|
||||
@ -605,6 +609,10 @@ size_t MemoryManager::GetMemoryLayoutSize(GPUVAddr gpu_addr) const {
|
||||
return true;
|
||||
}
|
||||
range_so_far += copy_amount;
|
||||
if (range_so_far >= max_size) {
|
||||
result = true;
|
||||
return true;
|
||||
}
|
||||
return false;
|
||||
};
|
||||
auto check_short_pages = [&](std::size_t page_index, std::size_t offset,
|
||||
|
@ -118,7 +118,8 @@ public:
|
||||
|
||||
PTEKind GetPageKind(GPUVAddr gpu_addr) const;
|
||||
|
||||
size_t GetMemoryLayoutSize(GPUVAddr gpu_addr) const;
|
||||
size_t GetMemoryLayoutSize(GPUVAddr gpu_addr,
|
||||
size_t max_size = std::numeric_limits<size_t>::max()) const;
|
||||
|
||||
private:
|
||||
template <bool is_big_pages, typename FuncMapped, typename FuncReserved, typename FuncUnmapped>
|
||||
|
@ -97,6 +97,7 @@ void FixedPipelineState::Refresh(Tegra::Engines::Maxwell3D& maxwell3d,
|
||||
smooth_lines.Assign(regs.line_anti_alias_enable != 0 ? 1 : 0);
|
||||
alpha_to_coverage_enabled.Assign(regs.anti_alias_alpha_control.alpha_to_coverage != 0 ? 1 : 0);
|
||||
alpha_to_one_enabled.Assign(regs.anti_alias_alpha_control.alpha_to_one != 0 ? 1 : 0);
|
||||
app_stage.Assign(maxwell3d.engine_state);
|
||||
|
||||
for (size_t i = 0; i < regs.rt.size(); ++i) {
|
||||
color_formats[i] = static_cast<u8>(regs.rt[i].format);
|
||||
|
@ -197,6 +197,7 @@ struct FixedPipelineState {
|
||||
BitField<14, 1, u32> smooth_lines;
|
||||
BitField<15, 1, u32> alpha_to_coverage_enabled;
|
||||
BitField<16, 1, u32> alpha_to_one_enabled;
|
||||
BitField<17, 3, Tegra::Engines::Maxwell3D::EngineHint> app_stage;
|
||||
};
|
||||
std::array<u8, Maxwell::NumRenderTargets> color_formats;
|
||||
|
||||
|
@ -54,7 +54,7 @@ using VideoCommon::FileEnvironment;
|
||||
using VideoCommon::GenericEnvironment;
|
||||
using VideoCommon::GraphicsEnvironment;
|
||||
|
||||
constexpr u32 CACHE_VERSION = 8;
|
||||
constexpr u32 CACHE_VERSION = 9;
|
||||
|
||||
template <typename Container>
|
||||
auto MakeSpan(Container& container) {
|
||||
|
@ -202,12 +202,15 @@ void GenericEnvironment::Serialize(std::ofstream& file) const {
|
||||
const u64 num_texture_types{static_cast<u64>(texture_types.size())};
|
||||
const u64 num_texture_pixel_formats{static_cast<u64>(texture_pixel_formats.size())};
|
||||
const u64 num_cbuf_values{static_cast<u64>(cbuf_values.size())};
|
||||
const u64 num_cbuf_replacement_values{static_cast<u64>(cbuf_replacements.size())};
|
||||
|
||||
file.write(reinterpret_cast<const char*>(&code_size), sizeof(code_size))
|
||||
.write(reinterpret_cast<const char*>(&num_texture_types), sizeof(num_texture_types))
|
||||
.write(reinterpret_cast<const char*>(&num_texture_pixel_formats),
|
||||
sizeof(num_texture_pixel_formats))
|
||||
.write(reinterpret_cast<const char*>(&num_cbuf_values), sizeof(num_cbuf_values))
|
||||
.write(reinterpret_cast<const char*>(&num_cbuf_replacement_values),
|
||||
sizeof(num_cbuf_replacement_values))
|
||||
.write(reinterpret_cast<const char*>(&local_memory_size), sizeof(local_memory_size))
|
||||
.write(reinterpret_cast<const char*>(&texture_bound), sizeof(texture_bound))
|
||||
.write(reinterpret_cast<const char*>(&start_address), sizeof(start_address))
|
||||
@ -229,6 +232,10 @@ void GenericEnvironment::Serialize(std::ofstream& file) const {
|
||||
file.write(reinterpret_cast<const char*>(&key), sizeof(key))
|
||||
.write(reinterpret_cast<const char*>(&type), sizeof(type));
|
||||
}
|
||||
for (const auto& [key, type] : cbuf_replacements) {
|
||||
file.write(reinterpret_cast<const char*>(&key), sizeof(key))
|
||||
.write(reinterpret_cast<const char*>(&type), sizeof(type));
|
||||
}
|
||||
if (stage == Shader::Stage::Compute) {
|
||||
file.write(reinterpret_cast<const char*>(&workgroup_size), sizeof(workgroup_size))
|
||||
.write(reinterpret_cast<const char*>(&shared_memory_size), sizeof(shared_memory_size));
|
||||
@ -318,6 +325,8 @@ GraphicsEnvironment::GraphicsEnvironment(Tegra::Engines::Maxwell3D& maxwell3d_,
|
||||
ASSERT(local_size <= std::numeric_limits<u32>::max());
|
||||
local_memory_size = static_cast<u32>(local_size) + sph.common3.shader_local_memory_crs_size;
|
||||
texture_bound = maxwell3d->regs.bindless_texture_const_buffer_slot;
|
||||
has_hle_engine_state =
|
||||
maxwell3d->engine_state == Tegra::Engines::Maxwell3D::EngineHint::OnHLEMacro;
|
||||
}
|
||||
|
||||
u32 GraphicsEnvironment::ReadCbufValue(u32 cbuf_index, u32 cbuf_offset) {
|
||||
@ -331,6 +340,30 @@ u32 GraphicsEnvironment::ReadCbufValue(u32 cbuf_index, u32 cbuf_offset) {
|
||||
return value;
|
||||
}
|
||||
|
||||
std::optional<Shader::ReplaceConstant> GraphicsEnvironment::GetReplaceConstBuffer(u32 bank,
|
||||
u32 offset) {
|
||||
if (!has_hle_engine_state) {
|
||||
return std::nullopt;
|
||||
}
|
||||
const u64 key = (static_cast<u64>(bank) << 32) | static_cast<u64>(offset);
|
||||
auto it = maxwell3d->replace_table.find(key);
|
||||
if (it == maxwell3d->replace_table.end()) {
|
||||
return std::nullopt;
|
||||
}
|
||||
const auto converted_value = [](Tegra::Engines::Maxwell3D::HLEReplaceName name) {
|
||||
switch (name) {
|
||||
case Tegra::Engines::Maxwell3D::HLEReplaceName::BaseVertex:
|
||||
return Shader::ReplaceConstant::BaseVertex;
|
||||
case Tegra::Engines::Maxwell3D::HLEReplaceName::BaseInstance:
|
||||
return Shader::ReplaceConstant::BaseInstance;
|
||||
default:
|
||||
UNREACHABLE();
|
||||
}
|
||||
}(it->second);
|
||||
cbuf_replacements.emplace(key, converted_value);
|
||||
return converted_value;
|
||||
}
|
||||
|
||||
Shader::TextureType GraphicsEnvironment::ReadTextureType(u32 handle) {
|
||||
const auto& regs{maxwell3d->regs};
|
||||
const bool via_header_index{regs.sampler_binding == Maxwell::SamplerBinding::ViaHeaderBinding};
|
||||
@ -409,11 +442,14 @@ void FileEnvironment::Deserialize(std::ifstream& file) {
|
||||
u64 num_texture_types{};
|
||||
u64 num_texture_pixel_formats{};
|
||||
u64 num_cbuf_values{};
|
||||
u64 num_cbuf_replacement_values{};
|
||||
file.read(reinterpret_cast<char*>(&code_size), sizeof(code_size))
|
||||
.read(reinterpret_cast<char*>(&num_texture_types), sizeof(num_texture_types))
|
||||
.read(reinterpret_cast<char*>(&num_texture_pixel_formats),
|
||||
sizeof(num_texture_pixel_formats))
|
||||
.read(reinterpret_cast<char*>(&num_cbuf_values), sizeof(num_cbuf_values))
|
||||
.read(reinterpret_cast<char*>(&num_cbuf_replacement_values),
|
||||
sizeof(num_cbuf_replacement_values))
|
||||
.read(reinterpret_cast<char*>(&local_memory_size), sizeof(local_memory_size))
|
||||
.read(reinterpret_cast<char*>(&texture_bound), sizeof(texture_bound))
|
||||
.read(reinterpret_cast<char*>(&start_address), sizeof(start_address))
|
||||
@ -444,6 +480,13 @@ void FileEnvironment::Deserialize(std::ifstream& file) {
|
||||
.read(reinterpret_cast<char*>(&value), sizeof(value));
|
||||
cbuf_values.emplace(key, value);
|
||||
}
|
||||
for (size_t i = 0; i < num_cbuf_replacement_values; ++i) {
|
||||
u64 key;
|
||||
Shader::ReplaceConstant value;
|
||||
file.read(reinterpret_cast<char*>(&key), sizeof(key))
|
||||
.read(reinterpret_cast<char*>(&value), sizeof(value));
|
||||
cbuf_replacements.emplace(key, value);
|
||||
}
|
||||
if (stage == Shader::Stage::Compute) {
|
||||
file.read(reinterpret_cast<char*>(&workgroup_size), sizeof(workgroup_size))
|
||||
.read(reinterpret_cast<char*>(&shared_memory_size), sizeof(shared_memory_size));
|
||||
@ -512,6 +555,16 @@ std::array<u32, 3> FileEnvironment::WorkgroupSize() const {
|
||||
return workgroup_size;
|
||||
}
|
||||
|
||||
std::optional<Shader::ReplaceConstant> FileEnvironment::GetReplaceConstBuffer(u32 bank,
|
||||
u32 offset) {
|
||||
const u64 key = (static_cast<u64>(bank) << 32) | static_cast<u64>(offset);
|
||||
auto it = cbuf_replacements.find(key);
|
||||
if (it == cbuf_replacements.end()) {
|
||||
return std::nullopt;
|
||||
}
|
||||
return it->second;
|
||||
}
|
||||
|
||||
void SerializePipeline(std::span<const char> key, std::span<const GenericEnvironment* const> envs,
|
||||
const std::filesystem::path& filename, u32 cache_version) try {
|
||||
std::ofstream file(filename, std::ios::binary | std::ios::ate | std::ios::app);
|
||||
|
@ -60,6 +60,10 @@ public:
|
||||
|
||||
void Serialize(std::ofstream& file) const;
|
||||
|
||||
bool HasHLEMacroState() const override {
|
||||
return has_hle_engine_state;
|
||||
}
|
||||
|
||||
protected:
|
||||
std::optional<u64> TryFindSize();
|
||||
|
||||
@ -73,6 +77,7 @@ protected:
|
||||
std::unordered_map<u32, Shader::TextureType> texture_types;
|
||||
std::unordered_map<u32, Shader::TexturePixelFormat> texture_pixel_formats;
|
||||
std::unordered_map<u64, u32> cbuf_values;
|
||||
std::unordered_map<u64, Shader::ReplaceConstant> cbuf_replacements;
|
||||
|
||||
u32 local_memory_size{};
|
||||
u32 texture_bound{};
|
||||
@ -89,6 +94,7 @@ protected:
|
||||
u32 viewport_transform_state = 1;
|
||||
|
||||
bool has_unbound_instructions = false;
|
||||
bool has_hle_engine_state = false;
|
||||
};
|
||||
|
||||
class GraphicsEnvironment final : public GenericEnvironment {
|
||||
@ -109,6 +115,8 @@ public:
|
||||
|
||||
u32 ReadViewportTransformState() override;
|
||||
|
||||
std::optional<Shader::ReplaceConstant> GetReplaceConstBuffer(u32 bank, u32 offset) override;
|
||||
|
||||
private:
|
||||
Tegra::Engines::Maxwell3D* maxwell3d{};
|
||||
size_t stage_index{};
|
||||
@ -131,6 +139,11 @@ public:
|
||||
|
||||
u32 ReadViewportTransformState() override;
|
||||
|
||||
std::optional<Shader::ReplaceConstant> GetReplaceConstBuffer(
|
||||
[[maybe_unused]] u32 bank, [[maybe_unused]] u32 offset) override {
|
||||
return std::nullopt;
|
||||
}
|
||||
|
||||
private:
|
||||
Tegra::Engines::KeplerCompute* kepler_compute{};
|
||||
};
|
||||
@ -166,6 +179,13 @@ public:
|
||||
|
||||
[[nodiscard]] std::array<u32, 3> WorkgroupSize() const override;
|
||||
|
||||
[[nodiscard]] std::optional<Shader::ReplaceConstant> GetReplaceConstBuffer(u32 bank,
|
||||
u32 offset) override;
|
||||
|
||||
[[nodiscard]] bool HasHLEMacroState() const override {
|
||||
return cbuf_replacements.size() != 0;
|
||||
}
|
||||
|
||||
void Dump(u64 hash) override;
|
||||
|
||||
private:
|
||||
@ -173,6 +193,7 @@ private:
|
||||
std::unordered_map<u32, Shader::TextureType> texture_types;
|
||||
std::unordered_map<u32, Shader::TexturePixelFormat> texture_pixel_formats;
|
||||
std::unordered_map<u64, u32> cbuf_values;
|
||||
std::unordered_map<u64, Shader::ReplaceConstant> cbuf_replacements;
|
||||
std::array<u32, 3> workgroup_size{};
|
||||
u32 local_memory_size{};
|
||||
u32 shared_memory_size{};
|
||||
|
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