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Merge pull request #3619 from ReinUsesLisp/i2i
shader/conversion: Implement I2I sign extension, saturation and selection
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commit
7b62212461
@ -2,6 +2,10 @@
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// Licensed under GPLv2 or any later version
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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// Refer to the license.txt file included.
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#include <limits>
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#include <optional>
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#include <utility>
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#include "common/assert.h"
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#include "common/assert.h"
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#include "common/common_types.h"
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#include "common/common_types.h"
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#include "video_core/engines/shader_bytecode.h"
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#include "video_core/engines/shader_bytecode.h"
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@ -15,9 +19,49 @@ using Tegra::Shader::OpCode;
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using Tegra::Shader::Register;
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using Tegra::Shader::Register;
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namespace {
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namespace {
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constexpr OperationCode GetFloatSelector(u64 selector) {
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constexpr OperationCode GetFloatSelector(u64 selector) {
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return selector == 0 ? OperationCode::FCastHalf0 : OperationCode::FCastHalf1;
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return selector == 0 ? OperationCode::FCastHalf0 : OperationCode::FCastHalf1;
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}
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}
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constexpr u32 SizeInBits(Register::Size size) {
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switch (size) {
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case Register::Size::Byte:
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return 8;
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case Register::Size::Short:
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return 16;
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case Register::Size::Word:
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return 32;
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case Register::Size::Long:
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return 64;
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}
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return 0;
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}
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constexpr std::optional<std::pair<s32, s32>> IntegerSaturateBounds(Register::Size src_size,
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Register::Size dst_size,
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bool src_signed,
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bool dst_signed) {
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const u32 dst_bits = SizeInBits(dst_size);
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if (src_size == Register::Size::Word && dst_size == Register::Size::Word) {
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if (src_signed == dst_signed) {
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return std::nullopt;
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}
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return std::make_pair(0, std::numeric_limits<s32>::max());
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}
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if (dst_signed) {
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// Signed destination, clamp to [-128, 127] for instance
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return std::make_pair(-(1 << (dst_bits - 1)), (1 << (dst_bits - 1)) - 1);
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} else {
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// Unsigned destination
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if (dst_bits == 32) {
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// Avoid shifting by 32, that is undefined behavior
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return std::make_pair(0, s32(std::numeric_limits<u32>::max()));
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}
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return std::make_pair(0, (1 << dst_bits) - 1);
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}
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}
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} // Anonymous namespace
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} // Anonymous namespace
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u32 ShaderIR::DecodeConversion(NodeBlock& bb, u32 pc) {
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u32 ShaderIR::DecodeConversion(NodeBlock& bb, u32 pc) {
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@ -28,14 +72,13 @@ u32 ShaderIR::DecodeConversion(NodeBlock& bb, u32 pc) {
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case OpCode::Id::I2I_R:
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case OpCode::Id::I2I_R:
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case OpCode::Id::I2I_C:
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case OpCode::Id::I2I_C:
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case OpCode::Id::I2I_IMM: {
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case OpCode::Id::I2I_IMM: {
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UNIMPLEMENTED_IF(instr.conversion.int_src.selector != 0);
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const bool src_signed = instr.conversion.is_input_signed;
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UNIMPLEMENTED_IF(instr.conversion.dst_size != Register::Size::Word);
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const bool dst_signed = instr.conversion.is_output_signed;
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UNIMPLEMENTED_IF(instr.alu.saturate_d);
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const Register::Size src_size = instr.conversion.src_size;
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const Register::Size dst_size = instr.conversion.dst_size;
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const u32 selector = static_cast<u32>(instr.conversion.int_src.selector);
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const bool input_signed = instr.conversion.is_input_signed;
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Node value = [this, instr, opcode] {
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const bool output_signed = instr.conversion.is_output_signed;
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Node value = [&]() {
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switch (opcode->get().GetId()) {
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switch (opcode->get().GetId()) {
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case OpCode::Id::I2I_R:
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case OpCode::Id::I2I_R:
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return GetRegister(instr.gpr20);
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return GetRegister(instr.gpr20);
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@ -48,16 +91,60 @@ u32 ShaderIR::DecodeConversion(NodeBlock& bb, u32 pc) {
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return Immediate(0);
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return Immediate(0);
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}
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}
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}();
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}();
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value = ConvertIntegerSize(value, instr.conversion.src_size, input_signed);
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value = GetOperandAbsNegInteger(value, instr.conversion.abs_a, instr.conversion.negate_a,
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// Ensure the source selector is valid
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input_signed);
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switch (instr.conversion.src_size) {
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if (input_signed != output_signed) {
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case Register::Size::Byte:
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value = SignedOperation(OperationCode::ICastUnsigned, output_signed, NO_PRECISE, value);
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break;
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case Register::Size::Short:
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ASSERT(selector == 0 || selector == 2);
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break;
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default:
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ASSERT(selector == 0);
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break;
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}
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if (src_size != Register::Size::Word || selector != 0) {
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value = SignedOperation(OperationCode::IBitfieldExtract, src_signed, std::move(value),
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Immediate(selector * 8), Immediate(SizeInBits(src_size)));
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}
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value = GetOperandAbsNegInteger(std::move(value), instr.conversion.abs_a,
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instr.conversion.negate_a, src_signed);
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if (instr.alu.saturate_d) {
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if (src_signed && !dst_signed) {
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Node is_negative = Operation(OperationCode::LogicalUGreaterEqual, value,
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Immediate(1 << (SizeInBits(src_size) - 1)));
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value = Operation(OperationCode::Select, std::move(is_negative), Immediate(0),
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std::move(value));
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// Simplify generated expressions, this can be removed without semantic impact
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SetTemporary(bb, 0, std::move(value));
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value = GetTemporary(0);
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if (dst_size != Register::Size::Word) {
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const Node limit = Immediate((1 << SizeInBits(dst_size)) - 1);
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Node is_large =
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Operation(OperationCode::LogicalUGreaterThan, std::move(value), limit);
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value = Operation(OperationCode::Select, std::move(is_large), limit,
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std::move(value));
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}
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} else if (const std::optional bounds =
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IntegerSaturateBounds(src_size, dst_size, src_signed, dst_signed)) {
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value = SignedOperation(OperationCode::IMax, src_signed, std::move(value),
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Immediate(bounds->first));
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value = SignedOperation(OperationCode::IMin, src_signed, std::move(value),
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Immediate(bounds->second));
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}
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} else if (dst_size != Register::Size::Word) {
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// No saturation, we only have to mask the result
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Node mask = Immediate((1 << SizeInBits(dst_size)) - 1);
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value = Operation(OperationCode::UBitwiseAnd, std::move(value), std::move(mask));
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}
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}
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SetInternalFlagsFromInteger(bb, value, instr.generates_cc);
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SetInternalFlagsFromInteger(bb, value, instr.generates_cc);
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SetRegister(bb, instr.gpr0, value);
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SetRegister(bb, instr.gpr0, std::move(value));
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break;
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break;
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}
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}
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case OpCode::Id::I2F_R:
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case OpCode::Id::I2F_R:
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