mirror of
https://github.com/yuzu-emu/yuzu.git
synced 2024-11-16 06:20:06 +00:00
Fixed FSETP and FSET
This commit is contained in:
parent
f034121620
commit
5c5b4e8e7d
@ -753,7 +753,6 @@ union Instruction {
|
|||||||
BitField<45, 2, PredOperation> op;
|
BitField<45, 2, PredOperation> op;
|
||||||
BitField<47, 1, u64> ftz;
|
BitField<47, 1, u64> ftz;
|
||||||
BitField<48, 4, PredCondition> cond;
|
BitField<48, 4, PredCondition> cond;
|
||||||
BitField<56, 1, u64> neg_b;
|
|
||||||
} fsetp;
|
} fsetp;
|
||||||
|
|
||||||
union {
|
union {
|
||||||
@ -828,7 +827,6 @@ union Instruction {
|
|||||||
BitField<53, 1, u64> neg_b;
|
BitField<53, 1, u64> neg_b;
|
||||||
BitField<54, 1, u64> abs_a;
|
BitField<54, 1, u64> abs_a;
|
||||||
BitField<55, 1, u64> ftz;
|
BitField<55, 1, u64> ftz;
|
||||||
BitField<56, 1, u64> neg_imm;
|
|
||||||
} fset;
|
} fset;
|
||||||
|
|
||||||
union {
|
union {
|
||||||
|
@ -2736,20 +2736,13 @@ private:
|
|||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
case OpCode::Type::FloatSetPredicate: {
|
case OpCode::Type::FloatSetPredicate: {
|
||||||
std::string op_a = instr.fsetp.neg_a ? "-" : "";
|
const std::string op_a =
|
||||||
op_a += regs.GetRegisterAsFloat(instr.gpr8);
|
GetOperandAbsNeg(regs.GetRegisterAsFloat(instr.gpr8), instr.fsetp.abs_a != 0,
|
||||||
|
instr.fsetp.neg_a != 0);
|
||||||
|
|
||||||
if (instr.fsetp.abs_a) {
|
std::string op_b;
|
||||||
op_a = "abs(" + op_a + ')';
|
|
||||||
}
|
|
||||||
|
|
||||||
std::string op_b{};
|
|
||||||
|
|
||||||
if (instr.is_b_imm) {
|
if (instr.is_b_imm) {
|
||||||
if (instr.fsetp.neg_b) {
|
|
||||||
// Only the immediate version of fsetp has a neg_b bit.
|
|
||||||
op_b += '-';
|
|
||||||
}
|
|
||||||
op_b += '(' + GetImmediate19(instr) + ')';
|
op_b += '(' + GetImmediate19(instr) + ')';
|
||||||
} else {
|
} else {
|
||||||
if (instr.is_b_gpr) {
|
if (instr.is_b_gpr) {
|
||||||
@ -2945,33 +2938,24 @@ private:
|
|||||||
break;
|
break;
|
||||||
}
|
}
|
||||||
case OpCode::Type::FloatSet: {
|
case OpCode::Type::FloatSet: {
|
||||||
std::string op_a = instr.fset.neg_a ? "-" : "";
|
const std::string op_a = GetOperandAbsNeg(regs.GetRegisterAsFloat(instr.gpr8),
|
||||||
op_a += regs.GetRegisterAsFloat(instr.gpr8);
|
instr.fset.abs_a != 0, instr.fset.neg_a != 0);
|
||||||
|
|
||||||
if (instr.fset.abs_a) {
|
std::string op_b;
|
||||||
op_a = "abs(" + op_a + ')';
|
|
||||||
}
|
|
||||||
|
|
||||||
std::string op_b = instr.fset.neg_b ? "-" : "";
|
|
||||||
|
|
||||||
if (instr.is_b_imm) {
|
if (instr.is_b_imm) {
|
||||||
const std::string imm = GetImmediate19(instr);
|
const std::string imm = GetImmediate19(instr);
|
||||||
if (instr.fset.neg_imm)
|
op_b = imm;
|
||||||
op_b += "(-" + imm + ')';
|
|
||||||
else
|
|
||||||
op_b += imm;
|
|
||||||
} else {
|
} else {
|
||||||
if (instr.is_b_gpr) {
|
if (instr.is_b_gpr) {
|
||||||
op_b += regs.GetRegisterAsFloat(instr.gpr20);
|
op_b = regs.GetRegisterAsFloat(instr.gpr20);
|
||||||
} else {
|
} else {
|
||||||
op_b += regs.GetUniform(instr.cbuf34.index, instr.cbuf34.offset,
|
op_b = regs.GetUniform(instr.cbuf34.index, instr.cbuf34.offset,
|
||||||
GLSLRegister::Type::Float);
|
GLSLRegister::Type::Float);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
if (instr.fset.abs_b) {
|
op_b = GetOperandAbsNeg(op_b, instr.fset.abs_b != 0, instr.fset.neg_b != 0);
|
||||||
op_b = "abs(" + op_b + ')';
|
|
||||||
}
|
|
||||||
|
|
||||||
// The fset instruction sets a register to 1.0 or -1 (depending on the bf bit) if the
|
// The fset instruction sets a register to 1.0 or -1 (depending on the bf bit) if the
|
||||||
// condition is true, and to 0 otherwise.
|
// condition is true, and to 0 otherwise.
|
||||||
|
Loading…
Reference in New Issue
Block a user