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ARMInterface/Externals: Update dynarmic and fit to latest version.
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parent
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commit
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2
externals/dynarmic
vendored
2
externals/dynarmic
vendored
@ -1 +1 @@
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Subproject commit e7166e8ba74d7b9c85e87afc0aaf667e7e84cfe0
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Subproject commit f4922a97f6eb4b93decfbd80a881a7eac89d6890
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@ -195,7 +195,7 @@ std::shared_ptr<Dynarmic::A64::Jit> ARM_Dynarmic_64::MakeJit(Common::PageTable&
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config.enable_fast_dispatch = false;
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config.enable_fast_dispatch = false;
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}
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}
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// CNTPCT uses wall clock.
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// Timing
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config.wall_clock_cntpct = uses_wall_clock;
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config.wall_clock_cntpct = uses_wall_clock;
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return std::make_shared<Dynarmic::A64::Jit>(config);
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return std::make_shared<Dynarmic::A64::Jit>(config);
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@ -271,7 +271,7 @@ void ARM_Dynarmic_64::SetTPIDR_EL0(u64 value) {
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}
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}
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void ARM_Dynarmic_64::ChangeProcessorId(std::size_t new_core_id) {
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void ARM_Dynarmic_64::ChangeProcessorId(std::size_t new_core_id) {
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jit->ChangeProcessorId(new_core_id);
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jit->ChangeProcessorID(new_core_id);
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}
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}
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void ARM_Dynarmic_64::SaveContext(ThreadContext64& ctx) {
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void ARM_Dynarmic_64::SaveContext(ThreadContext64& ctx) {
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@ -358,31 +358,31 @@ void DynarmicExclusiveMonitor::ClearExclusive() {
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}
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}
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bool DynarmicExclusiveMonitor::ExclusiveWrite8(std::size_t core_index, VAddr vaddr, u8 value) {
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bool DynarmicExclusiveMonitor::ExclusiveWrite8(std::size_t core_index, VAddr vaddr, u8 value) {
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return monitor.DoExclusiveOperation<u8>(core_index, vaddr, 1, [&](u8 expected) -> bool {
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return monitor.DoExclusiveOperation<u8>(core_index, vaddr, [&](u8 expected) -> bool {
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return memory.WriteExclusive8(vaddr, value, expected);
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return memory.WriteExclusive8(vaddr, value, expected);
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});
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});
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}
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}
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bool DynarmicExclusiveMonitor::ExclusiveWrite16(std::size_t core_index, VAddr vaddr, u16 value) {
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bool DynarmicExclusiveMonitor::ExclusiveWrite16(std::size_t core_index, VAddr vaddr, u16 value) {
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return monitor.DoExclusiveOperation<u16>(core_index, vaddr, 2, [&](u16 expected) -> bool {
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return monitor.DoExclusiveOperation<u16>(core_index, vaddr, [&](u16 expected) -> bool {
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return memory.WriteExclusive16(vaddr, value, expected);
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return memory.WriteExclusive16(vaddr, value, expected);
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});
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});
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}
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}
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bool DynarmicExclusiveMonitor::ExclusiveWrite32(std::size_t core_index, VAddr vaddr, u32 value) {
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bool DynarmicExclusiveMonitor::ExclusiveWrite32(std::size_t core_index, VAddr vaddr, u32 value) {
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return monitor.DoExclusiveOperation<u32>(core_index, vaddr, 4, [&](u32 expected) -> bool {
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return monitor.DoExclusiveOperation<u32>(core_index, vaddr, [&](u32 expected) -> bool {
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return memory.WriteExclusive32(vaddr, value, expected);
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return memory.WriteExclusive32(vaddr, value, expected);
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});
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});
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}
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}
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bool DynarmicExclusiveMonitor::ExclusiveWrite64(std::size_t core_index, VAddr vaddr, u64 value) {
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bool DynarmicExclusiveMonitor::ExclusiveWrite64(std::size_t core_index, VAddr vaddr, u64 value) {
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return monitor.DoExclusiveOperation<u64>(core_index, vaddr, 8, [&](u64 expected) -> bool {
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return monitor.DoExclusiveOperation<u64>(core_index, vaddr, [&](u64 expected) -> bool {
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return memory.WriteExclusive64(vaddr, value, expected);
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return memory.WriteExclusive64(vaddr, value, expected);
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});
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});
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}
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}
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bool DynarmicExclusiveMonitor::ExclusiveWrite128(std::size_t core_index, VAddr vaddr, u128 value) {
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bool DynarmicExclusiveMonitor::ExclusiveWrite128(std::size_t core_index, VAddr vaddr, u128 value) {
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return monitor.DoExclusiveOperation<u128>(core_index, vaddr, 16, [&](u128 expected) -> bool {
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return monitor.DoExclusiveOperation<u128>(core_index, vaddr, [&](u128 expected) -> bool {
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return memory.WriteExclusive128(vaddr, value, expected);
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return memory.WriteExclusive128(vaddr, value, expected);
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});
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});
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}
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}
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