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Merge pull request #9079 from Morph1984/unknown-unkowns

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general: Fix spelling
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Morph 2022-10-17 02:56:58 -04:00 committed by GitHub
commit 2f37c7948f
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GPG Key ID: 4AEE18F83AFDEB23
5 changed files with 18 additions and 18 deletions
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20
src/core/hid/irs_types.h
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@ -14,7 +14,7 @@ enum class CameraAmbientNoiseLevel : u32 {
Low, Low,
Medium, Medium,
High, High,
Unkown3, // This level can't be reached Unknown3, // This level can't be reached
}; };
// This is nn::irsensor::CameraLightTarget // This is nn::irsensor::CameraLightTarget
@ -75,9 +75,9 @@ enum class IrCameraStatus : u32 {
enum class IrCameraInternalStatus : u32 { enum class IrCameraInternalStatus : u32 {
Stopped, Stopped,
FirmwareUpdateNeeded, FirmwareUpdateNeeded,
Unkown2, Unknown2,
Unkown3, Unknown3,
Unkown4, Unknown4,
FirmwareVersionRequested, FirmwareVersionRequested,
FirmwareVersionIsInvalid, FirmwareVersionIsInvalid,
Ready, Ready,
@ -121,20 +121,20 @@ enum class IrSensorFunctionLevel : u8 {
// This is nn::irsensor::MomentProcessorPreprocess // This is nn::irsensor::MomentProcessorPreprocess
enum class MomentProcessorPreprocess : u32 { enum class MomentProcessorPreprocess : u32 {
Unkown0, Unknown0,
Unkown1, Unknown1,
}; };
// This is nn::irsensor::PackedMomentProcessorPreprocess // This is nn::irsensor::PackedMomentProcessorPreprocess
enum class PackedMomentProcessorPreprocess : u8 { enum class PackedMomentProcessorPreprocess : u8 {
Unkown0, Unknown0,
Unkown1, Unknown1,
}; };
// This is nn::irsensor::PointingStatus // This is nn::irsensor::PointingStatus
enum class PointingStatus : u32 { enum class PointingStatus : u32 {
Unkown0, Unknown0,
Unkown1, Unknown1,
}; };
struct IrsRect { struct IrsRect {

2
src/core/hle/service/hid/hid.cpp
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@ -2118,7 +2118,7 @@ void Hid::WritePalmaWaveEntry(Kernel::HLERequestContext& ctx) {
ASSERT_MSG(t_mem->GetSize() == 0x3000, "t_mem has incorrect size"); ASSERT_MSG(t_mem->GetSize() == 0x3000, "t_mem has incorrect size");
LOG_WARNING(Service_HID, LOG_WARNING(Service_HID,
"(STUBBED) called, connection_handle={}, wave_set={}, unkown={}, " "(STUBBED) called, connection_handle={}, wave_set={}, unknown={}, "
"t_mem_handle=0x{:08X}, t_mem_size={}, size={}", "t_mem_handle=0x{:08X}, t_mem_size={}, size={}",
connection_handle.npad_id, wave_set, unknown, t_mem_handle, t_mem_size, size); connection_handle.npad_id, wave_set, unknown, t_mem_handle, t_mem_size, size);

4
src/core/hle/service/hid/irsensor/pointing_processor.h
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@ -37,10 +37,10 @@ private:
u8 pointing_status; u8 pointing_status;
INSERT_PADDING_BYTES(3); INSERT_PADDING_BYTES(3);
u32 unknown; u32 unknown;
float unkown_float1; float unknown_float1;
float position_x; float position_x;
float position_y; float position_y;
float unkown_float2; float unknown_float2;
Core::IrSensor::IrsRect window_of_interest; Core::IrSensor::IrsRect window_of_interest;
}; };
static_assert(sizeof(PointingProcessorMarkerData) == 0x20, static_assert(sizeof(PointingProcessorMarkerData) == 0x20,

2
src/video_core/texture_cache/descriptor_table.h
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@ -18,7 +18,7 @@ class DescriptorTable {
public: public:
explicit DescriptorTable(Tegra::MemoryManager& gpu_memory_) : gpu_memory{gpu_memory_} {} explicit DescriptorTable(Tegra::MemoryManager& gpu_memory_) : gpu_memory{gpu_memory_} {}
[[nodiscard]] bool Synchornize(GPUVAddr gpu_addr, u32 limit) { [[nodiscard]] bool Synchronize(GPUVAddr gpu_addr, u32 limit) {
[[likely]] if (current_gpu_addr == gpu_addr && current_limit == limit) { [[likely]] if (current_gpu_addr == gpu_addr && current_limit == limit) {
return false; return false;
} }

8
src/video_core/texture_cache/texture_cache.h
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@ -193,11 +193,11 @@ void TextureCache<P>::SynchronizeGraphicsDescriptors() {
const bool linked_tsc = maxwell3d->regs.sampler_binding == SamplerBinding::ViaHeaderBinding; const bool linked_tsc = maxwell3d->regs.sampler_binding == SamplerBinding::ViaHeaderBinding;
const u32 tic_limit = maxwell3d->regs.tex_header.limit; const u32 tic_limit = maxwell3d->regs.tex_header.limit;
const u32 tsc_limit = linked_tsc ? tic_limit : maxwell3d->regs.tex_sampler.limit; const u32 tsc_limit = linked_tsc ? tic_limit : maxwell3d->regs.tex_sampler.limit;
if (channel_state->graphics_sampler_table.Synchornize(maxwell3d->regs.tex_sampler.Address(), if (channel_state->graphics_sampler_table.Synchronize(maxwell3d->regs.tex_sampler.Address(),
tsc_limit)) { tsc_limit)) {
channel_state->graphics_sampler_ids.resize(tsc_limit + 1, CORRUPT_ID); channel_state->graphics_sampler_ids.resize(tsc_limit + 1, CORRUPT_ID);
} }
if (channel_state->graphics_image_table.Synchornize(maxwell3d->regs.tex_header.Address(), if (channel_state->graphics_image_table.Synchronize(maxwell3d->regs.tex_header.Address(),
tic_limit)) { tic_limit)) {
channel_state->graphics_image_view_ids.resize(tic_limit + 1, CORRUPT_ID); channel_state->graphics_image_view_ids.resize(tic_limit + 1, CORRUPT_ID);
} }
@ -209,10 +209,10 @@ void TextureCache<P>::SynchronizeComputeDescriptors() {
const u32 tic_limit = kepler_compute->regs.tic.limit; const u32 tic_limit = kepler_compute->regs.tic.limit;
const u32 tsc_limit = linked_tsc ? tic_limit : kepler_compute->regs.tsc.limit; const u32 tsc_limit = linked_tsc ? tic_limit : kepler_compute->regs.tsc.limit;
const GPUVAddr tsc_gpu_addr = kepler_compute->regs.tsc.Address(); const GPUVAddr tsc_gpu_addr = kepler_compute->regs.tsc.Address();
if (channel_state->compute_sampler_table.Synchornize(tsc_gpu_addr, tsc_limit)) { if (channel_state->compute_sampler_table.Synchronize(tsc_gpu_addr, tsc_limit)) {
channel_state->compute_sampler_ids.resize(tsc_limit + 1, CORRUPT_ID); channel_state->compute_sampler_ids.resize(tsc_limit + 1, CORRUPT_ID);
} }
if (channel_state->compute_image_table.Synchornize(kepler_compute->regs.tic.Address(), if (channel_state->compute_image_table.Synchronize(kepler_compute->regs.tic.Address(),
tic_limit)) { tic_limit)) {
channel_state->compute_image_view_ids.resize(tic_limit + 1, CORRUPT_ID); channel_state->compute_image_view_ids.resize(tic_limit + 1, CORRUPT_ID);
} }