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Merge pull request #549 from bunnei/iadd
gl_shader_decompiler: Implement IADD instruction.
This commit is contained in:
commit
174c22e5f6
@ -213,6 +213,7 @@ union Instruction {
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BitField<28, 8, Register> gpr28;
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BitField<28, 8, Register> gpr28;
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BitField<39, 8, Register> gpr39;
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BitField<39, 8, Register> gpr39;
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BitField<48, 16, u64> opcode;
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BitField<48, 16, u64> opcode;
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BitField<50, 1, u64> saturate_a;
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union {
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union {
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BitField<20, 19, u64> imm20_19;
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BitField<20, 19, u64> imm20_19;
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@ -263,7 +264,7 @@ union Instruction {
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BitField<39, 5, u64> shift_amount;
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BitField<39, 5, u64> shift_amount;
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BitField<48, 1, u64> negate_b;
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BitField<48, 1, u64> negate_b;
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BitField<49, 1, u64> negate_a;
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BitField<49, 1, u64> negate_a;
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} iscadd;
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} alu_integer;
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union {
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union {
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BitField<20, 8, u64> shift_position;
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BitField<20, 8, u64> shift_position;
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@ -331,7 +332,6 @@ union Instruction {
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BitField<41, 2, u64> selector;
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BitField<41, 2, u64> selector;
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BitField<45, 1, u64> negate_a;
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BitField<45, 1, u64> negate_a;
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BitField<49, 1, u64> abs_a;
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BitField<49, 1, u64> abs_a;
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BitField<50, 1, u64> saturate_a;
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union {
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union {
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BitField<39, 2, F2iRoundingOp> rounding;
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BitField<39, 2, F2iRoundingOp> rounding;
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@ -434,6 +434,9 @@ public:
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FMUL_R,
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FMUL_R,
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FMUL_IMM,
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FMUL_IMM,
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FMUL32_IMM,
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FMUL32_IMM,
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IADD_C,
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IADD_R,
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IADD_IMM,
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ISCADD_C, // Scale and Add
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ISCADD_C, // Scale and Add
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ISCADD_R,
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ISCADD_R,
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ISCADD_IMM,
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ISCADD_IMM,
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@ -489,10 +492,10 @@ public:
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enum class Type {
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enum class Type {
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Trivial,
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Trivial,
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Arithmetic,
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Arithmetic,
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ArithmeticInteger,
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Bfe,
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Bfe,
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Logic,
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Logic,
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Shift,
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Shift,
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ScaledAdd,
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Ffma,
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Ffma,
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Flow,
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Flow,
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Memory,
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Memory,
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@ -617,9 +620,12 @@ private:
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INST("0101110001101---", Id::FMUL_R, Type::Arithmetic, "FMUL_R"),
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INST("0101110001101---", Id::FMUL_R, Type::Arithmetic, "FMUL_R"),
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INST("0011100-01101---", Id::FMUL_IMM, Type::Arithmetic, "FMUL_IMM"),
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INST("0011100-01101---", Id::FMUL_IMM, Type::Arithmetic, "FMUL_IMM"),
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INST("00011110--------", Id::FMUL32_IMM, Type::Arithmetic, "FMUL32_IMM"),
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INST("00011110--------", Id::FMUL32_IMM, Type::Arithmetic, "FMUL32_IMM"),
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INST("0100110000011---", Id::ISCADD_C, Type::ScaledAdd, "ISCADD_C"),
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INST("0100110000010---", Id::IADD_C, Type::ArithmeticInteger, "IADD_C"),
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INST("0101110000011---", Id::ISCADD_R, Type::ScaledAdd, "ISCADD_R"),
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INST("0101110000010---", Id::IADD_R, Type::ArithmeticInteger, "IADD_R"),
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INST("0011100-00011---", Id::ISCADD_IMM, Type::ScaledAdd, "ISCADD_IMM"),
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INST("0011100-00010---", Id::IADD_IMM, Type::ArithmeticInteger, "IADD_IMM"),
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INST("0100110000011---", Id::ISCADD_C, Type::ArithmeticInteger, "ISCADD_C"),
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INST("0101110000011---", Id::ISCADD_R, Type::ArithmeticInteger, "ISCADD_R"),
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INST("0011100-00011---", Id::ISCADD_IMM, Type::ArithmeticInteger, "ISCADD_IMM"),
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INST("0101000010000---", Id::MUFU, Type::Arithmetic, "MUFU"),
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INST("0101000010000---", Id::MUFU, Type::Arithmetic, "MUFU"),
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INST("0100110010010---", Id::RRO_C, Type::Arithmetic, "RRO_C"),
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INST("0100110010010---", Id::RRO_C, Type::Arithmetic, "RRO_C"),
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INST("0101110010010---", Id::RRO_R, Type::Arithmetic, "RRO_R"),
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INST("0101110010010---", Id::RRO_R, Type::Arithmetic, "RRO_R"),
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@ -808,6 +808,8 @@ private:
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case OpCode::Id::FMUL_C:
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case OpCode::Id::FMUL_C:
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case OpCode::Id::FMUL_R:
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case OpCode::Id::FMUL_R:
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case OpCode::Id::FMUL_IMM: {
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case OpCode::Id::FMUL_IMM: {
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ASSERT_MSG(!instr.saturate_a, "Unimplemented");
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regs.SetRegisterToFloat(instr.gpr0, 0, op_a + " * " + op_b, 1, 1, instr.alu.abs_d);
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regs.SetRegisterToFloat(instr.gpr0, 0, op_a + " * " + op_b, 1, 1, instr.alu.abs_d);
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break;
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break;
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}
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}
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@ -821,10 +823,14 @@ private:
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case OpCode::Id::FADD_C:
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case OpCode::Id::FADD_C:
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case OpCode::Id::FADD_R:
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case OpCode::Id::FADD_R:
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case OpCode::Id::FADD_IMM: {
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case OpCode::Id::FADD_IMM: {
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ASSERT_MSG(!instr.saturate_a, "Unimplemented");
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regs.SetRegisterToFloat(instr.gpr0, 0, op_a + " + " + op_b, 1, 1, instr.alu.abs_d);
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regs.SetRegisterToFloat(instr.gpr0, 0, op_a + " + " + op_b, 1, 1, instr.alu.abs_d);
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break;
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break;
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}
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}
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case OpCode::Id::MUFU: {
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case OpCode::Id::MUFU: {
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ASSERT_MSG(!instr.saturate_a, "Unimplemented");
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switch (instr.sub_op) {
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switch (instr.sub_op) {
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case SubOp::Cos:
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case SubOp::Cos:
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regs.SetRegisterToFloat(instr.gpr0, 0, "cos(" + op_a + ')', 1, 1,
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regs.SetRegisterToFloat(instr.gpr0, 0, "cos(" + op_a + ')', 1, 1,
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@ -986,13 +992,13 @@ private:
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break;
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break;
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}
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}
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case OpCode::Type::ScaledAdd: {
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case OpCode::Type::ArithmeticInteger: {
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std::string op_a = regs.GetRegisterAsInteger(instr.gpr8);
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std::string op_a = regs.GetRegisterAsInteger(instr.gpr8);
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if (instr.iscadd.negate_a)
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if (instr.alu_integer.negate_a)
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op_a = '-' + op_a;
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op_a = '-' + op_a;
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std::string op_b = instr.iscadd.negate_b ? "-" : "";
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std::string op_b = instr.alu_integer.negate_b ? "-" : "";
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if (instr.is_b_imm) {
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if (instr.is_b_imm) {
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op_b += '(' + std::to_string(instr.alu.GetSignedImm20_20()) + ')';
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op_b += '(' + std::to_string(instr.alu.GetSignedImm20_20()) + ')';
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@ -1005,13 +1011,35 @@ private:
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}
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}
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}
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}
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std::string shift = std::to_string(instr.iscadd.shift_amount.Value());
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switch (opcode->GetId()) {
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case OpCode::Id::IADD_C:
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case OpCode::Id::IADD_R:
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case OpCode::Id::IADD_IMM: {
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ASSERT_MSG(!instr.saturate_a, "Unimplemented");
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regs.SetRegisterToInteger(instr.gpr0, true, 0, op_a + " + " + op_b, 1, 1);
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break;
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}
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case OpCode::Id::ISCADD_C:
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case OpCode::Id::ISCADD_R:
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case OpCode::Id::ISCADD_IMM: {
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std::string shift = std::to_string(instr.alu_integer.shift_amount.Value());
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regs.SetRegisterToInteger(instr.gpr0, true, 0,
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regs.SetRegisterToInteger(instr.gpr0, true, 0,
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"((" + op_a + " << " + shift + ") + " + op_b + ')', 1, 1);
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"((" + op_a + " << " + shift + ") + " + op_b + ')', 1, 1);
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break;
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break;
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}
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}
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default: {
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NGLOG_CRITICAL(HW_GPU, "Unhandled ArithmeticInteger instruction: {}",
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opcode->GetName());
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UNREACHABLE();
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}
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}
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break;
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}
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case OpCode::Type::Ffma: {
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case OpCode::Type::Ffma: {
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ASSERT_MSG(!instr.saturate_a, "Unimplemented");
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std::string op_a = regs.GetRegisterAsFloat(instr.gpr8);
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std::string op_a = regs.GetRegisterAsFloat(instr.gpr8);
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std::string op_b = instr.ffma.negate_b ? "-" : "";
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std::string op_b = instr.ffma.negate_b ? "-" : "";
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std::string op_c = instr.ffma.negate_c ? "-" : "";
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std::string op_c = instr.ffma.negate_c ? "-" : "";
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@ -1051,7 +1079,7 @@ private:
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case OpCode::Type::Conversion: {
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case OpCode::Type::Conversion: {
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ASSERT_MSG(instr.conversion.size == Register::Size::Word, "Unimplemented");
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ASSERT_MSG(instr.conversion.size == Register::Size::Word, "Unimplemented");
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ASSERT_MSG(!instr.conversion.negate_a, "Unimplemented");
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ASSERT_MSG(!instr.conversion.negate_a, "Unimplemented");
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ASSERT_MSG(!instr.conversion.saturate_a, "Unimplemented");
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ASSERT_MSG(!instr.saturate_a, "Unimplemented");
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switch (opcode->GetId()) {
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switch (opcode->GetId()) {
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case OpCode::Id::I2I_R: {
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case OpCode::Id::I2I_R: {
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@ -1081,6 +1109,8 @@ private:
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break;
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break;
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}
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}
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case OpCode::Id::F2F_R: {
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case OpCode::Id::F2F_R: {
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ASSERT_MSG(!instr.saturate_a, "Unimplemented");
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std::string op_a = regs.GetRegisterAsFloat(instr.gpr20);
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std::string op_a = regs.GetRegisterAsFloat(instr.gpr20);
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switch (instr.conversion.f2f.rounding) {
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switch (instr.conversion.f2f.rounding) {
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@ -1198,8 +1228,8 @@ private:
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const std::string op_b = regs.GetRegisterAsFloat(instr.gpr8.Value() + 1);
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const std::string op_b = regs.GetRegisterAsFloat(instr.gpr8.Value() + 1);
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const std::string sampler = GetSampler(instr.sampler);
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const std::string sampler = GetSampler(instr.sampler);
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const std::string coord = "vec2 coords = vec2(" + op_a + ", " + op_b + ");";
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const std::string coord = "vec2 coords = vec2(" + op_a + ", " + op_b + ");";
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// Add an extra scope and declare the texture coords inside to prevent overwriting
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// Add an extra scope and declare the texture coords inside to prevent
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// them in case they are used as outputs of the texs instruction.
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// overwriting them in case they are used as outputs of the texs instruction.
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shader.AddLine("{");
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shader.AddLine("{");
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++shader.scope;
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++shader.scope;
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shader.AddLine(coord);
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shader.AddLine(coord);
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@ -1230,8 +1260,8 @@ private:
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shader.AddLine(coord);
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shader.AddLine(coord);
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const std::string texture = "texture(" + sampler + ", coords)";
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const std::string texture = "texture(" + sampler + ", coords)";
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// TEXS has two destination registers. RG goes into gpr0+0 and gpr0+1, and BA goes
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// TEXS has two destination registers. RG goes into gpr0+0 and gpr0+1, and BA
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// into gpr28+0 and gpr28+1
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// goes into gpr28+0 and gpr28+1
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size_t offset{};
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size_t offset{};
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for (const auto& dest : {instr.gpr0.Value(), instr.gpr28.Value()}) {
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for (const auto& dest : {instr.gpr0.Value(), instr.gpr28.Value()}) {
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@ -1412,8 +1442,8 @@ private:
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shader.AddLine("return true;");
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shader.AddLine("return true;");
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if (instr.pred.pred_index == static_cast<u64>(Pred::UnusedIndex)) {
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if (instr.pred.pred_index == static_cast<u64>(Pred::UnusedIndex)) {
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// If this is an unconditional exit then just end processing here, otherwise we
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// If this is an unconditional exit then just end processing here, otherwise
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// have to account for the possibility of the condition not being met, so
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// we have to account for the possibility of the condition not being met, so
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// continue processing the next instruction.
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// continue processing the next instruction.
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offset = PROGRAM_END - 1;
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offset = PROGRAM_END - 1;
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}
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}
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