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Merge pull request #1624 from JayFoxRox/buffer-allow-write
Implement buffer-write allow registers
This commit is contained in:
commit
069e040500
@ -578,7 +578,17 @@ struct Regs {
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}
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}
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struct {
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struct {
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INSERT_PADDING_WORDS(0x6);
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INSERT_PADDING_WORDS(0x3);
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union {
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BitField<0, 4, u32> allow_color_write; // 0 = disable, else enable
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};
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INSERT_PADDING_WORDS(0x1);
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union {
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BitField<0, 2, u32> allow_depth_stencil_write; // 0 = disable, else enable
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};
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DepthFormat depth_format; // TODO: Should be a BitField!
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DepthFormat depth_format; // TODO: Should be a BitField!
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BitField<16, 3, ColorFormat> color_format;
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BitField<16, 3, ColorFormat> color_format;
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@ -809,6 +809,7 @@ static void ProcessTriangleInternal(const Shader::OutputVertex& v0,
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auto UpdateStencil = [stencil_test, x, y, &old_stencil](Pica::Regs::StencilAction action) {
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auto UpdateStencil = [stencil_test, x, y, &old_stencil](Pica::Regs::StencilAction action) {
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u8 new_stencil = PerformStencilAction(action, old_stencil, stencil_test.reference_value);
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u8 new_stencil = PerformStencilAction(action, old_stencil, stencil_test.reference_value);
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if (g_state.regs.framebuffer.allow_depth_stencil_write != 0)
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SetStencil(x >> 4, y >> 4, (new_stencil & stencil_test.write_mask) | (old_stencil & ~stencil_test.write_mask));
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SetStencil(x >> 4, y >> 4, (new_stencil & stencil_test.write_mask) | (old_stencil & ~stencil_test.write_mask));
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};
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};
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@ -909,7 +910,7 @@ static void ProcessTriangleInternal(const Shader::OutputVertex& v0,
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}
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}
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}
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}
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if (output_merger.depth_write_enable)
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if (regs.framebuffer.allow_depth_stencil_write != 0 && output_merger.depth_write_enable)
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SetDepth(x >> 4, y >> 4, z);
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SetDepth(x >> 4, y >> 4, z);
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// The stencil depth_pass action is executed even if depth testing is disabled
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// The stencil depth_pass action is executed even if depth testing is disabled
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@ -1133,6 +1134,7 @@ static void ProcessTriangleInternal(const Shader::OutputVertex& v0,
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output_merger.alpha_enable ? blend_output.a() : dest.a()
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output_merger.alpha_enable ? blend_output.a() : dest.a()
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};
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};
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if (regs.framebuffer.allow_color_write != 0)
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DrawPixel(x >> 4, y >> 4, result);
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DrawPixel(x >> 4, y >> 4, result);
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}
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}
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}
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}
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@ -153,6 +153,9 @@ void RasterizerOpenGL::Reset() {
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SyncLogicOp();
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SyncLogicOp();
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SyncStencilTest();
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SyncStencilTest();
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SyncDepthTest();
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SyncDepthTest();
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SyncColorWriteMask();
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SyncStencilWriteMask();
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SyncDepthWriteMask();
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SetShader();
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SetShader();
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@ -268,15 +271,36 @@ void RasterizerOpenGL::NotifyPicaRegisterChanged(u32 id) {
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state.draw.shader_dirty = true;
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state.draw.shader_dirty = true;
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break;
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break;
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// Stencil test
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// Sync GL stencil test + stencil write mask
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// (Pica stencil test function register also contains a stencil write mask)
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case PICA_REG_INDEX(output_merger.stencil_test.raw_func):
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case PICA_REG_INDEX(output_merger.stencil_test.raw_func):
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SyncStencilTest();
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SyncStencilWriteMask();
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break;
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case PICA_REG_INDEX(output_merger.stencil_test.raw_op):
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case PICA_REG_INDEX(output_merger.stencil_test.raw_op):
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case PICA_REG_INDEX(framebuffer.depth_format):
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SyncStencilTest();
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SyncStencilTest();
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break;
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break;
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// Depth test
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// Sync GL depth test + depth and color write mask
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// (Pica depth test function register also contains a depth and color write mask)
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case PICA_REG_INDEX(output_merger.depth_test_enable):
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case PICA_REG_INDEX(output_merger.depth_test_enable):
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SyncDepthTest();
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SyncDepthTest();
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SyncDepthWriteMask();
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SyncColorWriteMask();
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break;
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// Sync GL depth and stencil write mask
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// (This is a dedicated combined depth / stencil write-enable register)
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case PICA_REG_INDEX(framebuffer.allow_depth_stencil_write):
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SyncDepthWriteMask();
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SyncStencilWriteMask();
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break;
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// Sync GL color write mask
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// (This is a dedicated color write-enable register)
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case PICA_REG_INDEX(framebuffer.allow_color_write):
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SyncColorWriteMask();
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break;
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break;
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// Logic op
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// Logic op
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@ -880,13 +904,39 @@ void RasterizerOpenGL::SyncLogicOp() {
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state.logic_op = PicaToGL::LogicOp(Pica::g_state.regs.output_merger.logic_op);
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state.logic_op = PicaToGL::LogicOp(Pica::g_state.regs.output_merger.logic_op);
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}
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}
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void RasterizerOpenGL::SyncColorWriteMask() {
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const auto& regs = Pica::g_state.regs;
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auto IsColorWriteEnabled = [&](u32 value) {
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return (regs.framebuffer.allow_color_write != 0 && value != 0) ? GL_TRUE : GL_FALSE;
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};
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state.color_mask.red_enabled = IsColorWriteEnabled(regs.output_merger.red_enable);
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state.color_mask.green_enabled = IsColorWriteEnabled(regs.output_merger.green_enable);
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state.color_mask.blue_enabled = IsColorWriteEnabled(regs.output_merger.blue_enable);
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state.color_mask.alpha_enabled = IsColorWriteEnabled(regs.output_merger.alpha_enable);
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}
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void RasterizerOpenGL::SyncStencilWriteMask() {
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const auto& regs = Pica::g_state.regs;
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state.stencil.write_mask = (regs.framebuffer.allow_depth_stencil_write != 0)
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? static_cast<GLuint>(regs.output_merger.stencil_test.write_mask)
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: 0;
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}
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void RasterizerOpenGL::SyncDepthWriteMask() {
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const auto& regs = Pica::g_state.regs;
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state.depth.write_mask = (regs.framebuffer.allow_depth_stencil_write != 0 && regs.output_merger.depth_write_enable)
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? GL_TRUE
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: GL_FALSE;
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}
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void RasterizerOpenGL::SyncStencilTest() {
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void RasterizerOpenGL::SyncStencilTest() {
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const auto& regs = Pica::g_state.regs;
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const auto& regs = Pica::g_state.regs;
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state.stencil.test_enabled = regs.output_merger.stencil_test.enable && regs.framebuffer.depth_format == Pica::Regs::DepthFormat::D24S8;
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state.stencil.test_enabled = regs.output_merger.stencil_test.enable && regs.framebuffer.depth_format == Pica::Regs::DepthFormat::D24S8;
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state.stencil.test_func = PicaToGL::CompareFunc(regs.output_merger.stencil_test.func);
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state.stencil.test_func = PicaToGL::CompareFunc(regs.output_merger.stencil_test.func);
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state.stencil.test_ref = regs.output_merger.stencil_test.reference_value;
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state.stencil.test_ref = regs.output_merger.stencil_test.reference_value;
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state.stencil.test_mask = regs.output_merger.stencil_test.input_mask;
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state.stencil.test_mask = regs.output_merger.stencil_test.input_mask;
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state.stencil.write_mask = regs.output_merger.stencil_test.write_mask;
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state.stencil.action_stencil_fail = PicaToGL::StencilOp(regs.output_merger.stencil_test.action_stencil_fail);
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state.stencil.action_stencil_fail = PicaToGL::StencilOp(regs.output_merger.stencil_test.action_stencil_fail);
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state.stencil.action_depth_fail = PicaToGL::StencilOp(regs.output_merger.stencil_test.action_depth_fail);
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state.stencil.action_depth_fail = PicaToGL::StencilOp(regs.output_merger.stencil_test.action_depth_fail);
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state.stencil.action_depth_pass = PicaToGL::StencilOp(regs.output_merger.stencil_test.action_depth_pass);
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state.stencil.action_depth_pass = PicaToGL::StencilOp(regs.output_merger.stencil_test.action_depth_pass);
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@ -898,11 +948,6 @@ void RasterizerOpenGL::SyncDepthTest() {
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regs.output_merger.depth_write_enable == 1;
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regs.output_merger.depth_write_enable == 1;
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state.depth.test_func = regs.output_merger.depth_test_enable == 1 ?
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state.depth.test_func = regs.output_merger.depth_test_enable == 1 ?
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PicaToGL::CompareFunc(regs.output_merger.depth_test_func) : GL_ALWAYS;
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PicaToGL::CompareFunc(regs.output_merger.depth_test_func) : GL_ALWAYS;
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state.color_mask.red_enabled = regs.output_merger.red_enable;
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state.color_mask.green_enabled = regs.output_merger.green_enable;
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state.color_mask.blue_enabled = regs.output_merger.blue_enable;
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state.color_mask.alpha_enabled = regs.output_merger.alpha_enable;
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state.depth.write_mask = regs.output_merger.depth_write_enable ? GL_TRUE : GL_FALSE;
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}
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}
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void RasterizerOpenGL::SyncCombinerColor() {
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void RasterizerOpenGL::SyncCombinerColor() {
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@ -344,6 +344,15 @@ private:
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/// Syncs the logic op states to match the PICA register
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/// Syncs the logic op states to match the PICA register
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void SyncLogicOp();
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void SyncLogicOp();
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/// Syncs the color write mask to match the PICA register state
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void SyncColorWriteMask();
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/// Syncs the stencil write mask to match the PICA register state
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void SyncStencilWriteMask();
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/// Syncs the depth write mask to match the PICA register state
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void SyncDepthWriteMask();
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/// Syncs the stencil test states to match the PICA register
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/// Syncs the stencil test states to match the PICA register
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void SyncStencilTest();
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void SyncStencilTest();
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