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131 lines
3.7 KiB
C++
131 lines
3.7 KiB
C++
// Copyright 2014 Citra Emulator Project
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// Licensed under GPLv2
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// Refer to the license.txt file included.
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#pragma once
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#include <initializer_list>
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#include <map>
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#include "common/bit_field.h"
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#include "common/common_types.h"
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#include "common/register_set.h"
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namespace Pica {
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struct Regs {
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enum Id : u32 {
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ViewportSizeX = 0x41,
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ViewportInvSizeX = 0x42,
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ViewportSizeY = 0x43,
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ViewportInvSizeY = 0x44,
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ViewportCorner = 0x68,
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DepthBufferFormat = 0x116,
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ColorBufferFormat = 0x117,
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DepthBufferAddress = 0x11C,
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ColorBufferAddress = 0x11D,
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ColorBufferSize = 0x11E,
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VertexArrayBaseAddr = 0x200,
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VertexDescriptor = 0x201, // 0x202
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VertexAttributeOffset = 0x203, // 0x206,0x209,0x20C,0x20F,0x212,0x215,0x218,0x21B,0x21E,0x221,0x224
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VertexAttributeInfo0 = 0x204, // 0x207,0x20A,0x20D,0x210,0x213,0x216,0x219,0x21C,0x21F,0x222,0x225
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VertexAttributeInfo1 = 0x205, // 0x208,0x20B,0x20E,0x211,0x214,0x217,0x21A,0x21D,0x220,0x223,0x226
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NumIds = 0x300,
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};
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template<Id id>
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union Struct;
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};
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static inline Regs::Id VertexAttributeOffset(int n)
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{
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return static_cast<Regs::Id>(0x203 + 3*n);
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}
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static inline Regs::Id VertexAttributeInfo0(int n)
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{
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return static_cast<Regs::Id>(0x204 + 3*n);
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}
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static inline Regs::Id VertexAttributeInfo1(int n)
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{
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return static_cast<Regs::Id>(0x205 + 3*n);
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}
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union CommandHeader {
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CommandHeader(u32 h) : hex(h) {}
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u32 hex;
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BitField< 0, 16, Regs::Id> cmd_id;
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BitField<16, 4, u32> parameter_mask;
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BitField<20, 11, u32> extra_data_length;
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BitField<31, 1, u32> group_commands;
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};
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static std::map<Regs::Id, const char*> command_names = {
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{Regs::ViewportSizeX, "ViewportSizeX" },
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{Regs::ViewportInvSizeX, "ViewportInvSizeX" },
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{Regs::ViewportSizeY, "ViewportSizeY" },
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{Regs::ViewportInvSizeY, "ViewportInvSizeY" },
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{Regs::ViewportCorner, "ViewportCorner" },
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{Regs::DepthBufferFormat, "DepthBufferFormat" },
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{Regs::ColorBufferFormat, "ColorBufferFormat" },
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{Regs::DepthBufferAddress, "DepthBufferAddress" },
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{Regs::ColorBufferAddress, "ColorBufferAddress" },
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{Regs::ColorBufferSize, "ColorBufferSize" },
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};
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template<>
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union Regs::Struct<Regs::ViewportSizeX> {
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BitField<0, 24, u32> value;
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};
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template<>
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union Regs::Struct<Regs::ViewportSizeY> {
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BitField<0, 24, u32> value;
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};
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template<>
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union Regs::Struct<Regs::VertexDescriptor> {
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enum class Format : u64 {
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BYTE = 0,
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UBYTE = 1,
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SHORT = 2,
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FLOAT = 3,
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};
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BitField< 0, 2, Format> format0;
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BitField< 2, 2, u64> size0; // number of elements minus 1
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BitField< 4, 2, Format> format1;
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BitField< 6, 2, u64> size1;
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BitField< 8, 2, Format> format2;
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BitField<10, 2, u64> size2;
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BitField<12, 2, Format> format3;
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BitField<14, 2, u64> size3;
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BitField<16, 2, Format> format4;
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BitField<18, 2, u64> size4;
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BitField<20, 2, Format> format5;
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BitField<22, 2, u64> size5;
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BitField<24, 2, Format> format6;
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BitField<26, 2, u64> size6;
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BitField<28, 2, Format> format7;
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BitField<30, 2, u64> size7;
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BitField<32, 2, Format> format8;
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BitField<34, 2, u64> size8;
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BitField<36, 2, Format> format9;
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BitField<38, 2, u64> size9;
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BitField<40, 2, Format> format10;
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BitField<42, 2, u64> size10;
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BitField<44, 2, Format> format11;
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BitField<46, 2, u64> size11;
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BitField<48, 12, u64> attribute_mask;
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BitField<60, 4, u64> num_attributes; // number of total attributes minus 1
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};
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} // namespace
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