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115 lines
3.5 KiB
C++
115 lines
3.5 KiB
C++
// Copyright 2014 Citra Emulator Project
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// Licensed under GPLv2
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// Refer to the license.txt file included.
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#pragma once
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#include "common/common_types.h"
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namespace GPU {
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static const u32 kFrameCycles = 268123480 / 60; ///< 268MHz / 60 frames per second
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static const u32 kFrameTicks = kFrameCycles / 3; ///< Approximate number of instructions/frame
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struct Registers {
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enum Id : u32 {
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FramebufferTopLeft1 = 0x1EF00468, // Main LCD, first framebuffer for 3D left
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FramebufferTopLeft2 = 0x1EF0046C, // Main LCD, second framebuffer for 3D left
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FramebufferTopRight1 = 0x1EF00494, // Main LCD, first framebuffer for 3D right
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FramebufferTopRight2 = 0x1EF00498, // Main LCD, second framebuffer for 3D right
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FramebufferSubLeft1 = 0x1EF00568, // Sub LCD, first framebuffer
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FramebufferSubLeft2 = 0x1EF0056C, // Sub LCD, second framebuffer
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FramebufferSubRight1 = 0x1EF00594, // Sub LCD, unused first framebuffer
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FramebufferSubRight2 = 0x1EF00598, // Sub LCD, unused second framebuffer
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CommandListSize = 0x1EF018E0,
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CommandListAddress = 0x1EF018E8,
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ProcessCommandList = 0x1EF018F0,
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};
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u32 framebuffer_top_left_1;
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u32 framebuffer_top_left_2;
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u32 framebuffer_top_right_1;
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u32 framebuffer_top_right_2;
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u32 framebuffer_sub_left_1;
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u32 framebuffer_sub_left_2;
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u32 framebuffer_sub_right_1;
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u32 framebuffer_sub_right_2;
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u32 command_list_size;
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u32 command_list_address;
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u32 command_processing_enabled;
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};
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extern Registers g_regs;
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enum {
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TOP_ASPECT_X = 0x5,
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TOP_ASPECT_Y = 0x3,
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TOP_HEIGHT = 240,
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TOP_WIDTH = 400,
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BOTTOM_WIDTH = 320,
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// Physical addresses in FCRAM used by ARM9 applications - these are correct for real hardware
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PADDR_FRAMEBUFFER_SEL = 0x20184E59,
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PADDR_TOP_LEFT_FRAME1 = 0x20184E60,
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PADDR_TOP_LEFT_FRAME2 = 0x201CB370,
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PADDR_TOP_RIGHT_FRAME1 = 0x20282160,
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PADDR_TOP_RIGHT_FRAME2 = 0x202C8670,
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PADDR_SUB_FRAME1 = 0x202118E0,
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PADDR_SUB_FRAME2 = 0x20249CF0,
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// Physical addresses in VRAM - I'm not sure how these are actually allocated (so not real)
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PADDR_VRAM_FRAMEBUFFER_SEL = 0x18184E59,
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PADDR_VRAM_TOP_LEFT_FRAME1 = 0x18184E60,
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PADDR_VRAM_TOP_LEFT_FRAME2 = 0x181CB370,
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PADDR_VRAM_TOP_RIGHT_FRAME1 = 0x18282160,
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PADDR_VRAM_TOP_RIGHT_FRAME2 = 0x182C8670,
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PADDR_VRAM_SUB_FRAME1 = 0x182118E0,
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PADDR_VRAM_SUB_FRAME2 = 0x18249CF0,
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};
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/// Framebuffer location
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enum FramebufferLocation {
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FRAMEBUFFER_LOCATION_UNKNOWN, ///< Framebuffer location is unknown
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FRAMEBUFFER_LOCATION_FCRAM, ///< Framebuffer is in the GSP heap
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FRAMEBUFFER_LOCATION_VRAM, ///< Framebuffer is in VRAM
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};
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/**
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* Sets whether the framebuffers are in the GSP heap (FCRAM) or VRAM
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* @param
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*/
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void SetFramebufferLocation(const FramebufferLocation mode);
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/**
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* Gets a read-only pointer to a framebuffer in memory
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* @param address Physical address of framebuffer
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* @return Returns const pointer to raw framebuffer
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*/
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const u8* GetFramebufferPointer(const u32 address);
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/**
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* Gets the location of the framebuffers
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*/
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const FramebufferLocation GetFramebufferLocation();
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template <typename T>
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inline void Read(T &var, const u32 addr);
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template <typename T>
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inline void Write(u32 addr, const T data);
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/// Update hardware
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void Update();
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/// Initialize hardware
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void Init();
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/// Shutdown hardware
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void Shutdown();
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} // namespace
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