mirror of https://github.com/citra-emu/citra.git
345 lines
10 KiB
C++
345 lines
10 KiB
C++
// Copyright 2014 Citra Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#pragma once
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#include <cstddef>
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#include <type_traits>
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#include <boost/serialization/access.hpp>
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#include <boost/serialization/binary_object.hpp>
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#include "common/assert.h"
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#include "common/bit_field.h"
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#include "common/common_funcs.h"
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#include "common/common_types.h"
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#include "core/core_timing.h"
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namespace Memory {
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class MemorySystem;
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}
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namespace GPU {
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// Measured on hardware to be 2240568 timer cycles or 4481136 ARM11 cycles
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constexpr u64 frame_ticks = 4481136ull;
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// Refresh rate defined by ratio of ARM11 frequency to ARM11 ticks per frame
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// (268,111,856) / (4,481,136) = 59.83122493939037Hz
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constexpr double SCREEN_REFRESH_RATE = BASE_CLOCK_RATE_ARM11 / static_cast<double>(frame_ticks);
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// Returns index corresponding to the Regs member labeled by field_name
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#define GPU_REG_INDEX(field_name) (offsetof(GPU::Regs, field_name) / sizeof(u32))
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// Returns index corresponding to the Regs::FramebufferConfig labeled by field_name
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// screen_id is a subscript for Regs::framebuffer_config
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#define GPU_FRAMEBUFFER_REG_INDEX(screen_id, field_name) \
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((offsetof(GPU::Regs, framebuffer_config) + \
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sizeof(GPU::Regs::FramebufferConfig) * (screen_id) + \
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offsetof(GPU::Regs::FramebufferConfig, field_name)) / \
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sizeof(u32))
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// MMIO region 0x1EFxxxxx
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struct Regs {
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// helper macro to make sure the defined structures are of the expected size.
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#define ASSERT_MEMBER_SIZE(name, size_in_bytes) \
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static_assert(sizeof(name) == size_in_bytes, \
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"Structure size and register block length don't match")
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// Components are laid out in reverse byte order, most significant bits first.
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enum class PixelFormat : u32 {
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RGBA8 = 0,
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RGB8 = 1,
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RGB565 = 2,
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RGB5A1 = 3,
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RGBA4 = 4,
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};
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/**
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* Returns the number of bytes per pixel.
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*/
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static int BytesPerPixel(PixelFormat format) {
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switch (format) {
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case PixelFormat::RGBA8:
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return 4;
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case PixelFormat::RGB8:
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return 3;
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case PixelFormat::RGB565:
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case PixelFormat::RGB5A1:
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case PixelFormat::RGBA4:
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return 2;
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default:
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UNREACHABLE();
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}
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return 0;
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}
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INSERT_PADDING_WORDS(0x4);
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struct MemoryFillConfig {
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u32 address_start;
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u32 address_end;
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union {
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u32 value_32bit;
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BitField<0, 16, u32> value_16bit;
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// TODO: Verify component order
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BitField<0, 8, u32> value_24bit_r;
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BitField<8, 8, u32> value_24bit_g;
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BitField<16, 8, u32> value_24bit_b;
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};
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union {
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u32 control;
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// Setting this field to 1 triggers the memory fill.
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// This field also acts as a status flag, and gets reset to 0 upon completion.
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BitField<0, 1, u32> trigger;
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// Set to 1 upon completion.
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BitField<1, 1, u32> finished;
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// If both of these bits are unset, then it will fill the memory with a 16 bit value
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// 1: fill with 24-bit wide values
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BitField<8, 1, u32> fill_24bit;
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// 1: fill with 32-bit wide values
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BitField<9, 1, u32> fill_32bit;
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};
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inline u32 GetStartAddress() const {
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return DecodeAddressRegister(address_start);
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}
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inline u32 GetEndAddress() const {
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return DecodeAddressRegister(address_end);
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}
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inline std::string DebugName() const {
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return fmt::format("from {:#X} to {:#X} with {}-bit value {:#X}", GetStartAddress(),
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GetEndAddress(), fill_32bit ? "32" : (fill_24bit ? "24" : "16"),
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value_32bit);
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}
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} memory_fill_config[2];
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ASSERT_MEMBER_SIZE(memory_fill_config[0], 0x10);
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INSERT_PADDING_WORDS(0x10b);
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struct FramebufferConfig {
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union {
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u32 size;
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BitField<0, 16, u32> width;
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BitField<16, 16, u32> height;
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};
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INSERT_PADDING_WORDS(0x2);
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u32 address_left1;
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u32 address_left2;
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union {
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u32 format;
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BitField<0, 3, PixelFormat> color_format;
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};
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INSERT_PADDING_WORDS(0x1);
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union {
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u32 active_fb;
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// 0: Use parameters ending with "1"
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// 1: Use parameters ending with "2"
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BitField<0, 1, u32> second_fb_active;
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};
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INSERT_PADDING_WORDS(0x5);
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// Distance between two pixel rows, in bytes
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u32 stride;
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u32 address_right1;
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u32 address_right2;
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INSERT_PADDING_WORDS(0x30);
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} framebuffer_config[2];
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ASSERT_MEMBER_SIZE(framebuffer_config[0], 0x100);
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INSERT_PADDING_WORDS(0x169);
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struct DisplayTransferConfig {
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u32 input_address;
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u32 output_address;
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inline u32 GetPhysicalInputAddress() const {
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return DecodeAddressRegister(input_address);
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}
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inline u32 GetPhysicalOutputAddress() const {
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return DecodeAddressRegister(output_address);
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}
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inline std::string DebugName() const noexcept {
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return fmt::format("from {:#x} to {:#x} with {} scaling and stride {}, width {}",
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GetPhysicalInputAddress(), GetPhysicalOutputAddress(),
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scaling == NoScale ? "no" : (scaling == ScaleX ? "X" : "XY"),
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input_width.Value(), output_width.Value());
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}
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union {
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u32 output_size;
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BitField<0, 16, u32> output_width;
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BitField<16, 16, u32> output_height;
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};
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union {
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u32 input_size;
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BitField<0, 16, u32> input_width;
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BitField<16, 16, u32> input_height;
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};
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enum ScalingMode : u32 {
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NoScale = 0, // Doesn't scale the image
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ScaleX = 1, // Downscales the image in half in the X axis and applies a box filter
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ScaleXY =
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2, // Downscales the image in half in both the X and Y axes and applies a box filter
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};
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union {
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u32 flags;
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BitField<0, 1, u32> flip_vertically; // flips input data vertically
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BitField<1, 1, u32> input_linear; // Converts from linear to tiled format
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BitField<2, 1, u32> crop_input_lines;
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BitField<3, 1, u32> is_texture_copy; // Copies the data without performing any
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// processing and respecting texture copy fields
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BitField<5, 1, u32> dont_swizzle;
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BitField<8, 3, PixelFormat> input_format;
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BitField<12, 3, PixelFormat> output_format;
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/// Uses some kind of 32x32 block swizzling mode, instead of the usual 8x8 one.
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BitField<16, 1, u32> block_32; // TODO(yuriks): unimplemented
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BitField<24, 2, ScalingMode> scaling; // Determines the scaling mode of the transfer
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};
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INSERT_PADDING_WORDS(0x1);
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// it seems that writing to this field triggers the display transfer
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u32 trigger;
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INSERT_PADDING_WORDS(0x1);
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struct {
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u32 size; // The lower 4 bits are ignored
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union {
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u32 input_size;
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BitField<0, 16, u32> input_width;
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BitField<16, 16, u32> input_gap;
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};
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union {
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u32 output_size;
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BitField<0, 16, u32> output_width;
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BitField<16, 16, u32> output_gap;
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};
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} texture_copy;
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} display_transfer_config;
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ASSERT_MEMBER_SIZE(display_transfer_config, 0x2c);
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INSERT_PADDING_WORDS(0x32D);
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struct {
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// command list size (in bytes)
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u32 size;
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INSERT_PADDING_WORDS(0x1);
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// command list address
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u32 address;
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INSERT_PADDING_WORDS(0x1);
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// it seems that writing to this field triggers command list processing
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u32 trigger;
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inline u32 GetPhysicalAddress() const {
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return DecodeAddressRegister(address);
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}
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} command_processor_config;
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ASSERT_MEMBER_SIZE(command_processor_config, 0x14);
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INSERT_PADDING_WORDS(0x9c3);
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static constexpr std::size_t NumIds() {
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return sizeof(Regs) / sizeof(u32);
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}
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const u32& operator[](int index) const {
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const u32* content = reinterpret_cast<const u32*>(this);
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return content[index];
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}
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u32& operator[](int index) {
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u32* content = reinterpret_cast<u32*>(this);
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return content[index];
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}
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#undef ASSERT_MEMBER_SIZE
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private:
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/*
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* Most physical addresses which GPU registers refer to are 8-byte aligned.
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* This function should be used to get the address from a raw register value.
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*/
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static inline u32 DecodeAddressRegister(u32 register_value) {
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return register_value * 8;
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}
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template <class Archive>
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void serialize(Archive& ar, const unsigned int) {
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ar& boost::serialization::make_binary_object(this, sizeof(Regs));
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}
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friend class boost::serialization::access;
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};
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static_assert(std::is_standard_layout<Regs>::value, "Structure does not use standard layout");
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#define ASSERT_REG_POSITION(field_name, position) \
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static_assert(offsetof(Regs, field_name) == position * 4, \
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"Field " #field_name " has invalid position")
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ASSERT_REG_POSITION(memory_fill_config[0], 0x00004);
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ASSERT_REG_POSITION(memory_fill_config[1], 0x00008);
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ASSERT_REG_POSITION(framebuffer_config[0], 0x00117);
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ASSERT_REG_POSITION(framebuffer_config[1], 0x00157);
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ASSERT_REG_POSITION(display_transfer_config, 0x00300);
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ASSERT_REG_POSITION(command_processor_config, 0x00638);
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#undef ASSERT_REG_POSITION
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// The total number of registers is chosen arbitrarily, but let's make sure it's not some odd value
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// anyway.
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static_assert(sizeof(Regs) == 0x1000 * sizeof(u32), "Invalid total size of register set");
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extern Regs g_regs;
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template <typename T>
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void Read(T& var, const u32 addr);
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template <typename T>
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void Write(u32 addr, const T data);
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/// Initialize hardware
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void Init(Memory::MemorySystem& memory);
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/// Shutdown hardware
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void Shutdown();
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} // namespace GPU
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