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https://github.com/citra-emu/citra.git
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JitX64: Data Processing: Implement shift-by-immediate (_reg) instructions
This commit is contained in:
MerryMage
parent
1e57d34c0b
commit
fc1f126ec5
@ -71,13 +71,13 @@ static const std::array<Instruction, 27> thumb_instruction_table = { {
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Register Rd = bits<0, 2>(instruction);
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switch (opcode) {
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case 0: // LSL <Rd>, <Rm>, #<imm5>
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v->MOV_reg(0xE, /*S=*/true, Rd, imm5, 0b000, Rm);
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v->MOV_reg(0xE, /*S=*/true, Rd, imm5, 0b00, Rm);
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break;
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case 1: // LSR <Rd>, <Rm>, #<imm5>
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v->MOV_reg(0xE, /*S=*/true, Rd, imm5, 0b010, Rm);
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v->MOV_reg(0xE, /*S=*/true, Rd, imm5, 0b01, Rm);
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break;
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case 2: // ASR <Rd>, <Rm>, #<imm5>
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v->MOV_reg(0xE, /*S=*/true, Rd, imm5, 0b100, Rm);
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v->MOV_reg(0xE, /*S=*/true, Rd, imm5, 0b10, Rm);
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break;
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default:
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UNREACHABLE();
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@ -27,11 +27,11 @@ void JitX64::CompileDataProcessingHelper(ArmReg Rn_index, ArmReg Rd_index, std::
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} else {
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X64Reg Rd = reg_alloc.BindArmForWrite(Rd_index);
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OpArg Rn = reg_alloc.LockArmForRead(Rn_index);
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code->MOV(32, R(Rd), Rn);
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reg_alloc.UnlockArm(Rn_index);
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body(Rd);
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reg_alloc.UnlockArm(Rn_index);
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reg_alloc.UnlockArm(Rd_index);
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}
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}
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@ -61,6 +61,77 @@ void JitX64::CompileDataProcessingHelper_Reverse(ArmReg Rn_index, ArmReg Rd_inde
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}
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}
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X64Reg JitX64::CompileDataProcessingHelper_reg(ArmImm5 imm5, ShiftType shift, ArmReg Rm_index, bool do_shifter_carry_out) {
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// We directly put shifter_carry_out into MJitStateCFlag()
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X64Reg tmp = reg_alloc.AllocTemp();
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if (Rm_index != 15) {
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OpArg Rm = reg_alloc.LockArmForRead(Rm_index);
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code->MOV(32, R(tmp), Rm);
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reg_alloc.UnlockArm(Rm_index);
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} else {
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code->MOV(32, R(tmp), Imm32(GetReg15Value()));
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}
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if (do_shifter_carry_out) {
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cond_manager.FlagsDirty();
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}
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switch (shift) {
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case 0b00: // Logical shift left by immediate
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if (imm5 != 0) {
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code->SHL(32, R(tmp), Imm8(imm5));
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if (do_shifter_carry_out) {
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code->SETcc(CC_C, MJitStateCFlag());
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}
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}
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return tmp;
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case 0b01: // Logical shift right by immediate
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if (imm5 == 0) {
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if (do_shifter_carry_out) {
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code->BT(32, R(tmp), Imm8(31));
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code->SETcc(CC_C, MJitStateCFlag());
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}
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code->MOV(64, R(tmp), Imm32(0));
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} else {
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code->SHR(32, R(tmp), Imm8(imm5));
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if (do_shifter_carry_out) {
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code->SETcc(CC_C, MJitStateCFlag());
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}
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}
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return tmp;
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case 0b10: // Arithmetic shift right by immediate
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if (imm5 == 0) {
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if (do_shifter_carry_out) {
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code->BT(32, R(tmp), Imm8(31));
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code->SETcc(CC_C, MJitStateCFlag());
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}
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code->SAR(32, R(tmp), Imm8(31));
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} else {
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code->SAR(32, R(tmp), Imm8(imm5));
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if (do_shifter_carry_out) {
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code->SETcc(CC_C, MJitStateCFlag());
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}
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}
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return tmp;
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case 0b11: // Rotate right by immediate
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if (imm5 == 0) { //RRX
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code->BT(8, MJitStateCFlag(), Imm8(0));
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code->RCR(32, R(tmp), Imm8(1));
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if (do_shifter_carry_out)
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code->SETcc(CC_C, MJitStateCFlag());
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} else {
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code->ROR(32, R(tmp), Imm8(imm5));
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if (do_shifter_carry_out)
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code->SETcc(CC_C, MJitStateCFlag());
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}
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return tmp;
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}
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UNREACHABLE();
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}
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void JitX64::ADC_imm(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, int rotate, ArmImm8 imm8) {
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cond_manager.CompileCond((ConditionCode)cond);
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@ -81,6 +152,28 @@ void JitX64::ADC_imm(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, int ro
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}
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}
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void JitX64::ADC_reg(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmImm5 imm5, ShiftType shift, ArmReg Rm_index) {
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cond_manager.CompileCond((ConditionCode)cond);
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Gen::X64Reg tmp = CompileDataProcessingHelper_reg(imm5, shift, Rm_index, false);
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CompileDataProcessingHelper(Rn_index, Rd_index, [&](X64Reg Rd) {
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code->BT(32, MJitStateCFlag(), Imm8(0));
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code->ADC(32, R(Rd), R(tmp));
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});
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reg_alloc.UnlockTemp(tmp);
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if (S) {
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UpdateFlagsZVCN();
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}
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current.arm_pc += GetInstSize();
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if (Rd_index == 15) {
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CompileReturnToDispatch();
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}
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}
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void JitX64::ADD_imm(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, int rotate, ArmImm8 imm8) {
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cond_manager.CompileCond((ConditionCode)cond);
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@ -100,6 +193,27 @@ void JitX64::ADD_imm(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, int ro
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}
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}
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void JitX64::ADD_reg(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmImm5 imm5, ShiftType shift, ArmReg Rm_index) {
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cond_manager.CompileCond((ConditionCode)cond);
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Gen::X64Reg tmp = CompileDataProcessingHelper_reg(imm5, shift, Rm_index, false);
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CompileDataProcessingHelper(Rn_index, Rd_index, [&](X64Reg Rd) {
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code->ADD(32, R(Rd), R(tmp));
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});
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reg_alloc.UnlockTemp(tmp);
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if (S) {
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UpdateFlagsZVCN();
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}
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current.arm_pc += GetInstSize();
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if (Rd_index == 15) {
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CompileReturnToDispatch();
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}
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}
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void JitX64::AND_imm(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, int rotate, ArmImm8 imm8) {
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cond_manager.CompileCond((ConditionCode)cond);
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@ -122,6 +236,27 @@ void JitX64::AND_imm(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, int ro
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}
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}
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void JitX64::AND_reg(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmImm5 imm5, ShiftType shift, ArmReg Rm_index) {
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cond_manager.CompileCond((ConditionCode)cond);
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Gen::X64Reg tmp = CompileDataProcessingHelper_reg(imm5, shift, Rm_index, S);
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CompileDataProcessingHelper(Rn_index, Rd_index, [&](X64Reg Rd) {
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code->AND(32, R(Rd), R(tmp));
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});
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reg_alloc.UnlockTemp(tmp);
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if (S) {
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UpdateFlagsZN();
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}
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current.arm_pc += GetInstSize();
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if (Rd_index == 15) {
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CompileReturnToDispatch();
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}
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}
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void JitX64::BIC_imm(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, int rotate, ArmImm8 imm8) {
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cond_manager.CompileCond((ConditionCode)cond);
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@ -144,8 +279,119 @@ void JitX64::BIC_imm(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, int ro
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}
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}
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void JitX64::CMN_imm(Cond cond, ArmReg Rn_index, int rotate, ArmImm8 imm8) { CompileInterpretInstruction(); }
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void JitX64::CMP_imm(Cond cond, ArmReg Rn_index, int rotate, ArmImm8 imm8) { CompileInterpretInstruction(); }
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void JitX64::BIC_reg(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmImm5 imm5, ShiftType shift, ArmReg Rm_index) {
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cond_manager.CompileCond((ConditionCode)cond);
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Gen::X64Reg tmp = CompileDataProcessingHelper_reg(imm5, shift, Rm_index, S);
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CompileDataProcessingHelper(Rn_index, Rd_index, [&](X64Reg Rd) {
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// TODO: Use ANDN instead.
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code->NOT(32, R(tmp));
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code->AND(32, R(Rd), R(tmp));
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});
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reg_alloc.UnlockTemp(tmp);
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if (S) {
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UpdateFlagsZN();
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}
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current.arm_pc += GetInstSize();
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if (Rd_index == 15) {
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CompileReturnToDispatch();
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}
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}
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void JitX64::CMN_imm(Cond cond, ArmReg Rn_index, int rotate, ArmImm8 imm8) {
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cond_manager.CompileCond((ConditionCode)cond);
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u32 immediate = rotr(imm8, rotate * 2);
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X64Reg tmp = reg_alloc.AllocTemp();
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if (Rn_index != 15) {
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OpArg Rn = reg_alloc.LockArmForRead(Rn_index);
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code->MOV(32, R(tmp), Rn);
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reg_alloc.UnlockArm(Rn_index);
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} else {
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code->MOV(32, R(tmp), Imm32(GetReg15Value()));
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}
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code->ADD(32, R(tmp), Imm32(immediate));
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reg_alloc.UnlockTemp(tmp);
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UpdateFlagsZVCN();
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current.arm_pc += GetInstSize();
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}
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void JitX64::CMN_reg(Cond cond, ArmReg Rn_index, ArmImm5 imm5, ShiftType shift, ArmReg Rm_index) {
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cond_manager.CompileCond((ConditionCode)cond);
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Gen::X64Reg tmp = CompileDataProcessingHelper_reg(imm5, shift, Rm_index, false);
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if (Rn_index != 15) {
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OpArg Rn = reg_alloc.LockArmForRead(Rn_index);
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code->ADD(32, R(tmp), Rn);
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reg_alloc.UnlockArm(Rn_index);
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} else {
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code->ADD(32, R(tmp), Imm32(GetReg15Value()));
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}
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reg_alloc.UnlockTemp(tmp);
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UpdateFlagsZVCN();
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current.arm_pc += GetInstSize();
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}
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void JitX64::CMP_imm(Cond cond, ArmReg Rn_index, int rotate, ArmImm8 imm8) {
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cond_manager.CompileCond((ConditionCode)cond);
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u32 immediate = rotr(imm8, rotate * 2);
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if (Rn_index != 15) {
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OpArg Rn = reg_alloc.LockArmForRead(Rn_index);
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code->CMP(32, Rn, Imm32(immediate));
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reg_alloc.UnlockArm(Rn_index);
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} else {
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// TODO: Optimize this
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X64Reg tmp = reg_alloc.AllocTemp();
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code->MOV(32, R(tmp), Imm32(GetReg15Value()));
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code->CMP(32, R(tmp), Imm32(immediate));
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reg_alloc.UnlockTemp(tmp);
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}
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UpdateFlagsC_complement();
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UpdateFlagsZVN();
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current.arm_pc += GetInstSize();
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}
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void JitX64::CMP_reg(Cond cond, ArmReg Rn_index, ArmImm5 imm5, ShiftType shift, ArmReg Rm_index) {
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cond_manager.CompileCond((ConditionCode)cond);
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Gen::X64Reg tmp = CompileDataProcessingHelper_reg(imm5, shift, Rm_index, false);
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if (Rn_index != 15) {
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OpArg Rn = reg_alloc.LockArmForRead(Rn_index);
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code->CMP(32, Rn, R(tmp));
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reg_alloc.UnlockArm(Rn_index);
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} else {
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// TODO: Optimize this
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X64Reg tmp2 = reg_alloc.AllocTemp();
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code->MOV(32, R(tmp2), Imm32(GetReg15Value()));
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code->CMP(32, R(tmp2), R(tmp));
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reg_alloc.UnlockTemp(tmp2);
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}
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reg_alloc.UnlockTemp(tmp);
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UpdateFlagsC_complement();
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UpdateFlagsZVN();
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current.arm_pc += GetInstSize();
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}
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void JitX64::EOR_imm(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, int rotate, ArmImm8 imm8) {
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cond_manager.CompileCond((ConditionCode)cond);
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@ -169,6 +415,27 @@ void JitX64::EOR_imm(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, int ro
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}
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}
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void JitX64::EOR_reg(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmImm5 imm5, ShiftType shift, ArmReg Rm_index) {
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cond_manager.CompileCond((ConditionCode)cond);
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Gen::X64Reg tmp = CompileDataProcessingHelper_reg(imm5, shift, Rm_index, S);
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CompileDataProcessingHelper(Rn_index, Rd_index, [&](X64Reg Rd) {
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code->XOR(32, R(Rd), R(tmp));
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});
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reg_alloc.UnlockTemp(tmp);
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if (S) {
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UpdateFlagsZN();
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}
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current.arm_pc += GetInstSize();
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if (Rd_index == 15) {
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CompileReturnToDispatch();
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}
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}
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void JitX64::MOV_imm(Cond cond, bool S, ArmReg Rd_index, int rotate, ArmImm8 imm8) {
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cond_manager.CompileCond((ConditionCode)cond);
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@ -194,6 +461,28 @@ void JitX64::MOV_imm(Cond cond, bool S, ArmReg Rd_index, int rotate, ArmImm8 imm
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}
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}
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void JitX64::MOV_reg(Cond cond, bool S, ArmReg Rd_index, ArmImm5 imm5, ShiftType shift, ArmReg Rm_index) {
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cond_manager.CompileCond((ConditionCode)cond);
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Gen::X64Reg tmp = CompileDataProcessingHelper_reg(imm5, shift, Rm_index, S);
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Gen::OpArg Rd = reg_alloc.LockArmForWrite(Rd_index);
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code->MOV(32, Rd, R(tmp));
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reg_alloc.UnlockArm(Rd_index);
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if (S) {
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code->CMP(32, R(tmp), Imm32(0));
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UpdateFlagsZN();
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}
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reg_alloc.UnlockTemp(tmp);
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current.arm_pc += GetInstSize();
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if (Rd_index == 15) {
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CompileReturnToDispatch();
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}
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}
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void JitX64::MVN_imm(Cond cond, bool S, ArmReg Rd_index, int rotate, ArmImm8 imm8) {
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cond_manager.CompileCond((ConditionCode)cond);
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@ -219,6 +508,29 @@ void JitX64::MVN_imm(Cond cond, bool S, ArmReg Rd_index, int rotate, ArmImm8 imm
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}
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}
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void JitX64::MVN_reg(Cond cond, bool S, ArmReg Rd_index, ArmImm5 imm5, ShiftType shift, ArmReg Rm_index) {
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cond_manager.CompileCond((ConditionCode)cond);
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Gen::X64Reg tmp = CompileDataProcessingHelper_reg(imm5, shift, Rm_index, S);
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code->NOT(32, R(tmp));
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Gen::OpArg Rd = reg_alloc.LockArmForWrite(Rd_index);
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code->MOV(32, Rd, R(tmp));
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reg_alloc.UnlockArm(Rd_index);
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if (S) {
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code->CMP(32, R(tmp), Imm32(0));
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UpdateFlagsZN();
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}
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reg_alloc.UnlockTemp(tmp);
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current.arm_pc += GetInstSize();
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if (Rd_index == 15) {
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CompileReturnToDispatch();
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}
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}
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void JitX64::ORR_imm(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, int rotate, ArmImm8 imm8) {
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cond_manager.CompileCond((ConditionCode)cond);
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@ -241,6 +553,27 @@ void JitX64::ORR_imm(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, int ro
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}
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}
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void JitX64::ORR_reg(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmImm5 imm5, ShiftType shift, ArmReg Rm_index) {
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cond_manager.CompileCond((ConditionCode)cond);
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Gen::X64Reg tmp = CompileDataProcessingHelper_reg(imm5, shift, Rm_index, S);
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CompileDataProcessingHelper(Rn_index, Rd_index, [&](X64Reg Rd) {
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code->OR(32, R(Rd), R(tmp));
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});
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reg_alloc.UnlockTemp(tmp);
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if (S) {
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UpdateFlagsZN();
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}
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current.arm_pc += GetInstSize();
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if (Rd_index == 15) {
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CompileReturnToDispatch();
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}
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}
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void JitX64::RSB_imm(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, int rotate, ArmImm8 imm8) {
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cond_manager.CompileCond((ConditionCode)cond);
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@ -269,6 +602,36 @@ void JitX64::RSB_imm(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, int ro
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}
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}
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void JitX64::RSB_reg(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmImm5 imm5, ShiftType shift, ArmReg Rm_index) {
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cond_manager.CompileCond((ConditionCode)cond);
|
||||
|
||||
Gen::X64Reg tmp = CompileDataProcessingHelper_reg(imm5, shift, Rm_index, false);
|
||||
|
||||
CompileDataProcessingHelper_Reverse(Rn_index, Rd_index, [&](X64Reg Rd) {
|
||||
code->MOV(32, R(Rd), R(tmp));
|
||||
|
||||
if (Rn_index == 15) {
|
||||
code->SUB(32, R(Rd), Imm32(GetReg15Value()));
|
||||
} else {
|
||||
Gen::OpArg Rn = reg_alloc.LockArmForRead(Rn_index);
|
||||
code->SUB(32, R(Rd), Rn);
|
||||
reg_alloc.UnlockArm(Rn_index);
|
||||
}
|
||||
});
|
||||
|
||||
reg_alloc.UnlockTemp(tmp);
|
||||
|
||||
if (S) {
|
||||
UpdateFlagsZVN();
|
||||
UpdateFlagsC_complement();
|
||||
}
|
||||
|
||||
current.arm_pc += GetInstSize();
|
||||
if (Rd_index == 15) {
|
||||
CompileReturnToDispatch();
|
||||
}
|
||||
}
|
||||
|
||||
void JitX64::RSC_imm(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, int rotate, ArmImm8 imm8) {
|
||||
cond_manager.CompileCond((ConditionCode)cond);
|
||||
|
||||
@ -300,6 +663,39 @@ void JitX64::RSC_imm(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, int ro
|
||||
}
|
||||
}
|
||||
|
||||
void JitX64::RSC_reg(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmImm5 imm5, ShiftType shift, ArmReg Rm_index) {
|
||||
cond_manager.CompileCond((ConditionCode)cond);
|
||||
|
||||
Gen::X64Reg tmp = CompileDataProcessingHelper_reg(imm5, shift, Rm_index, false);
|
||||
|
||||
CompileDataProcessingHelper_Reverse(Rn_index, Rd_index, [&](X64Reg Rd) {
|
||||
code->MOV(32, R(Rd), R(tmp));
|
||||
|
||||
code->BT(32, MJitStateCFlag(), Imm8(0));
|
||||
code->CMC();
|
||||
|
||||
if (Rn_index == 15) {
|
||||
code->SBB(32, R(Rd), Imm32(GetReg15Value()));
|
||||
} else {
|
||||
Gen::OpArg Rn = reg_alloc.LockArmForRead(Rn_index);
|
||||
code->SBB(32, R(Rd), Rn);
|
||||
reg_alloc.UnlockArm(Rn_index);
|
||||
}
|
||||
});
|
||||
|
||||
reg_alloc.UnlockTemp(tmp);
|
||||
|
||||
if (S) {
|
||||
UpdateFlagsZVN();
|
||||
UpdateFlagsC_complement();
|
||||
}
|
||||
|
||||
current.arm_pc += GetInstSize();
|
||||
if (Rd_index == 15) {
|
||||
CompileReturnToDispatch();
|
||||
}
|
||||
}
|
||||
|
||||
void JitX64::SBC_imm(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, int rotate, ArmImm8 imm8) {
|
||||
cond_manager.CompileCond((ConditionCode)cond);
|
||||
|
||||
@ -322,6 +718,30 @@ void JitX64::SBC_imm(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, int ro
|
||||
}
|
||||
}
|
||||
|
||||
void JitX64::SBC_reg(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmImm5 imm5, ShiftType shift, ArmReg Rm_index) {
|
||||
cond_manager.CompileCond((ConditionCode)cond);
|
||||
|
||||
Gen::X64Reg tmp = CompileDataProcessingHelper_reg(imm5, shift, Rm_index, false);
|
||||
|
||||
CompileDataProcessingHelper(Rn_index, Rd_index, [&](X64Reg Rd) {
|
||||
code->BT(32, MJitStateCFlag(), Imm8(0));
|
||||
code->CMC();
|
||||
code->SBB(32, R(Rd), R(tmp));
|
||||
});
|
||||
|
||||
reg_alloc.UnlockTemp(tmp);
|
||||
|
||||
if (S) {
|
||||
UpdateFlagsZVN();
|
||||
UpdateFlagsC_complement();
|
||||
}
|
||||
|
||||
current.arm_pc += GetInstSize();
|
||||
if (Rd_index == 15) {
|
||||
CompileReturnToDispatch();
|
||||
}
|
||||
}
|
||||
|
||||
void JitX64::SUB_imm(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, int rotate, ArmImm8 imm8) {
|
||||
cond_manager.CompileCond((ConditionCode)cond);
|
||||
|
||||
@ -342,6 +762,28 @@ void JitX64::SUB_imm(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, int ro
|
||||
}
|
||||
}
|
||||
|
||||
void JitX64::SUB_reg(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmImm5 imm5, ShiftType shift, ArmReg Rm_index) {
|
||||
cond_manager.CompileCond((ConditionCode)cond);
|
||||
|
||||
Gen::X64Reg tmp = CompileDataProcessingHelper_reg(imm5, shift, Rm_index, false);
|
||||
|
||||
CompileDataProcessingHelper(Rn_index, Rd_index, [&](X64Reg Rd) {
|
||||
code->SUB(32, R(Rd), R(tmp));
|
||||
});
|
||||
|
||||
reg_alloc.UnlockTemp(tmp);
|
||||
|
||||
if (S) {
|
||||
UpdateFlagsZVN();
|
||||
UpdateFlagsC_complement();
|
||||
}
|
||||
|
||||
current.arm_pc += GetInstSize();
|
||||
if (Rd_index == 15) {
|
||||
CompileReturnToDispatch();
|
||||
}
|
||||
}
|
||||
|
||||
void JitX64::TEQ_imm(Cond cond, ArmReg Rn_index, int rotate, ArmImm8 imm8) {
|
||||
cond_manager.CompileCond((ConditionCode)cond);
|
||||
|
||||
@ -369,6 +811,26 @@ void JitX64::TEQ_imm(Cond cond, ArmReg Rn_index, int rotate, ArmImm8 imm8) {
|
||||
current.arm_pc += GetInstSize();
|
||||
}
|
||||
|
||||
void JitX64::TEQ_reg(Cond cond, ArmReg Rn_index, ArmImm5 imm5, ShiftType shift, ArmReg Rm_index) {
|
||||
cond_manager.CompileCond((ConditionCode)cond);
|
||||
|
||||
Gen::X64Reg tmp = CompileDataProcessingHelper_reg(imm5, shift, Rm_index, true);
|
||||
|
||||
if (Rn_index == 15) {
|
||||
code->XOR(32, R(tmp), Imm32(GetReg15Value()));
|
||||
} else {
|
||||
Gen::OpArg Rn = reg_alloc.LockArmForRead(Rn_index);
|
||||
code->XOR(32, R(tmp), Rn);
|
||||
reg_alloc.UnlockArm(Rn_index);
|
||||
}
|
||||
|
||||
reg_alloc.UnlockTemp(tmp);
|
||||
|
||||
UpdateFlagsZN();
|
||||
|
||||
current.arm_pc += GetInstSize();
|
||||
}
|
||||
|
||||
void JitX64::TST_imm(Cond cond, ArmReg Rn_index, int rotate, ArmImm8 imm8) {
|
||||
cond_manager.CompileCond((ConditionCode)cond);
|
||||
|
||||
@ -399,37 +861,41 @@ void JitX64::TST_imm(Cond cond, ArmReg Rn_index, int rotate, ArmImm8 imm8) {
|
||||
current.arm_pc += GetInstSize();
|
||||
}
|
||||
|
||||
void JitX64::ADC_reg(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmImm5 imm5, ShiftType shift, ArmReg Rm) { CompileInterpretInstruction(); }
|
||||
void JitX64::ADC_rsr(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmReg Rs, ShiftType shift, ArmReg Rm) { CompileInterpretInstruction(); }
|
||||
void JitX64::ADD_reg(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmImm5 imm5, ShiftType shift, ArmReg Rm) { CompileInterpretInstruction(); }
|
||||
void JitX64::ADD_rsr(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmReg Rs, ShiftType shift, ArmReg Rm) { CompileInterpretInstruction(); }
|
||||
void JitX64::AND_reg(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmImm5 imm5, ShiftType shift, ArmReg Rm) { CompileInterpretInstruction(); }
|
||||
void JitX64::AND_rsr(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmReg Rs, ShiftType shift, ArmReg Rm) { CompileInterpretInstruction(); }
|
||||
void JitX64::BIC_reg(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmImm5 imm5, ShiftType shift, ArmReg Rm) { CompileInterpretInstruction(); }
|
||||
void JitX64::BIC_rsr(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmReg Rs, ShiftType shift, ArmReg Rm) { CompileInterpretInstruction(); }
|
||||
void JitX64::CMN_reg(Cond cond, ArmReg Rn_index, ArmImm5 imm5, ShiftType shift, ArmReg Rm) { CompileInterpretInstruction(); }
|
||||
void JitX64::CMN_rsr(Cond cond, ArmReg Rn_index, ArmReg Rs, ShiftType shift, ArmReg Rm) { CompileInterpretInstruction(); }
|
||||
void JitX64::CMP_reg(Cond cond, ArmReg Rn_index, ArmImm5 imm5, ShiftType shift, ArmReg Rm) { CompileInterpretInstruction(); }
|
||||
void JitX64::CMP_rsr(Cond cond, ArmReg Rn_index, ArmReg Rs, ShiftType shift, ArmReg Rm) { CompileInterpretInstruction(); }
|
||||
void JitX64::EOR_reg(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmImm5 imm5, ShiftType shift, ArmReg Rm) { CompileInterpretInstruction(); }
|
||||
void JitX64::EOR_rsr(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmReg Rs, ShiftType shift, ArmReg Rm) { CompileInterpretInstruction(); }
|
||||
void JitX64::MOV_reg(Cond cond, bool S, ArmReg Rd_index, ArmImm5 imm5, ShiftType shift, ArmReg Rm) { CompileInterpretInstruction(); }
|
||||
void JitX64::MOV_rsr(Cond cond, bool S, ArmReg Rd_index, ArmReg Rs, ShiftType shift, ArmReg Rm) { CompileInterpretInstruction(); }
|
||||
void JitX64::MVN_reg(Cond cond, bool S, ArmReg Rd_index, ArmImm5 imm5, ShiftType shift, ArmReg Rm) { CompileInterpretInstruction(); }
|
||||
void JitX64::MVN_rsr(Cond cond, bool S, ArmReg Rd_index, ArmReg Rs, ShiftType shift, ArmReg Rm) { CompileInterpretInstruction(); }
|
||||
void JitX64::ORR_reg(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmImm5 imm5, ShiftType shift, ArmReg Rm) { CompileInterpretInstruction(); }
|
||||
void JitX64::ORR_rsr(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmReg Rs, ShiftType shift, ArmReg Rm) { CompileInterpretInstruction(); }
|
||||
void JitX64::RSB_reg(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmImm5 imm5, ShiftType shift, ArmReg Rm) { CompileInterpretInstruction(); }
|
||||
void JitX64::RSB_rsr(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmReg Rs, ShiftType shift, ArmReg Rm) { CompileInterpretInstruction(); }
|
||||
void JitX64::RSC_reg(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmImm5 imm5, ShiftType shift, ArmReg Rm) { CompileInterpretInstruction(); }
|
||||
void JitX64::RSC_rsr(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmReg Rs, ShiftType shift, ArmReg Rm) { CompileInterpretInstruction(); }
|
||||
void JitX64::SBC_reg(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmImm5 imm5, ShiftType shift, ArmReg Rm) { CompileInterpretInstruction(); }
|
||||
void JitX64::SBC_rsr(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmReg Rs, ShiftType shift, ArmReg Rm) { CompileInterpretInstruction(); }
|
||||
void JitX64::SUB_reg(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmImm5 imm5, ShiftType shift, ArmReg Rm) { CompileInterpretInstruction(); }
|
||||
void JitX64::SUB_rsr(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmReg Rs, ShiftType shift, ArmReg Rm) { CompileInterpretInstruction(); }
|
||||
void JitX64::TEQ_reg(Cond cond, ArmReg Rn_index, ArmImm5 imm5, ShiftType shift, ArmReg Rm) { CompileInterpretInstruction(); }
|
||||
void JitX64::TEQ_rsr(Cond cond, ArmReg Rn_index, ArmReg Rs, ShiftType shift, ArmReg Rm) { CompileInterpretInstruction(); }
|
||||
void JitX64::TST_reg(Cond cond, ArmReg Rn_index, ArmImm5 imm5, ShiftType shift, ArmReg Rm) { CompileInterpretInstruction(); }
|
||||
void JitX64::TST_rsr(Cond cond, ArmReg Rn_index, ArmReg Rs, ShiftType shift, ArmReg Rm) { CompileInterpretInstruction(); }
|
||||
void JitX64::TST_reg(Cond cond, ArmReg Rn_index, ArmImm5 imm5, ShiftType shift, ArmReg Rm_index) {
|
||||
cond_manager.CompileCond((ConditionCode)cond);
|
||||
|
||||
Gen::X64Reg tmp = CompileDataProcessingHelper_reg(imm5, shift, Rm_index, true);
|
||||
|
||||
if (Rn_index == 15) {
|
||||
code->TEST(32, R(tmp), Imm32(GetReg15Value()));
|
||||
} else {
|
||||
OpArg Rn = reg_alloc.LockArmForRead(Rn_index);
|
||||
code->TEST(32, R(tmp), Rn);
|
||||
reg_alloc.UnlockArm(Rn_index);
|
||||
}
|
||||
|
||||
reg_alloc.UnlockTemp(tmp);
|
||||
|
||||
UpdateFlagsZN();
|
||||
|
||||
current.arm_pc += GetInstSize();
|
||||
}
|
||||
|
||||
void JitX64::ADC_rsr(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmReg Rs_index, ShiftType shift, ArmReg Rm_index) { CompileInterpretInstruction(); }
|
||||
void JitX64::ADD_rsr(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmReg Rs_index, ShiftType shift, ArmReg Rm_index) { CompileInterpretInstruction(); }
|
||||
void JitX64::AND_rsr(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmReg Rs_index, ShiftType shift, ArmReg Rm_index) { CompileInterpretInstruction(); }
|
||||
void JitX64::BIC_rsr(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmReg Rs_index, ShiftType shift, ArmReg Rm_index) { CompileInterpretInstruction(); }
|
||||
void JitX64::CMN_rsr(Cond cond, ArmReg Rn_index, ArmReg Rs_index, ShiftType shift, ArmReg Rm_index) { CompileInterpretInstruction(); }
|
||||
void JitX64::CMP_rsr(Cond cond, ArmReg Rn_index, ArmReg Rs_index, ShiftType shift, ArmReg Rm_index) { CompileInterpretInstruction(); }
|
||||
void JitX64::EOR_rsr(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmReg Rs_index, ShiftType shift, ArmReg Rm_index) { CompileInterpretInstruction(); }
|
||||
void JitX64::MOV_rsr(Cond cond, bool S, ArmReg Rd_index, ArmReg Rs_index, ShiftType shift, ArmReg Rm_index) { CompileInterpretInstruction(); }
|
||||
void JitX64::MVN_rsr(Cond cond, bool S, ArmReg Rd_index, ArmReg Rs_index, ShiftType shift, ArmReg Rm_index) { CompileInterpretInstruction(); }
|
||||
void JitX64::ORR_rsr(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmReg Rs_index, ShiftType shift, ArmReg Rm_index) { CompileInterpretInstruction(); }
|
||||
void JitX64::RSB_rsr(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmReg Rs_index, ShiftType shift, ArmReg Rm_index) { CompileInterpretInstruction(); }
|
||||
void JitX64::RSC_rsr(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmReg Rs_index, ShiftType shift, ArmReg Rm_index) { CompileInterpretInstruction(); }
|
||||
void JitX64::SBC_rsr(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmReg Rs_index, ShiftType shift, ArmReg Rm_index) { CompileInterpretInstruction(); }
|
||||
void JitX64::SUB_rsr(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmReg Rs_index, ShiftType shift, ArmReg Rm_index) { CompileInterpretInstruction(); }
|
||||
void JitX64::TEQ_rsr(Cond cond, ArmReg Rn_index, ArmReg Rs_index, ShiftType shift, ArmReg Rm_index) { CompileInterpretInstruction(); }
|
||||
void JitX64::TST_rsr(Cond cond, ArmReg Rn_index, ArmReg Rs_index, ShiftType shift, ArmReg Rm_index) { CompileInterpretInstruction(); }
|
||||
|
||||
}
|
||||
|
||||
@ -94,7 +94,7 @@ private:
|
||||
Gen::OpArg MJitStateExclusiveTag();
|
||||
Gen::OpArg MJitStateExclusiveState();
|
||||
|
||||
u32 GetReg15Value() const { return (current.arm_pc & ~0x1) + GetInstSize() * 2; }
|
||||
u32 GetReg15Value() const { return static_cast<u32>((current.arm_pc & ~0x1) + GetInstSize() * 2); }
|
||||
|
||||
void UpdateFlagsZVCN() {
|
||||
cond_manager.FlagsDirty();
|
||||
@ -160,6 +160,8 @@ private:
|
||||
// Data processing instructions
|
||||
void CompileDataProcessingHelper(ArmReg Rn_index, ArmReg Rd_index, std::function<void(Gen::X64Reg)> body);
|
||||
void CompileDataProcessingHelper_Reverse(ArmReg Rn_index, ArmReg Rd_index, std::function<void(Gen::X64Reg)> body);
|
||||
Gen::X64Reg CompileDataProcessingHelper_reg(ArmImm5 imm5, ShiftType shift, ArmReg Rm, bool do_shifter_carry_out);
|
||||
Gen::X64Reg CompileDataProcessingHelper_rsr(ArmReg Rs, ShiftType shift, ArmReg Rm);
|
||||
void ADC_imm(Cond cond, bool S, ArmReg Rn, ArmReg Rd, int rotate, ArmImm8 imm8) override;
|
||||
void ADC_reg(Cond cond, bool S, ArmReg Rn, ArmReg Rd, ArmImm5 imm5, ShiftType shift, ArmReg Rm) override;
|
||||
void ADC_rsr(Cond cond, bool S, ArmReg Rn, ArmReg Rd, ArmReg Rs, ShiftType shift, ArmReg Rm) override;
|
||||
|
||||
@ -87,7 +87,7 @@ TEST_CASE("Fuzz ARM data processing instructions", "[JitX64]") {
|
||||
}
|
||||
|
||||
SECTION("long blocks") {
|
||||
FuzzJit(1024, 1025, 15, instruction_select_without_R15);
|
||||
FuzzJit(1024, 1025, 50, instruction_select_without_R15);
|
||||
}
|
||||
|
||||
auto instruction_select_only_R15 = [&]() -> u32 {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user