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vertex_shader: Optimized SIMD-based vertex shader interpreter for x86 systems.
This commit is contained in:
bunnei
parent
b7ac4cb54e
commit
f468dcd799
2
externals/nihstro
vendored
2
externals/nihstro
vendored
@ -1 +1 @@
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Subproject commit 81f1804a43f625e3a1a20752c0db70a413410380
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Subproject commit 0eb48f4488b1e85d8f97b55574b35cb92cbb0b8b
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@ -69,6 +69,7 @@ void Config::ReadValues() {
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Settings::values.frame_skip = glfw_config->GetInteger("Core", "frame_skip", 0);
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// Renderer
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Settings::values.shader_core = glfw_config->GetBoolean("Renderer", "shader_core", 0);
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Settings::values.use_hw_renderer = glfw_config->GetBoolean("Renderer", "use_hw_renderer", false);
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Settings::values.bg_red = (float)glfw_config->GetReal("Renderer", "bg_red", 1.0);
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@ -42,6 +42,10 @@ gpu_refresh_rate =
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frame_skip =
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[Renderer]
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# Shader core to use for emulation of vertex shaders
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# 0 (default): Optimized interpreter, 1: Interpreter
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shader_core =
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# Whether to use software or hardware rendering.
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# 0 (default): Software, 1: Hardware
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use_hw_renderer =
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@ -53,6 +53,7 @@ void Config::ReadValues() {
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qt_config->endGroup();
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qt_config->beginGroup("Renderer");
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Settings::values.shader_core = qt_config->value("shader_core", 0).toInt();
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Settings::values.use_hw_renderer = qt_config->value("use_hw_renderer", false).toBool();
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Settings::values.bg_red = qt_config->value("bg_red", 1.0).toFloat();
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@ -105,6 +106,7 @@ void Config::SaveValues() {
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qt_config->endGroup();
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qt_config->beginGroup("Renderer");
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qt_config->setValue("shader_core", Settings::values.shader_core);
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qt_config->setValue("use_hw_renderer", Settings::values.use_hw_renderer);
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// Cast to double because Qt's written float values are not human-readable
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@ -8,6 +8,11 @@
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namespace Settings {
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enum ShaderCore {
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OptimizedInterpreter,
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Interpreter
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};
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struct Values {
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// Controls
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int pad_a_key;
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@ -44,6 +49,7 @@ struct Values {
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int region_value;
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// Renderer
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int shader_core;
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bool use_hw_renderer;
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float bg_red;
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@ -14,6 +14,7 @@ set(SRCS
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rasterizer.cpp
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utils.cpp
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vertex_shader.cpp
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vertex_shader_simd.cpp
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video_core.cpp
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)
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@ -38,6 +39,7 @@ set(HEADERS
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renderer_base.h
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utils.h
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vertex_shader.h
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vertex_shader_simd.h
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video_core.h
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)
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@ -5,6 +5,7 @@
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#include <boost/range/algorithm/fill.hpp>
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#include "common/profiler.h"
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#include "common/cpu_detect.h"
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#include "clipper.h"
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#include "command_processor.h"
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@ -12,6 +13,7 @@
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#include "pica.h"
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#include "primitive_assembly.h"
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#include "vertex_shader.h"
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#include "vertex_shader_simd.h"
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#include "video_core.h"
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#include "core/hle/service/gsp_gpu.h"
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#include "core/hw/gpu.h"
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@ -121,6 +123,11 @@ static inline void WritePicaReg(u32 id, u32 value, u32 mask) {
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PrimitiveAssembler<VertexShader::OutputVertex> primitive_assembler(regs.triangle_topology.Value());
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PrimitiveAssembler<DebugUtils::GeometryDumper::Vertex> dumping_primitive_assembler(regs.triangle_topology.Value());
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VertexShaderSIMD::CoreState state;
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if (Settings::values.shader_core == Settings::OptimizedInterpreter) {
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VertexShaderSIMD::InitCore(state);
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}
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for (unsigned int index = 0; index < regs.num_vertices; ++index)
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{
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unsigned int vertex = is_indexed ? (index_u16 ? index_address_16[index] : index_address_8[index]) : index;
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@ -190,7 +197,12 @@ static inline void WritePicaReg(u32 id, u32 value, u32 mask) {
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&geometry_dumper, _1, _2, _3));
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// Send to vertex shader
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VertexShader::OutputVertex output = VertexShader::RunShader(input, attribute_config.GetNumTotalAttributes());
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VertexShader::OutputVertex output;
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if (Settings::values.shader_core == Settings::OptimizedInterpreter && Common::cpu_info.bSSE4_1) {
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output = VertexShaderSIMD::RunShader(state, input, attribute_config.GetNumTotalAttributes());
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} else {
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output = VertexShader::RunShader(input, attribute_config.GetNumTotalAttributes());
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}
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if (is_indexed) {
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// TODO: Add processed vertex to vertex cache!
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@ -6,11 +6,16 @@
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#include "pica.h"
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#include "vertex_shader_simd.h"
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namespace Pica {
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State g_state;
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void Init() {
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#if _M_SSE >= 0x401
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VertexShaderSIMD::Init();
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#endif
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}
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void Shutdown() {
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528
src/video_core/vertex_shader_simd.cpp
Normal file
528
src/video_core/vertex_shader_simd.cpp
Normal file
@ -0,0 +1,528 @@
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// Copyright 2015 Citra Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <vector>
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#include <nihstro/shader_bytecode.h>
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#include "video_core/vertex_shader_simd.h"
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using nihstro::OpCode;
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using nihstro::SwizzlePattern;
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namespace Pica {
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namespace VertexShaderSIMD {
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#if _M_SSE >= 0x401
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static __m128i swizzle_dst_mask[16];
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static __m128i swizzle_src_selector[256];
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#endif
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void Init() {
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#if _M_SSE >= 0x401
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for (int i = 0; i < 16; ++i) {
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swizzle_dst_mask[i].m128i_u32[0] = ((i >> 3) & 1) * 0xffffffff;
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swizzle_dst_mask[i].m128i_u32[1] = ((i >> 2) & 1) * 0xffffffff;
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swizzle_dst_mask[i].m128i_u32[2] = ((i >> 1) & 1) * 0xffffffff;
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swizzle_dst_mask[i].m128i_u32[3] = (i & 1) * 0xffffffff;
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}
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#define SELECT(n) (((((n) << 2) + 3) << 24) | ((((n) << 2) + 2) << 16) | ((((n) << 2) + 1) << 8) | ((n) << 2))
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for (int i = 0; i < 256; ++i) {
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swizzle_src_selector[i].m128i_u32[0] = SELECT((i >> 6) & 0x3);
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swizzle_src_selector[i].m128i_u32[1] = SELECT((i >> 4) & 0x3);
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swizzle_src_selector[i].m128i_u32[2] = SELECT((i >> 2) & 0x3);
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swizzle_src_selector[i].m128i_u32[3] = SELECT( i & 0x3);
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}
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#undef SELECT
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#endif
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}
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#pragma pack(1)
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union Instruction {
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Instruction& operator =(const Instruction& instr) {
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hex = instr.hex;
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return *this;
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}
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u32 hex;
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BitField<0x1a, 0x6, OpCode::Id> opcode;
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// General notes:
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//
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// When two input registers are used, one of them uses a 5-bit index while the other
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// one uses a 7-bit index. This is because at most one floating point uniform may be used
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// as an input.
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enum CompareOp : u32 {
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Equal = 0,
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NotEqual = 1,
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LessThan = 2,
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LessEqual = 3,
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GreaterThan = 4,
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GreaterEqual = 5,
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Unk6 = 6,
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Unk7 = 7
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};
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// Format used e.g. by arithmetic instructions and comparisons
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union Common { // TODO: Remove name
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BitField<0x00, 0x7, u32> operand_desc_id;
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/**
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* Source inputs may be reordered for certain instructions.
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* Use GetSrc1 and GetSrc2 instead to access the input register indices hence.
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*/
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BitField<0x07, 0x5, u32> src2;
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BitField<0x0c, 0x7, u32> src1;
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BitField<0x07, 0x7, u32> src2i;
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BitField<0x0e, 0x5, u32> src1i;
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// Address register value is used for relative addressing of src1
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BitField<0x13, 0x2, u32> address_register_index;
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union {
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BitField<0x15, 0x3, CompareOp> y;
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BitField<0x18, 0x3, CompareOp> x;
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} compare_op;
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BitField<0x15, 0x5, u32> dest;
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} common;
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union FlowControlType { // TODO: Make nameless once MSVC supports it
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enum Op : u32 {
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Or = 0,
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And = 1,
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JustX = 2,
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JustY = 3
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};
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BitField<0x00, 0x8, u32> num_instructions;
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BitField<0x0a, 0xc, u32> dest_offset;
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BitField<0x16, 0x2, Op> op;
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BitField<0x16, 0x4, u32> bool_uniform_id;
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BitField<0x16, 0x2, u32> int_uniform_id; // TODO: Verify that only this many bits are used...
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BitFlag<0x18, u32> refy;
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BitFlag<0x19, u32> refx;
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} flow_control;
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union {
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BitField<0x00, 0x5, u32> operand_desc_id;
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BitField<0x05, 0x5, u32> src3;
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BitField<0x0a, 0x7, u32> src2;
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BitField<0x11, 0x7, u32> src1;
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BitField<0x05, 0x7, u32> src3i;
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BitField<0x0c, 0x5, u32> src2i;
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BitField<0x18, 0x5, u32> dest;
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} cmp;
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union {
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BitField<0x00, 0x5, u32> operand_desc_id;
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BitField<0x05, 0x5, u32> src3;
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BitField<0x0a, 0x7, u32> src2;
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BitField<0x11, 0x7, u32> src1;
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BitField<0x05, 0x7, u32> src3i;
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BitField<0x0c, 0x5, u32> src2i;
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BitField<0x18, 0x5, u32> dest;
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} mad;
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};
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static_assert(sizeof(Instruction) == 0x4, "Incorrect structure size");
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static_assert(std::is_standard_layout<Instruction>::value, "Structure does not have standard layout");
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static inline void Call(CoreState& state, u32 offset, u32 num_instructions, u32 return_offset, u8 repeat_count, u8 loop_increment) {
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state.pc = offset;
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state.call_stack.push_back({ offset + num_instructions, return_offset, repeat_count, loop_increment, offset });
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};
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static inline bool Compare(Instruction::CompareOp op, f32 src1, f32 src2) {
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switch (op) {
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case Instruction::CompareOp::Equal:
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return src1 == src2;
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case Instruction::CompareOp::NotEqual:
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return src1 != src2;
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case Instruction::CompareOp::LessThan:
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return src1 < src2;
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case Instruction::CompareOp::LessEqual:
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return src1 <= src2;
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case Instruction::CompareOp::GreaterThan:
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return src1 > src2;
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case Instruction::CompareOp::GreaterEqual:
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return src1 >= src2;
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}
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return false;
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}
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static inline bool EvaluateCondition(const CoreState& state, bool refx, bool refy, Instruction::FlowControlType flow_control) {
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const bool results[2] = { refx == state.conditional_code[0],
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refy == state.conditional_code[1] };
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switch (flow_control.op) {
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case flow_control.Or:
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return results[0] || results[1];
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case flow_control.And:
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return results[0] && results[1];
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case flow_control.JustX:
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return results[0];
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case flow_control.JustY:
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return results[1];
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}
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return false;
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};
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void InitCore(CoreState& state) {
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memcpy(&state.uniform[0].x, g_state.vs.uniforms.f, sizeof(state.uniform));
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}
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VertexShader::OutputVertex RunShader(CoreState& state, const VertexShader::InputVertex& input, int num_attributes) {
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const auto& regs = g_state.regs;
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auto& vs = g_state.vs;
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const auto& swizzle_data = vs.swizzle_data;
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const auto& program_code = vs.program_code;
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bool exit_loop = false;
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state.pc = regs.vs_main_offset;
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state.address_offset.raw_i.m128i_i32[0] = 0;
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state.conditional_code[0] = false;
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state.conditional_code[1] = false;
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const auto& reg_map = regs.vs_input_register_map;
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for (int i = 0; i < num_attributes; ++i) {
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Reg& reg = state.input[reg_map.GetRegisterForAttribute(i)];
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reg.x = input.attr[i].x.ToFloat32();
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reg.y = input.attr[i].y.ToFloat32();
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reg.z = input.attr[i].z.ToFloat32();
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reg.w = input.attr[i].w.ToFloat32();
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}
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#if _M_SSE >= 0x401
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while (true) {
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if (!state.call_stack.empty()) {
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auto& top = state.call_stack.back();
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if (&program_code[state.pc] - program_code.data() == top.final_address) {
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state.address_offset.raw_i.m128i_i32[3] += top.loop_increment;
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if (top.repeat_counter-- == 0) {
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state.pc = top.return_address;
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state.call_stack.pop_back();
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} else {
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state.pc = top.loop_address;
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}
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// TODO: Is "trying again" accurate to hardware?
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continue;
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}
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}
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const Instruction& instr = *(const Instruction*)&program_code[state.pc];
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#define NEGATE(value, negate) _mm_xor_si128(value, _mm_set1_epi32(negate << 31))
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#define SWIZZLE(reg, selector) _mm_shuffle_epi8(state.InputReg(reg).raw_i, swizzle_src_selector[selector])
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#define FORMAT1(operation_) { \
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Reg src1, src2, temp; \
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const SwizzlePattern& swizzle = *(SwizzlePattern*)&swizzle_data[instr.common.operand_desc_id]; \
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int offset = state.address_offset.raw_i.m128i_i32[instr.common.address_register_index]; \
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src1.raw_i = NEGATE(SWIZZLE(instr.common.src1 + offset, swizzle.src1_selector), swizzle.negate_src1); \
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src2.raw_i = NEGATE(SWIZZLE(instr.common.src2, swizzle.src2_selector), swizzle.negate_src2); \
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temp.raw_f = operation_; \
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__m128i dst_mask = swizzle_dst_mask[swizzle.dest_mask]; \
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auto& dest = state.OutputReg(instr.common.dest); \
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dest.raw_i = _mm_or_si128(_mm_andnot_si128(dst_mask, dest.raw_i), _mm_and_si128(dst_mask, temp.raw_i)); \
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}
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#define FORMAT1I(operation_) { \
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Reg src1, src2, temp; \
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const SwizzlePattern& swizzle = *(SwizzlePattern*)&swizzle_data[instr.common.operand_desc_id]; \
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int offset = state.address_offset.raw_i.m128i_i32[instr.common.address_register_index]; \
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src1.raw_i = NEGATE(SWIZZLE(instr.common.src1i, swizzle.src1_selector), swizzle.negate_src1); \
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src2.raw_i = NEGATE(SWIZZLE(instr.common.src2i + offset, swizzle.src2_selector), swizzle.negate_src2); \
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temp.raw_f = operation_; \
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__m128i dst_mask = swizzle_dst_mask[swizzle.dest_mask]; \
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auto& dest = state.OutputReg(instr.common.dest); \
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dest.raw_i = _mm_or_si128(_mm_andnot_si128(dst_mask, dest.raw_i), _mm_and_si128(dst_mask, temp.raw_i)); \
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}
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#define FORMAT1U(operation_) { \
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Reg src1, temp; \
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const SwizzlePattern& swizzle = *(SwizzlePattern*)&swizzle_data[instr.common.operand_desc_id]; \
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int offset = state.address_offset.raw_i.m128i_i32[instr.common.address_register_index]; \
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src1.raw_i = NEGATE(SWIZZLE(instr.common.src1 + offset, swizzle.src1_selector), swizzle.negate_src1); \
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temp.raw_f = operation_; \
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__m128i dst_mask = swizzle_dst_mask[swizzle.dest_mask]; \
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auto& dest = state.OutputReg(instr.common.dest); \
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dest.raw_i = _mm_or_si128(_mm_andnot_si128(dst_mask, dest.raw_i), _mm_and_si128(dst_mask, temp.raw_i)); \
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}
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#define FORMAT5(operation_) { \
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Reg src1, src2, src3, temp; \
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const SwizzlePattern& swizzle = *(SwizzlePattern*)&swizzle_data[instr.mad.operand_desc_id]; \
|
||||
src1.raw_i = NEGATE(SWIZZLE(instr.mad.src1, swizzle.src1_selector), swizzle.negate_src1); \
|
||||
src2.raw_i = NEGATE(SWIZZLE(instr.mad.src2, swizzle.src2_selector), swizzle.negate_src2); \
|
||||
src3.raw_i = NEGATE(SWIZZLE(instr.mad.src3, swizzle.src3_selector), swizzle.negate_src3); \
|
||||
temp.raw_f = operation_; \
|
||||
__m128i dst_mask = swizzle_dst_mask[swizzle.dest_mask]; \
|
||||
auto& dest = state.OutputReg(instr.mad.dest); \
|
||||
dest.raw_i = _mm_or_si128(_mm_andnot_si128(dst_mask, dest.raw_i), _mm_and_si128(dst_mask, temp.raw_i)); \
|
||||
}
|
||||
|
||||
#define FORMAT5I(operation_) { \
|
||||
Reg src1, src2, src3, temp; \
|
||||
const SwizzlePattern& swizzle = *(SwizzlePattern*)&swizzle_data[instr.mad.operand_desc_id]; \
|
||||
src1.raw_i = NEGATE(SWIZZLE(instr.mad.src1, swizzle.src1_selector), swizzle.negate_src1); \
|
||||
src2.raw_i = NEGATE(SWIZZLE(instr.mad.src2i, swizzle.src2_selector), swizzle.negate_src2); \
|
||||
src3.raw_i = NEGATE(SWIZZLE(instr.mad.src3i, swizzle.src3_selector), swizzle.negate_src3); \
|
||||
temp.raw_f = operation_; \
|
||||
__m128i dst_mask = swizzle_dst_mask[swizzle.dest_mask]; \
|
||||
auto& dest = state.OutputReg(instr.mad.dest); \
|
||||
dest.raw_i = _mm_or_si128(_mm_andnot_si128(dst_mask, dest.raw_i), _mm_and_si128(dst_mask, temp.raw_i)); \
|
||||
}
|
||||
|
||||
switch (instr.opcode) {
|
||||
case OpCode::Id::ADD:
|
||||
FORMAT1(_mm_add_ps(src1.raw_f, src2.raw_f));
|
||||
break;
|
||||
|
||||
case OpCode::Id::DP3:
|
||||
FORMAT1(_mm_dp_ps(src1.raw_f, src2.raw_f, 0x7f));
|
||||
break;
|
||||
|
||||
case OpCode::Id::DP4:
|
||||
FORMAT1(_mm_dp_ps(src1.raw_f, src2.raw_f, 0xff));
|
||||
break;
|
||||
|
||||
case OpCode::Id::MUL:
|
||||
FORMAT1(_mm_mul_ps(src1.raw_f, src2.raw_f));
|
||||
break;
|
||||
|
||||
case OpCode::Id::SLT:
|
||||
FORMAT1(_mm_and_ps(_mm_cmplt_ps(src1.raw_f, src2.raw_f), _mm_set1_ps(1.f)));
|
||||
break;
|
||||
|
||||
case OpCode::Id::SLTI:
|
||||
FORMAT1I(_mm_and_ps(_mm_cmplt_ps(src1.raw_f, src2.raw_f), _mm_set1_ps(1.f)));
|
||||
break;
|
||||
|
||||
case OpCode::Id::FLR:
|
||||
FORMAT1U(_mm_floor_ps(src1.raw_f));
|
||||
break;
|
||||
|
||||
case OpCode::Id::MAX:
|
||||
FORMAT1(_mm_max_ps(src1.raw_f, src2.raw_f));
|
||||
break;
|
||||
|
||||
case OpCode::Id::MIN:
|
||||
FORMAT1(_mm_min_ps(src1.raw_f, src2.raw_f));
|
||||
break;
|
||||
|
||||
case OpCode::Id::RCP:
|
||||
FORMAT1U(_mm_rcp_ps(src1.raw_f));
|
||||
break;
|
||||
|
||||
case OpCode::Id::RSQ:
|
||||
FORMAT1U(_mm_rsqrt_ps(src1.raw_f));
|
||||
break;
|
||||
|
||||
case OpCode::Id::MOVA:
|
||||
{
|
||||
Reg src1, temp;
|
||||
const SwizzlePattern& swizzle = *(SwizzlePattern*)&swizzle_data[instr.common.operand_desc_id];
|
||||
int offset = state.address_offset.raw_i.m128i_i32[instr.common.address_register_index];
|
||||
src1.raw_i = NEGATE(SWIZZLE(instr.common.src1 + offset, swizzle.src1_selector), swizzle.negate_src1);
|
||||
temp.raw_i.m128i_i32[1] = static_cast<s32>(src1[0]);
|
||||
temp.raw_i.m128i_i32[2] = static_cast<s32>(src1[1]);
|
||||
__m128i dst_mask = swizzle_dst_mask[(swizzle.dest_mask & 0xc) >> 1];
|
||||
state.address_offset.raw_i = _mm_or_si128(_mm_andnot_si128(dst_mask, state.address_offset.raw_i),
|
||||
_mm_and_si128(dst_mask, temp.raw_i));
|
||||
break;
|
||||
}
|
||||
|
||||
case OpCode::Id::MOV:
|
||||
FORMAT1U(src1.raw_f);
|
||||
break;
|
||||
|
||||
case OpCode::Id::CALL:
|
||||
Call(state,
|
||||
instr.flow_control.dest_offset,
|
||||
instr.flow_control.num_instructions,
|
||||
state.pc + 1, 0, 0);
|
||||
continue;
|
||||
|
||||
case OpCode::Id::CALLU:
|
||||
if (vs.uniforms.b[instr.flow_control.bool_uniform_id]) {
|
||||
Call(state,
|
||||
instr.flow_control.dest_offset,
|
||||
instr.flow_control.num_instructions,
|
||||
state.pc + 1, 0, 0);
|
||||
continue;
|
||||
}
|
||||
break;
|
||||
|
||||
case OpCode::Id::CALLC:
|
||||
if (EvaluateCondition(state, instr.flow_control.refx, instr.flow_control.refy, instr.flow_control)) {
|
||||
Call(state,
|
||||
instr.flow_control.dest_offset,
|
||||
instr.flow_control.num_instructions,
|
||||
state.pc + 1, 0, 0);
|
||||
continue;
|
||||
}
|
||||
break;
|
||||
|
||||
case OpCode::Id::NOP:
|
||||
break;
|
||||
|
||||
case OpCode::Id::END:
|
||||
exit_loop = true;
|
||||
break;
|
||||
|
||||
case OpCode::Id::IFU:
|
||||
if (vs.uniforms.b[instr.flow_control.bool_uniform_id]) {
|
||||
Call(state,
|
||||
state.pc + 1,
|
||||
instr.flow_control.dest_offset - state.pc - 1,
|
||||
instr.flow_control.dest_offset + instr.flow_control.num_instructions, 0, 0);
|
||||
} else {
|
||||
Call(state,
|
||||
instr.flow_control.dest_offset,
|
||||
instr.flow_control.num_instructions,
|
||||
instr.flow_control.dest_offset + instr.flow_control.num_instructions, 0, 0);
|
||||
}
|
||||
continue;
|
||||
|
||||
case OpCode::Id::IFC:
|
||||
// TODO: Do we need to consider swizzlers here?
|
||||
if (EvaluateCondition(state, instr.flow_control.refx, instr.flow_control.refy, instr.flow_control)) {
|
||||
Call(state,
|
||||
state.pc + 1,
|
||||
instr.flow_control.dest_offset - state.pc - 1,
|
||||
instr.flow_control.dest_offset + instr.flow_control.num_instructions, 0, 0);
|
||||
} else {
|
||||
Call(state,
|
||||
instr.flow_control.dest_offset,
|
||||
instr.flow_control.num_instructions,
|
||||
instr.flow_control.dest_offset + instr.flow_control.num_instructions, 0, 0);
|
||||
}
|
||||
continue;
|
||||
|
||||
case OpCode::Id::LOOP:
|
||||
state.address_offset.raw_i.m128i_i32[3] = vs.uniforms.i[instr.flow_control.int_uniform_id].y;
|
||||
|
||||
Call(state,
|
||||
state.pc + 1,
|
||||
instr.flow_control.dest_offset - state.pc + 1,
|
||||
instr.flow_control.dest_offset + 1,
|
||||
vs.uniforms.i[instr.flow_control.int_uniform_id].x,
|
||||
vs.uniforms.i[instr.flow_control.int_uniform_id].z);
|
||||
|
||||
continue;
|
||||
|
||||
case OpCode::Id::JMPC:
|
||||
if (EvaluateCondition(state, instr.flow_control.refx, instr.flow_control.refy, instr.flow_control)) {
|
||||
state.pc = instr.flow_control.dest_offset;
|
||||
continue;
|
||||
}
|
||||
break;
|
||||
|
||||
case OpCode::Id::JMPU:
|
||||
if (vs.uniforms.b[instr.flow_control.bool_uniform_id]) {
|
||||
state.pc = instr.flow_control.dest_offset;
|
||||
continue;
|
||||
}
|
||||
break;
|
||||
|
||||
case OpCode::Id::CMP:
|
||||
case OpCode::Id::CMP + 1:
|
||||
{
|
||||
Reg src1, src2;
|
||||
const SwizzlePattern& swizzle = *(SwizzlePattern*)&swizzle_data[instr.common.operand_desc_id];
|
||||
int offset = state.address_offset.raw_i.m128i_i32[instr.common.address_register_index];
|
||||
src1.raw_i = NEGATE(SWIZZLE(instr.common.src1 + offset, swizzle.src1_selector), swizzle.negate_src1);
|
||||
src2.raw_i = NEGATE(SWIZZLE(instr.common.src2, swizzle.src2_selector), swizzle.negate_src2);
|
||||
state.conditional_code[0] = Compare(instr.common.compare_op.x, src1.x, src2.x);
|
||||
state.conditional_code[1] = Compare(instr.common.compare_op.y, src1.y, src2.y);
|
||||
break;
|
||||
}
|
||||
|
||||
case OpCode::Id::MADI:
|
||||
case OpCode::Id::MADI + 1:
|
||||
case OpCode::Id::MADI + 2:
|
||||
case OpCode::Id::MADI + 3:
|
||||
case OpCode::Id::MADI + 4:
|
||||
case OpCode::Id::MADI + 5:
|
||||
case OpCode::Id::MADI + 6:
|
||||
case OpCode::Id::MADI + 7:
|
||||
FORMAT5I(_mm_add_ps(_mm_mul_ps(src1.raw_f, src2.raw_f), src3.raw_f));
|
||||
break;
|
||||
|
||||
case OpCode::Id::MAD:
|
||||
case OpCode::Id::MAD + 1:
|
||||
case OpCode::Id::MAD + 2:
|
||||
case OpCode::Id::MAD + 3:
|
||||
case OpCode::Id::MAD + 4:
|
||||
case OpCode::Id::MAD + 5:
|
||||
case OpCode::Id::MAD + 6:
|
||||
case OpCode::Id::MAD + 7:
|
||||
FORMAT5(_mm_add_ps(_mm_mul_ps(src1.raw_f, src2.raw_f), src3.raw_f));
|
||||
break;
|
||||
|
||||
default:
|
||||
LOG_CRITICAL(HW_GPU, "Unhandled opcode: 0x%02x", instr.opcode.Value());
|
||||
UNIMPLEMENTED();
|
||||
}
|
||||
|
||||
state.pc += 1;
|
||||
|
||||
if (exit_loop)
|
||||
break;
|
||||
}
|
||||
#else
|
||||
UNREACHABLE();
|
||||
#endif
|
||||
|
||||
// Setup output data
|
||||
VertexShader::OutputVertex ret;
|
||||
// TODO(neobrain): Under some circumstances, up to 16 attributes may be output. We need to
|
||||
// figure out what those circumstances are and enable the remaining outputs then.
|
||||
for (int i = 0; i < 7; ++i) {
|
||||
const auto& output_register_map = regs.vs_output_attributes[i];
|
||||
|
||||
u32 semantics[4] = {
|
||||
output_register_map.map_x, output_register_map.map_y,
|
||||
output_register_map.map_z, output_register_map.map_w
|
||||
};
|
||||
|
||||
for (int comp = 0; comp < 4; ++comp) {
|
||||
f32* out = ((f32*)&ret) + semantics[comp];
|
||||
*out = state.output[i][comp];
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
} // namespace VertexShaderSIMD
|
||||
|
||||
} // namespace Pica
|
||||
78
src/video_core/vertex_shader_simd.h
Normal file
78
src/video_core/vertex_shader_simd.h
Normal file
@ -0,0 +1,78 @@
|
||||
// Copyright 2015 Citra Emulator Project
|
||||
// Licensed under GPLv2 or any later version
|
||||
// Refer to the license.txt file included.
|
||||
|
||||
#include "common/common_types.h"
|
||||
#include "common/intrinsics.h"
|
||||
|
||||
#include "vertex_shader.h"
|
||||
|
||||
namespace Pica {
|
||||
|
||||
namespace VertexShaderSIMD {
|
||||
|
||||
struct Reg {
|
||||
union {
|
||||
struct {
|
||||
f32 x, y, z, w;
|
||||
};
|
||||
#if _M_SSE >= 0x401
|
||||
__m128 raw_f;
|
||||
__m128i raw_i;
|
||||
#endif
|
||||
};
|
||||
|
||||
f32 operator [] (int i) {
|
||||
return *(&x + i);
|
||||
}
|
||||
};
|
||||
|
||||
struct CoreState {
|
||||
u32 pc;
|
||||
Reg address_offset;
|
||||
bool conditional_code[2];
|
||||
|
||||
struct CallStackElement {
|
||||
u32 final_address; // Address upon which we jump to return_address
|
||||
u32 return_address; // Where to jump when leaving scope
|
||||
u8 repeat_counter; // How often to repeat until this call stack element is removed
|
||||
u8 loop_increment; // Which value to add to the loop counter after an iteration
|
||||
// TODO: Should this be a signed value? Does it even matter?
|
||||
u32 loop_address; // The address where we'll return to after each loop iteration
|
||||
};
|
||||
|
||||
// TODO: Is there a maximal size for this?
|
||||
std::vector<CallStackElement> call_stack;
|
||||
|
||||
union {
|
||||
struct {
|
||||
Reg output[0x10];
|
||||
Reg input[0x10];
|
||||
Reg temporary[0x10];
|
||||
Reg uniform[0x60];
|
||||
};
|
||||
Reg regs[0x90];
|
||||
};
|
||||
|
||||
Reg InputReg(int index) const {
|
||||
return input[index];
|
||||
}
|
||||
|
||||
Reg& OutputReg(int index) {
|
||||
return regs[(index & 0xf) | ((index & 0x10) << 1)];
|
||||
}
|
||||
|
||||
};
|
||||
|
||||
/// Initializes lookup tables used by the SIMD vertex shader core
|
||||
void Init();
|
||||
|
||||
/// Initializes a SIMD vertex shader core for the current shader in Pica memory
|
||||
void InitCore(CoreState& state);
|
||||
|
||||
/// Runs a vertex shader core for the current shader in Pica memory
|
||||
VertexShader::OutputVertex RunShader(CoreState& state, const VertexShader::InputVertex& input, int num_attributes);
|
||||
|
||||
} // namespace VertexShaderSIMD
|
||||
|
||||
} // namespace Pica
|
||||
Loading…
Reference in New Issue
Block a user