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https://github.com/citra-emu/citra.git
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JitX64: Data Processing: Implement shift-by-register (_rsr) instructions
This commit is contained in:
MerryMage
parent
fc1f126ec5
commit
ec7c34ec92
@ -148,13 +148,13 @@ static const std::array<Instruction, 27> thumb_instruction_table = { {
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v->EOR_reg(0xE, /*S=*/true, Rd_Rn, Rd_Rn, 0, 0, Rm_Rs);
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break;
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case 2: // LSL Rd, Rs
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v->MOV_rsr(0xE, /*S=*/true, Rd_Rn, Rm_Rs, 0b0001, Rd_Rn);
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v->MOV_rsr(0xE, /*S=*/true, Rd_Rn, Rm_Rs, 0b00, Rd_Rn);
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break;
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case 3: // LSR Rd, Rs
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v->MOV_rsr(0xE, /*S=*/true, Rd_Rn, Rm_Rs, 0b0011, Rd_Rn);
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v->MOV_rsr(0xE, /*S=*/true, Rd_Rn, Rm_Rs, 0b01, Rd_Rn);
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break;
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case 4: // ASR Rd, Rs
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v->MOV_rsr(0xE, /*S=*/true, Rd_Rn, Rm_Rs, 0b0101, Rd_Rn);
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v->MOV_rsr(0xE, /*S=*/true, Rd_Rn, Rm_Rs, 0b10, Rd_Rn);
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break;
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case 5: // ADC Rd, Rm
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v->ADC_reg(0xE, /*S=*/true, Rd_Rn, Rd_Rn, 0, 0, Rm_Rs);
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@ -163,7 +163,7 @@ static const std::array<Instruction, 27> thumb_instruction_table = { {
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v->SBC_reg(0xE, /*S=*/true, Rd_Rn, Rd_Rn, 0, 0, Rm_Rs);
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break;
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case 7: // ROR Rd, Rs
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v->MOV_rsr(0xE, /*S=*/true, Rd_Rn, Rm_Rs, 0b0111, Rd_Rn);
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v->MOV_rsr(0xE, /*S=*/true, Rd_Rn, Rm_Rs, 0b11, Rd_Rn);
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break;
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case 8: // TST Rm, Rn
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v->TST_reg(0xE, Rd_Rn, 0, 0, Rm_Rs);
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@ -62,7 +62,9 @@ void JitX64::CompileDataProcessingHelper_Reverse(ArmReg Rn_index, ArmReg Rd_inde
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}
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X64Reg JitX64::CompileDataProcessingHelper_reg(ArmImm5 imm5, ShiftType shift, ArmReg Rm_index, bool do_shifter_carry_out) {
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// We directly put shifter_carry_out into MJitStateCFlag()
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// Caller must call reg_alloc.UnlockTemp on return value.
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// if do_shifter_carry_out,
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// we output code that calculates and puts shifter_carry_out into MJitStateCFlag().
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X64Reg tmp = reg_alloc.AllocTemp();
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@ -119,19 +121,191 @@ X64Reg JitX64::CompileDataProcessingHelper_reg(ArmImm5 imm5, ShiftType shift, Ar
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if (imm5 == 0) { //RRX
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code->BT(8, MJitStateCFlag(), Imm8(0));
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code->RCR(32, R(tmp), Imm8(1));
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if (do_shifter_carry_out)
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if (do_shifter_carry_out) {
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code->SETcc(CC_C, MJitStateCFlag());
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}
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} else {
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code->ROR(32, R(tmp), Imm8(imm5));
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if (do_shifter_carry_out)
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if (do_shifter_carry_out) {
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code->SETcc(CC_C, MJitStateCFlag());
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}
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}
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return tmp;
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}
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UNREACHABLE();
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}
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X64Reg JitX64::CompileDataProcessingHelper_rsr(ArmReg Rs_index, ShiftType shift, ArmReg Rm_index, bool do_shifter_carry_out) {
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// Caller must call reg_alloc.UnlockTemp on return value.
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// if do_shifter_carry_out,
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// we output code that calculates and puts shifter_carry_out into MJitStateCFlag().
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reg_alloc.FlushX64(RCX);
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reg_alloc.LockX64(RCX);
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X64Reg tmp = reg_alloc.AllocTemp();
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if (Rs_index != 15) {
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OpArg Rs = reg_alloc.LockArmForRead(Rs_index);
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code->MOV(32, R(RCX), Rs);
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code->AND(32, R(RCX), Imm32(0xFF));
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reg_alloc.UnlockArm(Rs_index);
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} else {
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code->MOV(32, R(RCX), Imm32(GetReg15Value() & 0xFF));
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}
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if (Rm_index != 15) {
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OpArg Rm = reg_alloc.LockArmForRead(Rm_index);
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code->MOV(32, R(tmp), Rm);
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reg_alloc.UnlockArm(Rm_index);
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} else {
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code->MOV(32, R(tmp), Imm32(GetReg15Value()));
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}
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switch (shift) {
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case 0b00: { // Logical shift left by register
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if (!do_shifter_carry_out) {
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code->SHL(32, R(tmp), R(CL));
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code->CMP(32, R(RCX), Imm8(32));
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X64Reg zero = reg_alloc.AllocTemp();
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code->MOV(32, R(zero), Imm32(0));
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code->CMOVcc(32, tmp, R(zero), CC_NB);
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reg_alloc.UnlockTemp(zero);
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} else {
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code->CMP(32, R(RCX), Imm8(32));
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auto Rs_gt32 = code->J_CC(CC_A);
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auto Rs_eq32 = code->J_CC(CC_E);
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// if (Rs & 0xFF == 0) goto end;
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code->TEST(32, R(RCX), R(RCX));
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auto Rs_zero = code->J_CC(CC_Z);
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// if (Rs & 0xFF < 32) {
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code->SHL(32, R(tmp), R(CL));
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code->SETcc(CC_C, MJitStateCFlag());
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auto jmp_to_end_1 = code->J();
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// } else if (Rs & 0xFF > 32) {
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code->SetJumpTarget(Rs_gt32);
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code->MOV(32, R(tmp), Imm32(0));
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code->MOV(8, MJitStateCFlag(), Imm8(0));
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auto jmp_to_end_2 = code->J();
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// } else if (Rs & 0xFF == 32) {
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code->SetJumpTarget(Rs_eq32);
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code->BT(32, R(tmp), Imm8(0));
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code->SETcc(CC_C, MJitStateCFlag());
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code->MOV(32, R(tmp), Imm32(0));
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// }
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code->SetJumpTarget(jmp_to_end_1);
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code->SetJumpTarget(jmp_to_end_1);
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code->SetJumpTarget(Rs_zero);
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}
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break;
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}
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case 0b01: { // Logical shift right by register
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if (!do_shifter_carry_out) {
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code->SHR(32, R(tmp), R(RCX));
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code->CMP(32, R(RCX), Imm8(32));
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X64Reg zero = reg_alloc.AllocTemp();
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code->MOV(32, R(zero), Imm32(0));
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code->CMOVcc(32, tmp, R(zero), CC_NB);
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reg_alloc.UnlockTemp(zero);
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} else {
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code->CMP(32, R(RCX), Imm8(32));
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auto Rs_gt32 = code->J_CC(CC_A);
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auto Rs_eq32 = code->J_CC(CC_E);
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// if (Rs & 0xFF == 0) goto end;
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code->TEST(32, R(RCX), R(RCX));
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auto Rs_zero = code->J_CC(CC_Z);
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// if (Rs & 0xFF < 32) {
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code->SHR(32, R(tmp), R(RCX));
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code->SETcc(CC_C, MJitStateCFlag());
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auto jmp_to_end_1 = code->J();
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// } else if (Rs & 0xFF > 32) {
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code->SetJumpTarget(Rs_gt32);
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code->MOV(32, R(tmp), Imm32(0));
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code->MOV(8, MJitStateCFlag(), Imm8(0));
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auto jmp_to_end_2 = code->J();
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// } else if (Rs & 0xFF == 32) {
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code->SetJumpTarget(Rs_eq32);
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code->BT(32, R(tmp), Imm8(31));
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code->SETcc(CC_C, MJitStateCFlag());
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code->MOV(32, R(tmp), Imm32(0));
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// }
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code->SetJumpTarget(jmp_to_end_1);
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code->SetJumpTarget(jmp_to_end_2);
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code->SetJumpTarget(Rs_zero);
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}
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break;
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}
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case 0b10: { // Arithmetic shift right by register
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if (!do_shifter_carry_out) {
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code->CMP(32, R(RCX), Imm8(31));
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auto Rs_gt31 = code->J_CC(CC_A);
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// if (Rs & 0xFF <= 31) {
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code->SAR(32, R(tmp), R(CL));
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auto jmp_to_end = code->J();
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// } else {
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code->SetJumpTarget(Rs_gt31);
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code->SAR(32, R(tmp), Imm8(31)); // Verified.
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// }
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code->SetJumpTarget(jmp_to_end);
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} else {
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code->CMP(32, R(RCX), Imm8(31));
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auto Rs_gt31 = code->J_CC(CC_A);
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// if (Rs & 0xFF == 0) goto end;
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code->TEST(32, R(RCX), R(RCX));
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auto Rs_zero = code->J_CC(CC_Z);
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// if (Rs & 0xFF <= 31) {
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code->SAR(32, R(tmp), R(CL));
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code->SETcc(CC_C, MJitStateCFlag());
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auto jmp_to_end = code->J();
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// } else if (Rs & 0xFF > 31) {
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code->SetJumpTarget(Rs_gt31);
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code->SAR(32, R(tmp), Imm8(31)); // Verified.
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code->BT(32, R(tmp), Imm8(31));
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code->SETcc(CC_C, MJitStateCFlag());
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// }
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code->SetJumpTarget(jmp_to_end);
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code->SetJumpTarget(Rs_zero);
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}
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break;
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}
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case 0b11: { // Rotate right by register
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if (!do_shifter_carry_out) {
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code->AND(32, R(RCX), Imm32(0x1F));
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code->ROR(32, R(tmp), R(CL));
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} else {
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// if (Rs & 0xFF == 0) goto end;
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code->TEST(32, R(RCX), R(RCX));
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auto Rs_zero = code->J_CC(CC_Z);
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code->AND(32, R(RCX), Imm32(0x1F));
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auto zero_1F = code->J_CC(CC_Z);
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// if (Rs & 0x1F != 0) {
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code->ROR(32, R(tmp), R(CL));
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code->SETcc(CC_C, MJitStateCFlag());
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auto jmp_to_end = code->J();
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// } else {
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code->SetJumpTarget(zero_1F);
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code->BT(32, R(tmp), Imm8(31));
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code->SETcc(CC_C, MJitStateCFlag());
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// }
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code->SetJumpTarget(jmp_to_end);
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code->SetJumpTarget(Rs_zero);
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}
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break;
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}
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default:
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UNREACHABLE();
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break;
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} // switch (shift)
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reg_alloc.UnlockX64(RCX);
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return tmp;
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}
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void JitX64::ADC_imm(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, int rotate, ArmImm8 imm8) {
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cond_manager.CompileCond((ConditionCode)cond);
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@ -174,6 +348,28 @@ void JitX64::ADC_reg(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmImm
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}
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}
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void JitX64::ADC_rsr(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmReg Rs_index, ShiftType shift, ArmReg Rm_index) {
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cond_manager.CompileCond((ConditionCode)cond);
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Gen::X64Reg tmp = CompileDataProcessingHelper_rsr(Rs_index, shift, Rm_index, false);
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CompileDataProcessingHelper(Rn_index, Rd_index, [&](X64Reg Rd) {
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code->BT(32, MJitStateCFlag(), Imm8(0));
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code->ADC(32, R(Rd), R(tmp));
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});
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reg_alloc.UnlockTemp(tmp);
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if (S) {
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UpdateFlagsZVCN();
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}
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current.arm_pc += GetInstSize();
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if (Rd_index == 15) {
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CompileReturnToDispatch();
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}
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}
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void JitX64::ADD_imm(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, int rotate, ArmImm8 imm8) {
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cond_manager.CompileCond((ConditionCode)cond);
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@ -214,6 +410,27 @@ void JitX64::ADD_reg(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmImm
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}
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}
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void JitX64::ADD_rsr(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmReg Rs_index, ShiftType shift, ArmReg Rm_index) {
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cond_manager.CompileCond((ConditionCode)cond);
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Gen::X64Reg tmp = CompileDataProcessingHelper_rsr(Rs_index, shift, Rm_index, false);
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CompileDataProcessingHelper(Rn_index, Rd_index, [&](X64Reg Rd) {
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code->ADD(32, R(Rd), R(tmp));
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});
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reg_alloc.UnlockTemp(tmp);
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if (S) {
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UpdateFlagsZVCN();
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}
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current.arm_pc += GetInstSize();
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if (Rd_index == 15) {
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CompileReturnToDispatch();
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}
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}
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void JitX64::AND_imm(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, int rotate, ArmImm8 imm8) {
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cond_manager.CompileCond((ConditionCode)cond);
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@ -249,6 +466,29 @@ void JitX64::AND_reg(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmImm
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if (S) {
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UpdateFlagsZN();
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// C updated by CompileDataProcessingHelper_reg
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}
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current.arm_pc += GetInstSize();
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if (Rd_index == 15) {
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CompileReturnToDispatch();
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}
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}
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void JitX64::AND_rsr(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmReg Rs_index, ShiftType shift, ArmReg Rm_index) {
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cond_manager.CompileCond((ConditionCode)cond);
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Gen::X64Reg tmp = CompileDataProcessingHelper_rsr(Rs_index, shift, Rm_index, S);
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CompileDataProcessingHelper(Rn_index, Rd_index, [&](X64Reg Rd) {
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code->AND(32, R(Rd), R(tmp));
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});
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reg_alloc.UnlockTemp(tmp);
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if (S) {
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UpdateFlagsZN();
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// C updated by CompileDataProcessingHelper_reg
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}
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current.arm_pc += GetInstSize();
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@ -302,6 +542,29 @@ void JitX64::BIC_reg(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmImm
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}
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}
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void JitX64::BIC_rsr(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmReg Rs_index, ShiftType shift, ArmReg Rm_index) {
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cond_manager.CompileCond((ConditionCode)cond);
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Gen::X64Reg tmp = CompileDataProcessingHelper_rsr(Rs_index, shift, Rm_index, S);
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CompileDataProcessingHelper(Rn_index, Rd_index, [&](X64Reg Rd) {
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// TODO: Use ANDN instead.
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code->NOT(32, R(tmp));
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code->AND(32, R(Rd), R(tmp));
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});
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reg_alloc.UnlockTemp(tmp);
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if (S) {
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UpdateFlagsZN();
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}
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current.arm_pc += GetInstSize();
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if (Rd_index == 15) {
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CompileReturnToDispatch();
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}
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}
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void JitX64::CMN_imm(Cond cond, ArmReg Rn_index, int rotate, ArmImm8 imm8) {
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cond_manager.CompileCond((ConditionCode)cond);
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@ -345,6 +608,26 @@ void JitX64::CMN_reg(Cond cond, ArmReg Rn_index, ArmImm5 imm5, ShiftType shift,
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current.arm_pc += GetInstSize();
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}
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void JitX64::CMN_rsr(Cond cond, ArmReg Rn_index, ArmReg Rs_index, ShiftType shift, ArmReg Rm_index) {
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cond_manager.CompileCond((ConditionCode)cond);
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Gen::X64Reg tmp = CompileDataProcessingHelper_rsr(Rs_index, shift, Rm_index, false);
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if (Rn_index != 15) {
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OpArg Rn = reg_alloc.LockArmForRead(Rn_index);
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code->ADD(32, R(tmp), Rn);
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reg_alloc.UnlockArm(Rn_index);
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} else {
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code->ADD(32, R(tmp), Imm32(GetReg15Value()));
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}
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reg_alloc.UnlockTemp(tmp);
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UpdateFlagsZVCN();
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current.arm_pc += GetInstSize();
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}
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void JitX64::CMP_imm(Cond cond, ArmReg Rn_index, int rotate, ArmImm8 imm8) {
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cond_manager.CompileCond((ConditionCode)cond);
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@ -393,6 +676,31 @@ void JitX64::CMP_reg(Cond cond, ArmReg Rn_index, ArmImm5 imm5, ShiftType shift,
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current.arm_pc += GetInstSize();
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}
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void JitX64::CMP_rsr(Cond cond, ArmReg Rn_index, ArmReg Rs_index, ShiftType shift, ArmReg Rm_index) {
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cond_manager.CompileCond((ConditionCode)cond);
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Gen::X64Reg tmp = CompileDataProcessingHelper_rsr(Rs_index, shift, Rm_index, false);
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if (Rn_index != 15) {
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OpArg Rn = reg_alloc.LockArmForRead(Rn_index);
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code->CMP(32, Rn, R(tmp));
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reg_alloc.UnlockArm(Rn_index);
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} else {
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// TODO: Optimize this
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X64Reg tmp2 = reg_alloc.AllocTemp();
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code->MOV(32, R(tmp2), Imm32(GetReg15Value()));
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code->CMP(32, R(tmp2), R(tmp));
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reg_alloc.UnlockTemp(tmp2);
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}
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reg_alloc.UnlockTemp(tmp);
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UpdateFlagsC_complement();
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UpdateFlagsZVN();
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current.arm_pc += GetInstSize();
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}
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void JitX64::EOR_imm(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, int rotate, ArmImm8 imm8) {
|
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cond_manager.CompileCond((ConditionCode)cond);
|
||||
|
||||
@ -436,6 +744,27 @@ void JitX64::EOR_reg(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmImm
|
||||
}
|
||||
}
|
||||
|
||||
void JitX64::EOR_rsr(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmReg Rs_index, ShiftType shift, ArmReg Rm_index) {
|
||||
cond_manager.CompileCond((ConditionCode)cond);
|
||||
|
||||
Gen::X64Reg tmp = CompileDataProcessingHelper_rsr(Rs_index, shift, Rm_index, S);
|
||||
|
||||
CompileDataProcessingHelper(Rn_index, Rd_index, [&](X64Reg Rd) {
|
||||
code->XOR(32, R(Rd), R(tmp));
|
||||
});
|
||||
|
||||
reg_alloc.UnlockTemp(tmp);
|
||||
|
||||
if (S) {
|
||||
UpdateFlagsZN();
|
||||
}
|
||||
|
||||
current.arm_pc += GetInstSize();
|
||||
if (Rd_index == 15) {
|
||||
CompileReturnToDispatch();
|
||||
}
|
||||
}
|
||||
|
||||
void JitX64::MOV_imm(Cond cond, bool S, ArmReg Rd_index, int rotate, ArmImm8 imm8) {
|
||||
cond_manager.CompileCond((ConditionCode)cond);
|
||||
|
||||
@ -483,6 +812,28 @@ void JitX64::MOV_reg(Cond cond, bool S, ArmReg Rd_index, ArmImm5 imm5, ShiftType
|
||||
}
|
||||
}
|
||||
|
||||
void JitX64::MOV_rsr(Cond cond, bool S, ArmReg Rd_index, ArmReg Rs_index, ShiftType shift, ArmReg Rm_index) {
|
||||
cond_manager.CompileCond((ConditionCode)cond);
|
||||
|
||||
Gen::X64Reg tmp = CompileDataProcessingHelper_rsr(Rs_index, shift, Rm_index, S);
|
||||
|
||||
Gen::OpArg Rd = reg_alloc.LockArmForWrite(Rd_index);
|
||||
code->MOV(32, Rd, R(tmp));
|
||||
reg_alloc.UnlockArm(Rd_index);
|
||||
|
||||
if (S) {
|
||||
code->CMP(32, R(tmp), Imm32(0));
|
||||
UpdateFlagsZN();
|
||||
}
|
||||
|
||||
reg_alloc.UnlockTemp(tmp);
|
||||
|
||||
current.arm_pc += GetInstSize();
|
||||
if (Rd_index == 15) {
|
||||
CompileReturnToDispatch();
|
||||
}
|
||||
}
|
||||
|
||||
void JitX64::MVN_imm(Cond cond, bool S, ArmReg Rd_index, int rotate, ArmImm8 imm8) {
|
||||
cond_manager.CompileCond((ConditionCode)cond);
|
||||
|
||||
@ -531,6 +882,29 @@ void JitX64::MVN_reg(Cond cond, bool S, ArmReg Rd_index, ArmImm5 imm5, ShiftType
|
||||
}
|
||||
}
|
||||
|
||||
void JitX64::MVN_rsr(Cond cond, bool S, ArmReg Rd_index, ArmReg Rs_index, ShiftType shift, ArmReg Rm_index) {
|
||||
cond_manager.CompileCond((ConditionCode)cond);
|
||||
|
||||
Gen::X64Reg tmp = CompileDataProcessingHelper_rsr(Rs_index, shift, Rm_index, S);
|
||||
code->NOT(32, R(tmp));
|
||||
|
||||
Gen::OpArg Rd = reg_alloc.LockArmForWrite(Rd_index);
|
||||
code->MOV(32, Rd, R(tmp));
|
||||
reg_alloc.UnlockArm(Rd_index);
|
||||
|
||||
if (S) {
|
||||
code->CMP(32, R(tmp), Imm32(0));
|
||||
UpdateFlagsZN();
|
||||
}
|
||||
|
||||
reg_alloc.UnlockTemp(tmp);
|
||||
|
||||
current.arm_pc += GetInstSize();
|
||||
if (Rd_index == 15) {
|
||||
CompileReturnToDispatch();
|
||||
}
|
||||
}
|
||||
|
||||
void JitX64::ORR_imm(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, int rotate, ArmImm8 imm8) {
|
||||
cond_manager.CompileCond((ConditionCode)cond);
|
||||
|
||||
@ -574,6 +948,27 @@ void JitX64::ORR_reg(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmImm
|
||||
}
|
||||
}
|
||||
|
||||
void JitX64::ORR_rsr(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmReg Rs_index, ShiftType shift, ArmReg Rm_index) {
|
||||
cond_manager.CompileCond((ConditionCode)cond);
|
||||
|
||||
Gen::X64Reg tmp = CompileDataProcessingHelper_rsr(Rs_index, shift, Rm_index, S);
|
||||
|
||||
CompileDataProcessingHelper(Rn_index, Rd_index, [&](X64Reg Rd) {
|
||||
code->OR(32, R(Rd), R(tmp));
|
||||
});
|
||||
|
||||
reg_alloc.UnlockTemp(tmp);
|
||||
|
||||
if (S) {
|
||||
UpdateFlagsZN();
|
||||
}
|
||||
|
||||
current.arm_pc += GetInstSize();
|
||||
if (Rd_index == 15) {
|
||||
CompileReturnToDispatch();
|
||||
}
|
||||
}
|
||||
|
||||
void JitX64::RSB_imm(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, int rotate, ArmImm8 imm8) {
|
||||
cond_manager.CompileCond((ConditionCode)cond);
|
||||
|
||||
@ -632,6 +1027,36 @@ void JitX64::RSB_reg(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmImm
|
||||
}
|
||||
}
|
||||
|
||||
void JitX64::RSB_rsr(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmReg Rs_index, ShiftType shift, ArmReg Rm_index) {
|
||||
cond_manager.CompileCond((ConditionCode)cond);
|
||||
|
||||
Gen::X64Reg tmp = CompileDataProcessingHelper_rsr(Rs_index, shift, Rm_index, false);
|
||||
|
||||
CompileDataProcessingHelper_Reverse(Rn_index, Rd_index, [&](X64Reg Rd) {
|
||||
code->MOV(32, R(Rd), R(tmp));
|
||||
|
||||
if (Rn_index == 15) {
|
||||
code->SUB(32, R(Rd), Imm32(GetReg15Value()));
|
||||
} else {
|
||||
Gen::OpArg Rn = reg_alloc.LockArmForRead(Rn_index);
|
||||
code->SUB(32, R(Rd), Rn);
|
||||
reg_alloc.UnlockArm(Rn_index);
|
||||
}
|
||||
});
|
||||
|
||||
reg_alloc.UnlockTemp(tmp);
|
||||
|
||||
if (S) {
|
||||
UpdateFlagsZVN();
|
||||
UpdateFlagsC_complement();
|
||||
}
|
||||
|
||||
current.arm_pc += GetInstSize();
|
||||
if (Rd_index == 15) {
|
||||
CompileReturnToDispatch();
|
||||
}
|
||||
}
|
||||
|
||||
void JitX64::RSC_imm(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, int rotate, ArmImm8 imm8) {
|
||||
cond_manager.CompileCond((ConditionCode)cond);
|
||||
|
||||
@ -696,6 +1121,39 @@ void JitX64::RSC_reg(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmImm
|
||||
}
|
||||
}
|
||||
|
||||
void JitX64::RSC_rsr(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmReg Rs_index, ShiftType shift, ArmReg Rm_index) {
|
||||
cond_manager.CompileCond((ConditionCode)cond);
|
||||
|
||||
Gen::X64Reg tmp = CompileDataProcessingHelper_rsr(Rs_index, shift, Rm_index, false);
|
||||
|
||||
CompileDataProcessingHelper_Reverse(Rn_index, Rd_index, [&](X64Reg Rd) {
|
||||
code->MOV(32, R(Rd), R(tmp));
|
||||
|
||||
code->BT(32, MJitStateCFlag(), Imm8(0));
|
||||
code->CMC();
|
||||
|
||||
if (Rn_index == 15) {
|
||||
code->SBB(32, R(Rd), Imm32(GetReg15Value()));
|
||||
} else {
|
||||
Gen::OpArg Rn = reg_alloc.LockArmForRead(Rn_index);
|
||||
code->SBB(32, R(Rd), Rn);
|
||||
reg_alloc.UnlockArm(Rn_index);
|
||||
}
|
||||
});
|
||||
|
||||
reg_alloc.UnlockTemp(tmp);
|
||||
|
||||
if (S) {
|
||||
UpdateFlagsZVN();
|
||||
UpdateFlagsC_complement();
|
||||
}
|
||||
|
||||
current.arm_pc += GetInstSize();
|
||||
if (Rd_index == 15) {
|
||||
CompileReturnToDispatch();
|
||||
}
|
||||
}
|
||||
|
||||
void JitX64::SBC_imm(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, int rotate, ArmImm8 imm8) {
|
||||
cond_manager.CompileCond((ConditionCode)cond);
|
||||
|
||||
@ -742,6 +1200,30 @@ void JitX64::SBC_reg(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmImm
|
||||
}
|
||||
}
|
||||
|
||||
void JitX64::SBC_rsr(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmReg Rs_index, ShiftType shift, ArmReg Rm_index) {
|
||||
cond_manager.CompileCond((ConditionCode)cond);
|
||||
|
||||
Gen::X64Reg tmp = CompileDataProcessingHelper_rsr(Rs_index, shift, Rm_index, false);
|
||||
|
||||
CompileDataProcessingHelper(Rn_index, Rd_index, [&](X64Reg Rd) {
|
||||
code->BT(32, MJitStateCFlag(), Imm8(0));
|
||||
code->CMC();
|
||||
code->SBB(32, R(Rd), R(tmp));
|
||||
});
|
||||
|
||||
reg_alloc.UnlockTemp(tmp);
|
||||
|
||||
if (S) {
|
||||
UpdateFlagsZVN();
|
||||
UpdateFlagsC_complement();
|
||||
}
|
||||
|
||||
current.arm_pc += GetInstSize();
|
||||
if (Rd_index == 15) {
|
||||
CompileReturnToDispatch();
|
||||
}
|
||||
}
|
||||
|
||||
void JitX64::SUB_imm(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, int rotate, ArmImm8 imm8) {
|
||||
cond_manager.CompileCond((ConditionCode)cond);
|
||||
|
||||
@ -784,6 +1266,29 @@ void JitX64::SUB_reg(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmImm
|
||||
}
|
||||
}
|
||||
|
||||
void JitX64::SUB_rsr(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmReg Rs_index, ShiftType shift, ArmReg Rm_index) {
|
||||
cond_manager.CompileCond((ConditionCode)cond);
|
||||
|
||||
Gen::X64Reg tmp = CompileDataProcessingHelper_rsr(Rs_index, shift, Rm_index, false);
|
||||
|
||||
CompileDataProcessingHelper(Rn_index, Rd_index, [&](X64Reg Rd) {
|
||||
code->SUB(32, R(Rd), R(tmp));
|
||||
});
|
||||
|
||||
reg_alloc.UnlockTemp(tmp);
|
||||
|
||||
if (S) {
|
||||
UpdateFlagsZVN();
|
||||
UpdateFlagsC_complement();
|
||||
}
|
||||
|
||||
current.arm_pc += GetInstSize();
|
||||
if (Rd_index == 15) {
|
||||
CompileReturnToDispatch();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void JitX64::TEQ_imm(Cond cond, ArmReg Rn_index, int rotate, ArmImm8 imm8) {
|
||||
cond_manager.CompileCond((ConditionCode)cond);
|
||||
|
||||
@ -831,6 +1336,26 @@ void JitX64::TEQ_reg(Cond cond, ArmReg Rn_index, ArmImm5 imm5, ShiftType shift,
|
||||
current.arm_pc += GetInstSize();
|
||||
}
|
||||
|
||||
void JitX64::TEQ_rsr(Cond cond, ArmReg Rn_index, ArmReg Rs_index, ShiftType shift, ArmReg Rm_index) {
|
||||
cond_manager.CompileCond((ConditionCode)cond);
|
||||
|
||||
Gen::X64Reg tmp = CompileDataProcessingHelper_rsr(Rs_index, shift, Rm_index, true);
|
||||
|
||||
if (Rn_index == 15) {
|
||||
code->XOR(32, R(tmp), Imm32(GetReg15Value()));
|
||||
} else {
|
||||
Gen::OpArg Rn = reg_alloc.LockArmForRead(Rn_index);
|
||||
code->XOR(32, R(tmp), Rn);
|
||||
reg_alloc.UnlockArm(Rn_index);
|
||||
}
|
||||
|
||||
reg_alloc.UnlockTemp(tmp);
|
||||
|
||||
UpdateFlagsZN();
|
||||
|
||||
current.arm_pc += GetInstSize();
|
||||
}
|
||||
|
||||
void JitX64::TST_imm(Cond cond, ArmReg Rn_index, int rotate, ArmImm8 imm8) {
|
||||
cond_manager.CompileCond((ConditionCode)cond);
|
||||
|
||||
@ -881,21 +1406,24 @@ void JitX64::TST_reg(Cond cond, ArmReg Rn_index, ArmImm5 imm5, ShiftType shift,
|
||||
current.arm_pc += GetInstSize();
|
||||
}
|
||||
|
||||
void JitX64::ADC_rsr(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmReg Rs_index, ShiftType shift, ArmReg Rm_index) { CompileInterpretInstruction(); }
|
||||
void JitX64::ADD_rsr(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmReg Rs_index, ShiftType shift, ArmReg Rm_index) { CompileInterpretInstruction(); }
|
||||
void JitX64::AND_rsr(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmReg Rs_index, ShiftType shift, ArmReg Rm_index) { CompileInterpretInstruction(); }
|
||||
void JitX64::BIC_rsr(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmReg Rs_index, ShiftType shift, ArmReg Rm_index) { CompileInterpretInstruction(); }
|
||||
void JitX64::CMN_rsr(Cond cond, ArmReg Rn_index, ArmReg Rs_index, ShiftType shift, ArmReg Rm_index) { CompileInterpretInstruction(); }
|
||||
void JitX64::CMP_rsr(Cond cond, ArmReg Rn_index, ArmReg Rs_index, ShiftType shift, ArmReg Rm_index) { CompileInterpretInstruction(); }
|
||||
void JitX64::EOR_rsr(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmReg Rs_index, ShiftType shift, ArmReg Rm_index) { CompileInterpretInstruction(); }
|
||||
void JitX64::MOV_rsr(Cond cond, bool S, ArmReg Rd_index, ArmReg Rs_index, ShiftType shift, ArmReg Rm_index) { CompileInterpretInstruction(); }
|
||||
void JitX64::MVN_rsr(Cond cond, bool S, ArmReg Rd_index, ArmReg Rs_index, ShiftType shift, ArmReg Rm_index) { CompileInterpretInstruction(); }
|
||||
void JitX64::ORR_rsr(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmReg Rs_index, ShiftType shift, ArmReg Rm_index) { CompileInterpretInstruction(); }
|
||||
void JitX64::RSB_rsr(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmReg Rs_index, ShiftType shift, ArmReg Rm_index) { CompileInterpretInstruction(); }
|
||||
void JitX64::RSC_rsr(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmReg Rs_index, ShiftType shift, ArmReg Rm_index) { CompileInterpretInstruction(); }
|
||||
void JitX64::SBC_rsr(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmReg Rs_index, ShiftType shift, ArmReg Rm_index) { CompileInterpretInstruction(); }
|
||||
void JitX64::SUB_rsr(Cond cond, bool S, ArmReg Rn_index, ArmReg Rd_index, ArmReg Rs_index, ShiftType shift, ArmReg Rm_index) { CompileInterpretInstruction(); }
|
||||
void JitX64::TEQ_rsr(Cond cond, ArmReg Rn_index, ArmReg Rs_index, ShiftType shift, ArmReg Rm_index) { CompileInterpretInstruction(); }
|
||||
void JitX64::TST_rsr(Cond cond, ArmReg Rn_index, ArmReg Rs_index, ShiftType shift, ArmReg Rm_index) { CompileInterpretInstruction(); }
|
||||
void JitX64::TST_rsr(Cond cond, ArmReg Rn_index, ArmReg Rs_index, ShiftType shift, ArmReg Rm_index) {
|
||||
cond_manager.CompileCond((ConditionCode)cond);
|
||||
|
||||
Gen::X64Reg tmp = CompileDataProcessingHelper_rsr(Rs_index, shift, Rm_index, true);
|
||||
|
||||
if (Rn_index == 15) {
|
||||
code->TEST(32, R(tmp), Imm32(GetReg15Value()));
|
||||
} else {
|
||||
OpArg Rn = reg_alloc.LockArmForRead(Rn_index);
|
||||
code->TEST(32, R(tmp), Rn);
|
||||
reg_alloc.UnlockArm(Rn_index);
|
||||
}
|
||||
|
||||
reg_alloc.UnlockTemp(tmp);
|
||||
|
||||
UpdateFlagsZN();
|
||||
|
||||
current.arm_pc += GetInstSize();
|
||||
}
|
||||
|
||||
} // namespace JitX64
|
||||
|
||||
@ -161,7 +161,7 @@ private:
|
||||
void CompileDataProcessingHelper(ArmReg Rn_index, ArmReg Rd_index, std::function<void(Gen::X64Reg)> body);
|
||||
void CompileDataProcessingHelper_Reverse(ArmReg Rn_index, ArmReg Rd_index, std::function<void(Gen::X64Reg)> body);
|
||||
Gen::X64Reg CompileDataProcessingHelper_reg(ArmImm5 imm5, ShiftType shift, ArmReg Rm, bool do_shifter_carry_out);
|
||||
Gen::X64Reg CompileDataProcessingHelper_rsr(ArmReg Rs, ShiftType shift, ArmReg Rm);
|
||||
Gen::X64Reg CompileDataProcessingHelper_rsr(ArmReg Rs, ShiftType shift, ArmReg Rm, bool do_shifter_carry_out);
|
||||
void ADC_imm(Cond cond, bool S, ArmReg Rn, ArmReg Rd, int rotate, ArmImm8 imm8) override;
|
||||
void ADC_reg(Cond cond, bool S, ArmReg Rn, ArmReg Rd, ArmImm5 imm5, ShiftType shift, ArmReg Rm) override;
|
||||
void ADC_rsr(Cond cond, bool S, ArmReg Rn, ArmReg Rd, ArmReg Rs, ShiftType shift, ArmReg Rm) override;
|
||||
|
||||
@ -87,7 +87,7 @@ TEST_CASE("Fuzz ARM data processing instructions", "[JitX64]") {
|
||||
}
|
||||
|
||||
SECTION("long blocks") {
|
||||
FuzzJit(1024, 1025, 50, instruction_select_without_R15);
|
||||
FuzzJit(1024, 1025, 200, instruction_select_without_R15);
|
||||
}
|
||||
|
||||
auto instruction_select_only_R15 = [&]() -> u32 {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user