mirror of
https://github.com/citra-emu/citra.git
synced 2024-12-20 12:00:08 +00:00
arm: added option to prepare CPU core (while mid-instruction) for thread reschedule
This commit is contained in:
parent
15c7d81706
commit
e8a17ee6fd
@ -89,6 +89,9 @@ public:
|
|||||||
*/
|
*/
|
||||||
virtual void LoadContext(const ThreadContext& ctx) = 0;
|
virtual void LoadContext(const ThreadContext& ctx) = 0;
|
||||||
|
|
||||||
|
/// Prepare core for thread reschedule (if needed to correctly handle state)
|
||||||
|
virtual void PrepareReschedule() = 0;
|
||||||
|
|
||||||
/// Getter for num_instructions
|
/// Getter for num_instructions
|
||||||
u64 GetNumInstructions() {
|
u64 GetNumInstructions() {
|
||||||
return num_instructions;
|
return num_instructions;
|
||||||
|
@ -140,3 +140,8 @@ void ARM_Interpreter::LoadContext(const ThreadContext& ctx) {
|
|||||||
state->Reg[15] = ctx.pc;
|
state->Reg[15] = ctx.pc;
|
||||||
state->NextInstr = RESUME;
|
state->NextInstr = RESUME;
|
||||||
}
|
}
|
||||||
|
|
||||||
|
/// Prepare core for thread reschedule (if needed to correctly handle state)
|
||||||
|
void ARM_Interpreter::PrepareReschedule() {
|
||||||
|
state->NumInstrsToExecute = 0;
|
||||||
|
}
|
||||||
|
@ -72,6 +72,9 @@ public:
|
|||||||
*/
|
*/
|
||||||
void LoadContext(const ThreadContext& ctx);
|
void LoadContext(const ThreadContext& ctx);
|
||||||
|
|
||||||
|
/// Prepare core for thread reschedule (if needed to correctly handle state)
|
||||||
|
void PrepareReschedule();
|
||||||
|
|
||||||
protected:
|
protected:
|
||||||
|
|
||||||
/**
|
/**
|
||||||
|
Loading…
Reference in New Issue
Block a user