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https://github.com/citra-emu/citra.git
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Rename GPU::Regs::FramebufferFormat to PixelFormat
This name better represents what the enum does, and is less overloaded in the context. (The whole register the enum is part of is also called 'format'.)
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@ -90,7 +90,7 @@ inline void Write(u32 addr, const T data) {
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} source_color = { 0, 0, 0, 0 };
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} source_color = { 0, 0, 0, 0 };
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switch (config.input_format) {
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switch (config.input_format) {
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case Regs::FramebufferFormat::RGBA8:
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case Regs::PixelFormat::RGBA8:
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{
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{
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// TODO: Most likely got the component order messed up.
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// TODO: Most likely got the component order messed up.
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u8* srcptr = source_pointer + x * 4 + y * config.input_width * 4;
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u8* srcptr = source_pointer + x * 4 + y * config.input_width * 4;
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@ -107,7 +107,7 @@ inline void Write(u32 addr, const T data) {
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}
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}
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switch (config.output_format) {
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switch (config.output_format) {
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/*case Regs::FramebufferFormat::RGBA8:
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/*case Regs::PixelFormat::RGBA8:
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{
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{
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// TODO: Untested
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// TODO: Untested
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u8* dstptr = (u32*)(dest_pointer + x * 4 + y * config.output_width * 4);
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u8* dstptr = (u32*)(dest_pointer + x * 4 + y * config.output_width * 4);
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@ -118,7 +118,7 @@ inline void Write(u32 addr, const T data) {
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break;
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break;
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}*/
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}*/
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case Regs::FramebufferFormat::RGB8:
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case Regs::PixelFormat::RGB8:
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{
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{
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// TODO: Most likely got the component order messed up.
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// TODO: Most likely got the component order messed up.
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u8* dstptr = dest_pointer + x * 3 + y * config.output_width * 3;
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u8* dstptr = dest_pointer + x * 3 + y * config.output_width * 3;
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@ -220,13 +220,13 @@ void Init() {
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framebuffer_top.width = 240;
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framebuffer_top.width = 240;
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framebuffer_top.height = 400;
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framebuffer_top.height = 400;
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framebuffer_top.stride = 3 * 240;
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framebuffer_top.stride = 3 * 240;
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framebuffer_top.color_format = Regs::FramebufferFormat::RGB8;
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framebuffer_top.color_format = Regs::PixelFormat::RGB8;
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framebuffer_top.active_fb = 0;
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framebuffer_top.active_fb = 0;
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framebuffer_sub.width = 240;
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framebuffer_sub.width = 240;
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framebuffer_sub.height = 320;
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framebuffer_sub.height = 320;
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framebuffer_sub.stride = 3 * 240;
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framebuffer_sub.stride = 3 * 240;
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framebuffer_sub.color_format = Regs::FramebufferFormat::RGB8;
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framebuffer_sub.color_format = Regs::PixelFormat::RGB8;
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framebuffer_sub.active_fb = 0;
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framebuffer_sub.active_fb = 0;
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NOTICE_LOG(GPU, "initialized OK");
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NOTICE_LOG(GPU, "initialized OK");
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@ -56,7 +56,7 @@ struct Regs {
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"Structure size and register block length don't match")
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"Structure size and register block length don't match")
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#endif
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#endif
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enum class FramebufferFormat : u32 {
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enum class PixelFormat : u32 {
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RGBA8 = 0,
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RGBA8 = 0,
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RGB8 = 1,
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RGB8 = 1,
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RGB565 = 2,
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RGB565 = 2,
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@ -84,8 +84,8 @@ struct Regs {
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INSERT_PADDING_WORDS(0x10b);
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INSERT_PADDING_WORDS(0x10b);
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struct {
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struct FramebufferConfig {
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using Format = Regs::FramebufferFormat;
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using Format = Regs::PixelFormat;
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union {
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union {
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u32 size;
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u32 size;
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@ -130,7 +130,7 @@ struct Regs {
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INSERT_PADDING_WORDS(0x169);
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INSERT_PADDING_WORDS(0x169);
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struct {
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struct {
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using Format = Regs::FramebufferFormat;
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using Format = Regs::PixelFormat;
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u32 input_address;
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u32 input_address;
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u32 output_address;
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u32 output_address;
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