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citra-qt/command list: Add mask column
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cd06f5cedb
commit
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@ -175,29 +175,29 @@ int GPUCommandListModel::rowCount(const QModelIndex& parent) const {
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}
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int GPUCommandListModel::columnCount(const QModelIndex& parent) const {
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return 3;
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return 4;
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}
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QVariant GPUCommandListModel::data(const QModelIndex& index, int role) const {
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if (!index.isValid())
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return QVariant();
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const auto& writes = pica_trace.writes;
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const Pica::CommandProcessor::CommandHeader cmd{writes[index.row()].Id()};
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const u32 val{writes[index.row()].Value()};
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const auto& write = pica_trace.writes[index.row()];
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if (role == Qt::DisplayRole) {
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QString content;
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switch ( index.column() ) {
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case 0:
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return QString::fromLatin1(Pica::Regs::GetCommandName(cmd.cmd_id).c_str());
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return QString::fromLatin1(Pica::Regs::GetCommandName(write.cmd_id).c_str());
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case 1:
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return QString("%1").arg(cmd.cmd_id, 3, 16, QLatin1Char('0'));
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return QString("%1").arg(write.cmd_id, 3, 16, QLatin1Char('0'));
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case 2:
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return QString("%1").arg(val, 8, 16, QLatin1Char('0'));
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return QString("%1").arg(write.mask, 4, 2, QLatin1Char('0'));
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case 3:
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return QString("%1").arg(write.value, 8, 16, QLatin1Char('0'));
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}
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} else if (role == CommandIdRole) {
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return QVariant::fromValue<int>(cmd.cmd_id.Value());
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return QVariant::fromValue<int>(write.cmd_id);
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}
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return QVariant();
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@ -213,6 +213,8 @@ QVariant GPUCommandListModel::headerData(int section, Qt::Orientation orientatio
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case 1:
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return tr("Register");
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case 2:
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return tr("Mask");
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case 3:
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return tr("New Value");
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}
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@ -35,7 +35,15 @@ static u32 default_attr_write_buffer[3];
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Common::Profiling::TimingCategory category_drawing("Drawing");
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static inline void WritePicaReg(u32 id, u32 value, u32 mask) {
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// Expand a 4-bit mask to 4-byte mask, e.g. 0b0101 -> 0x00FF00FF
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static const u32 expand_bits_to_bytes[] = {
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0x00000000, 0x000000ff, 0x0000ff00, 0x0000ffff,
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0x00ff0000, 0x00ff00ff, 0x00ffff00, 0x00ffffff,
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0xff000000, 0xff0000ff, 0xff00ff00, 0xff00ffff,
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0xffff0000, 0xffff00ff, 0xffffff00, 0xffffffff
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};
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static void WritePicaReg(u32 id, u32 value, u32 mask) {
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auto& regs = g_state.regs;
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if (id >= regs.NumIds())
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@ -47,13 +55,16 @@ static inline void WritePicaReg(u32 id, u32 value, u32 mask) {
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// TODO: Figure out how register masking acts on e.g. vs.uniform_setup.set_value
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u32 old_value = regs[id];
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regs[id] = (old_value & ~mask) | (value & mask);
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const u32 write_mask = expand_bits_to_bytes[mask];
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regs[id] = (old_value & ~write_mask) | (value & write_mask);
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DebugUtils::OnPicaRegWrite({ (u16)id, (u16)mask, regs[id] });
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if (g_debug_context)
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g_debug_context->OnEvent(DebugContext::Event::PicaCommandLoaded, reinterpret_cast<void*>(&id));
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DebugUtils::OnPicaRegWrite(id, regs[id]);
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switch(id) {
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// Trigger IRQ
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case PICA_REG_INDEX(trigger_irq):
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@ -436,13 +447,6 @@ void ProcessCommandList(const u32* list, u32 size) {
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g_state.cmd_list.length = size / sizeof(u32);
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while (g_state.cmd_list.current_ptr < g_state.cmd_list.head_ptr + g_state.cmd_list.length) {
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// Expand a 4-bit mask to 4-byte mask, e.g. 0b0101 -> 0x00FF00FF
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static const u32 expand_bits_to_bytes[] = {
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0x00000000, 0x000000ff, 0x0000ff00, 0x0000ffff,
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0x00ff0000, 0x00ff00ff, 0x00ffff00, 0x00ffffff,
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0xff000000, 0xff0000ff, 0xff00ff00, 0xff00ffff,
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0xffff0000, 0xffff00ff, 0xffffff00, 0xffffffff
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};
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// Align read pointer to 8 bytes
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if ((g_state.cmd_list.head_ptr - g_state.cmd_list.current_ptr) % 2 != 0)
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@ -450,14 +454,13 @@ void ProcessCommandList(const u32* list, u32 size) {
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u32 value = *g_state.cmd_list.current_ptr++;
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const CommandHeader header = { *g_state.cmd_list.current_ptr++ };
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const u32 write_mask = expand_bits_to_bytes[header.parameter_mask];
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u32 cmd = header.cmd_id;
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WritePicaReg(cmd, value, write_mask);
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WritePicaReg(cmd, value, header.parameter_mask);
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for (unsigned i = 0; i < header.extra_data_length; ++i) {
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u32 cmd = header.cmd_id + (header.group_commands ? i + 1 : 0);
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WritePicaReg(cmd, *g_state.cmd_list.current_ptr++, write_mask);
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WritePicaReg(cmd, *g_state.cmd_list.current_ptr++, header.parameter_mask);
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}
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}
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}
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@ -280,7 +280,7 @@ bool IsPicaTracing()
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return is_pica_tracing != 0;
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}
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void OnPicaRegWrite(u32 id, u32 value)
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void OnPicaRegWrite(PicaTrace::Write write)
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{
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// Double check for is_pica_tracing to avoid pointless locking overhead
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if (!is_pica_tracing)
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@ -291,7 +291,7 @@ void OnPicaRegWrite(u32 id, u32 value)
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if (!is_pica_tracing)
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return;
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pica_trace->writes.emplace_back(id, value);
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pica_trace->writes.push_back(write);
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}
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std::unique_ptr<PicaTrace> FinishPicaTracing()
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@ -183,21 +183,17 @@ void DumpShader(const u32* binary_data, u32 binary_size, const u32* swizzle_data
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// Utility class to log Pica commands.
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struct PicaTrace {
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struct Write : public std::pair<u32,u32> {
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Write(u32 id, u32 value) : std::pair<u32,u32>(id, value) {}
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u32& Id() { return first; }
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const u32& Id() const { return first; }
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u32& Value() { return second; }
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const u32& Value() const { return second; }
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struct Write {
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u16 cmd_id;
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u16 mask;
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u32 value;
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};
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std::vector<Write> writes;
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};
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void StartPicaTracing();
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bool IsPicaTracing();
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void OnPicaRegWrite(u32 id, u32 value);
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void OnPicaRegWrite(PicaTrace::Write write);
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std::unique_ptr<PicaTrace> FinishPicaTracing();
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struct TextureInfo {
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