From d7898e269bd4d7e4abcb6510ae6b2830d07b22e8 Mon Sep 17 00:00:00 2001
From: wwylele <wwylele@gmail.com>
Date: Mon, 27 Jun 2016 21:38:49 +0300
Subject: [PATCH] ARM: add ClearInstructionCache function

---
 src/core/arm/arm_interface.h       | 3 +++
 src/core/arm/dyncom/arm_dyncom.cpp | 6 ++++++
 src/core/arm/dyncom/arm_dyncom.h   | 2 ++
 3 files changed, 11 insertions(+)

diff --git a/src/core/arm/arm_interface.h b/src/core/arm/arm_interface.h
index d8abe5aeb..de5e9c8fa 100644
--- a/src/core/arm/arm_interface.h
+++ b/src/core/arm/arm_interface.h
@@ -32,6 +32,9 @@ public:
         Run(1);
     }
 
+    /// Clear all instruction cache
+    virtual void ClearInstructionCache() = 0;
+
     /**
      * Set the Program Counter to an address
      * @param addr Address to set PC to
diff --git a/src/core/arm/dyncom/arm_dyncom.cpp b/src/core/arm/dyncom/arm_dyncom.cpp
index 13492a08b..ab77da965 100644
--- a/src/core/arm/dyncom/arm_dyncom.cpp
+++ b/src/core/arm/dyncom/arm_dyncom.cpp
@@ -12,6 +12,7 @@
 #include "core/arm/dyncom/arm_dyncom.h"
 #include "core/arm/dyncom/arm_dyncom_interpreter.h"
 #include "core/arm/dyncom/arm_dyncom_run.h"
+#include "core/arm/dyncom/arm_dyncom_trans.h"
 
 #include "core/core.h"
 #include "core/core_timing.h"
@@ -23,6 +24,11 @@ ARM_DynCom::ARM_DynCom(PrivilegeMode initial_mode) {
 ARM_DynCom::~ARM_DynCom() {
 }
 
+void ARM_DynCom::ClearInstructionCache() {
+    state->instruction_cache.clear();
+    trans_cache_buf_top = 0;
+}
+
 void ARM_DynCom::SetPC(u32 pc) {
     state->Reg[15] = pc;
 }
diff --git a/src/core/arm/dyncom/arm_dyncom.h b/src/core/arm/dyncom/arm_dyncom.h
index 3664fd728..e763abc24 100644
--- a/src/core/arm/dyncom/arm_dyncom.h
+++ b/src/core/arm/dyncom/arm_dyncom.h
@@ -21,6 +21,8 @@ public:
     ARM_DynCom(PrivilegeMode initial_mode);
     ~ARM_DynCom();
 
+    void ClearInstructionCache() override;
+
     void SetPC(u32 pc) override;
     u32 GetPC() const override;
     u32 GetReg(int index) const override;