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tests/JitX64: Improve tests
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MerryMage
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550fef508e
commit
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@ -39,6 +39,113 @@ std::pair<u32, u32> FromBitString(const char* str) {
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return { bits, mask };
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return { bits, mask };
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}
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}
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u32 RandInt(u32 min, u32 max) {
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static std::random_device rd;
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static std::mt19937 mt(rd());
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std::uniform_int_distribution<u32> rand(min, max);
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return rand(mt);
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}
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void FuzzJit(const int instruction_count, const int run_count, const std::function<u32()> instruction_generator) {
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// Init core
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Core::Init();
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SCOPE_EXIT({ Core::Shutdown(); });
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// Prepare memory
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constexpr size_t MEMORY_SIZE = 4096 * 2;
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std::array<u8, MEMORY_SIZE> test_mem;
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std::memset(test_mem.data(), 0, MEMORY_SIZE);
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Memory::MapMemoryRegion(0, MEMORY_SIZE, test_mem.data());
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SCOPE_EXIT({ Memory::UnmapRegion(0, MEMORY_SIZE); });
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// Prepare test subjects
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JitX64::ARM_Jit jit(PrivilegeMode::USER32MODE);
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ARM_DynCom interp(PrivilegeMode::USER32MODE);
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SCOPE_EXIT({
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jit.FastClearCache();
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interp.ClearCache();
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});
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for (int run_number = 0; run_number < run_count; run_number++) {
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jit.FastClearCache();
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interp.ClearCache();
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u32 initial_regs[15];
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for (int i = 0; i < 15; i++) {
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u32 val = RandInt(0, 0xFFFFFFFF);
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interp.SetReg(i, val);
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jit.SetReg(i, val);
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initial_regs[i] = val;
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}
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interp.SetCPSR(0x000001d0);
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jit.SetCPSR(0x000001d0);
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interp.SetPC(0);
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jit.SetPC(0);
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for (int i = 0; i < instruction_count; i++) {
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u32 inst = instruction_generator();
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Memory::Write32(i * 4, inst);
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}
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Memory::Write32(instruction_count * 4, 0b0011001000001111000000000000);
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interp.ExecuteInstructions(instruction_count);
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jit.ExecuteInstructions(instruction_count);
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bool pass = true;
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if (interp.GetCPSR() != jit.GetCPSR()) pass = false;
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for (int i = 0; i <= 15; i++) {
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if (interp.GetReg(i) != jit.GetReg(i)) pass = false;
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}
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if (!pass) {
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printf("Failed at execution number %i\n", run_number);
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printf("\nInstruction Listing: \n");
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for (int i = 0; i < instruction_count; i++) {
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printf("%s\n", ARM_Disasm::Disassemble(i * 4, Memory::Read32(i * 4)).c_str());
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}
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printf("\nFinal Register Listing: \n");
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for (int i = 0; i <= 15; i++) {
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printf("%4i: %08x %08x %s\n", i, interp.GetReg(i), jit.GetReg(i), interp.GetReg(i) != jit.GetReg(i) ? "*" : "");
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}
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printf("CPSR: %08x %08x %s\n", interp.GetCPSR(), jit.GetCPSR(), interp.GetCPSR() != jit.GetCPSR() ? "*" : "");
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printf("\nInterpreter walkthrough:\n");
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interp.ClearCache();
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interp.SetPC(0);
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interp.SetCPSR(0x000001d0);
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for (int i = 0; i < 15; i++) {
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interp.SetReg(i, initial_regs[i]);
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printf("%4i: %08x\n", i, interp.GetReg(i));
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}
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for (int inst = 0; inst < instruction_count; inst++) {
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printf("%s\n", ARM_Disasm::Disassemble(inst * 4, Memory::Read32(inst * 4)).c_str());
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interp.Step();
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for (int i = 0; i <= 15; i++) {
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printf("%4i: %08x\n", i, interp.GetReg(i));
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}
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printf("CPSR: %08x\n", interp.GetCPSR());
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}
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#ifdef _MSC_VER
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DebugBreak();
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#endif
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FAIL();
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}
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printf("%i\r", run_number);
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if (run_number % 50 == 0) {
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fflush(stdout);
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}
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}
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}
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TEST_CASE("Fuzz ARM data processing instructions", "[JitX64]") {
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TEST_CASE("Fuzz ARM data processing instructions", "[JitX64]") {
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const std::array<std::pair<u32, u32>, 48> instructions = {{
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const std::array<std::pair<u32, u32>, 48> instructions = {{
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FromBitString("cccc0010101Snnnnddddrrrrvvvvvvvv"),
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FromBitString("cccc0010101Snnnnddddrrrrvvvvvvvv"),
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@ -91,116 +198,25 @@ TEST_CASE("Fuzz ARM data processing instructions", "[JitX64]") {
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FromBitString("cccc00010001nnnn0000ssss0rr1mmmm"),
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FromBitString("cccc00010001nnnn0000ssss0rr1mmmm"),
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}};
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}};
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// Init core
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auto instruction_select_without_R15 = [&]() -> u32 {
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Core::Init();
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size_t inst_index = RandInt(0, instructions.size() - 1);
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SCOPE_EXIT({ Core::Shutdown(); });
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// Prepare random numbers
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u32 cond = 0xE;
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std::random_device rd;
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// Have a one-in-twenty-five chance of actually having a cond.
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std::mt19937 mt(rd());
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if (RandInt(1, 25) == 1) {
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auto rand_int = [&mt](u32 min, u32 max) -> u32 {
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cond = RandInt(0x0, 0xD);
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std::uniform_int_distribution<u32> rand(min, max);
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}
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return rand(mt);
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u32 Rn = RandInt(0, 15);
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u32 Rd = RandInt(0, 14);
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u32 S = RandInt(0, 1);
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u32 shifter_operand = RandInt(0, 0xFFF);
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u32 assemble_randoms = (shifter_operand << 0) | (Rd << 12) | (Rn << 16) | (S << 20) | (cond << 28);
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return instructions[inst_index].first | (assemble_randoms & (~instructions[inst_index].second));
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};
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};
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// Prepare memory
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FuzzJit(5, 10000, instruction_select_without_R15);
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u8* test_mem = new u8[4096 * 2];
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FuzzJit(1024, 500, instruction_select_without_R15);
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std::memset(test_mem, 0, 4096 * 2);
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Memory::MapMemoryRegion(0, 4096 * 2, test_mem);
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SCOPE_EXIT({ Memory::UnmapRegion(0, 4096 * 2); });
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// Prepare test subjects
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JitX64::ARM_Jit jit(PrivilegeMode::USER32MODE);
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ARM_DynCom interp(PrivilegeMode::USER32MODE);
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SCOPE_EXIT({
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jit.FastClearCache();
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interp.ClearCache();
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});
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for (int run_number = 0; run_number < 10000; run_number++) {
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jit.FastClearCache();
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interp.ClearCache();
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u32 initial_regs[15];
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for (int i = 0; i < 15; i++) {
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u32 val = rand_int(0, 0xFFFFFFFF);
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interp.SetReg(i, val);
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jit.SetReg(i, val);
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initial_regs[i] = val;
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}
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interp.SetCPSR(0x000001d0);
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jit.SetCPSR(0x000001d0);
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interp.SetPC(0);
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jit.SetPC(0);
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constexpr int NUM_INST = 5;
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for (int i = 0; i < NUM_INST; i++) {
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size_t inst_index = rand_int(0, instructions.size() - 1);
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u32 cond = rand_int(0x0, 0xE);
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u32 Rn = rand_int(0, 15);
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u32 Rd = rand_int(0, 14);
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u32 S = rand_int(0, 1);
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u32 shifter_operand = rand_int(0, 0xFFF);
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u32 assemble_randoms = (shifter_operand << 0) | (Rd << 12) | (Rn << 16) | (S << 20) | (cond << 28);
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u32 inst = instructions[inst_index].first | (assemble_randoms & (~instructions[inst_index].second));
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Memory::Write32(i * 4, inst);
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}
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Memory::Write32(NUM_INST * 4, 0b0011001000001111000000000000);
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interp.ExecuteInstructions(NUM_INST);
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jit.ExecuteInstructions(NUM_INST);
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bool pass = true;
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if (interp.GetCPSR() != jit.GetCPSR()) pass = false;
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for (int i = 0; i <= 15; i++) {
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if (interp.GetReg(i) != jit.GetReg(i)) pass = false;
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}
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if (!pass) {
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printf("Failed at execution number %i\n", run_number);
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printf("\nInstruction Listing: \n");
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for (int i = 0; i < NUM_INST; i++) {
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printf("%s\n", ARM_Disasm::Disassemble(i * 4, Memory::Read32(i * 4)).c_str());
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}
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printf("\nFinal Register Listing: \n");
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for (int i = 0; i <= 15; i++) {
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printf("%4i: %08x %08x %s\n", i, interp.GetReg(i), jit.GetReg(i), interp.GetReg(i) != jit.GetReg(i) ? "*" : "");
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}
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printf("CPSR: %08x %08x %s\n", interp.GetCPSR(), jit.GetCPSR(), interp.GetCPSR() != jit.GetCPSR() ? "*" : "");
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printf("\nInterpreter walkthrough:\n");
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interp.ClearCache();
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interp.SetPC(0);
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interp.SetCPSR(0x000001d0);
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for (int i = 0; i < 15; i++) {
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interp.SetReg(i, initial_regs[i]);
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printf("%4i: %08x\n", i, interp.GetReg(i));
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}
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for (int inst = 0; inst < NUM_INST; inst++) {
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printf("%s\n", ARM_Disasm::Disassemble(inst * 4, Memory::Read32(inst * 4)).c_str());
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interp.Step();
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for (int i = 0; i <= 15; i++) {
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printf("%4i: %08x\n", i, interp.GetReg(i));
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}
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printf("CPSR: %08x\n", interp.GetCPSR());
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}
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FAIL();
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}
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if (run_number % 100 == 0) {
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printf("%i\r", run_number);
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fflush(stdout);
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}
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}
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}
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}
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