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@ -195,10 +195,10 @@ endif()
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option(ENABLE_BINARY_TRANSLATION "Enable binary translation. Requires LLVM" OFF)
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if(ENABLE_BINARY_TRANSLATION)
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add_definitions(-DENABLE_BINARY_TRANSLATION)
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find_package(LLVM REQUIRED CONFIG)
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include_directories(${LLVM_INCLUDE_DIRS})
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add_definitions(${LLVM_DEFINITIONS})
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llvm_map_components_to_libnames(llvm_libs Core Support X86 ExecutionEngine MCJIT BitWriter ipo)
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add_definitions(-DENABLE_BINARY_TRANSLATION)
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find_package(LLVM REQUIRED CONFIG)
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include_directories(${LLVM_INCLUDE_DIRS})
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add_definitions(${LLVM_DEFINITIONS})
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llvm_map_components_to_libnames(llvm_libs Core Support X86 ExecutionEngine MCJIT BitWriter ipo)
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endif()
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add_subdirectory(src)
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@ -18,18 +18,6 @@ ARMFuncs::ShiftTN ARMFuncs::DecodeImmShift(InstructionBlock* instruction, u32 ty
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}
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}
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ARMFuncs::SRType ARMFuncs::DecodeRegShift(u32 type)
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{
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switch (type)
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{
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case 0: return SRType::LSL;
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case 1: return SRType::LSR;
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case 2: return SRType::ASR;
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case 3: return SRType::ROR;
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default: assert(false, "Invalid shift type");
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}
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}
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llvm::Value* ARMFuncs::Shift(InstructionBlock* instruction, llvm::Value* value, SRType type, llvm::Value* amount, llvm::Value* carry_in)
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{
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return Shift_C(instruction, value, type, amount, carry_in).result;
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@ -33,7 +33,6 @@ public:
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};
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static ShiftTN DecodeImmShift(InstructionBlock *instruction, u32 type, u32 imm5);
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static SRType DecodeRegShift(u32 type);
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static llvm::Value *Shift(InstructionBlock *instruction, llvm::Value *value, SRType type, llvm::Value *amount, llvm::Value *carry_in);
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static ResultCarry Shift_C(InstructionBlock *instruction, llvm::Value *value, SRType type, llvm::Value *amount, llvm::Value *carry_in);
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@ -11,8 +11,8 @@ struct BinarySearch
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size_t max;
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BinarySearch(size_t max) : min(0), mid(max / 2), max(max) { }
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BinarySearch(size_t min, size_t max) : min(min), mid((min + max) / 2), max(max) { }
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BinarySearch l() { return BinarySearch(min, mid); }
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BinarySearch r() { return BinarySearch(mid, max); }
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BinarySearch l() const { return BinarySearch(min, mid); }
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BinarySearch r() const { return BinarySearch(mid, max); }
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operator size_t()
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{
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LOG_DEBUG(BinaryTranslator, "BinarySearch: %x: %x - %x (%x, %d)", mid, max, min, max - min, (size_t)std::log2(max - min));
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@ -27,8 +27,8 @@ public:
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void GenerateFunctions();
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llvm::FunctionType *GetFunctionType() { return function_type; }
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size_t GetColorCount() { return colors.size(); }
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size_t GetColorInstructionCount(size_t color) { return colors[color].instructions.size(); }
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size_t GetColorCount() const { return colors.size(); }
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size_t GetColorInstructionCount(size_t color) const { return colors[color].instructions.size(); }
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InstructionBlock *GetColorInstruction(size_t color, size_t index) { return colors[color].instructions[index]; }
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llvm::Function *GetColorFunction(size_t color) { return colors[color].function; }
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private:
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@ -37,14 +37,14 @@ void CodeGen::Run()
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return;
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}
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IntializeLLVM();
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InitializeLLVM();
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GenerateModule();
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GenerateDebugFiles();
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if (!Verify()) return;
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OptimizeAndGenerate();
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}
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void CodeGen::IntializeLLVM()
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void CodeGen::InitializeLLVM()
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{
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InitializeNativeTarget();
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InitializeNativeTargetAsmPrinter();
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@ -19,7 +19,7 @@ public:
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~CodeGen();
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void Run();
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void IntializeLLVM();
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void InitializeLLVM();
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void GenerateModule();
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void GenerateDebugFiles();
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bool Verify();
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@ -54,7 +54,7 @@ void InstructionBlock::Link(InstructionBlock* prev, InstructionBlock* next)
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next->prevs.push_back(prev);
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}
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u32 InstructionBlock::Address()
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u32 InstructionBlock::Address() const
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{
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return instruction->Address();
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}
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@ -54,18 +54,18 @@ public:
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*/
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static void Link(InstructionBlock *prev, InstructionBlock *next);
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u32 Address();
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u32 Address() const;
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ModuleGen *Module() { return module; }
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llvm::IRBuilder<> *IrBuilder() { return module->IrBuilder(); }
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llvm::BasicBlock *GetEntryBasicBlock() { return entry_basic_block; }
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bool HasColor() { return has_color; }
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bool HasColor() const { return has_color; }
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void SetColor(size_t color) { this->color = color; has_color = true; }
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size_t GetColor() { return color; }
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size_t GetColor() const { return color; }
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std::list<InstructionBlock *> GetNexts() { return nexts; }
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std::list<InstructionBlock *> GetPrevs() { return prevs; }
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std::list<InstructionBlock *> GetNexts() const { return nexts; }
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std::list<InstructionBlock *> GetPrevs() const { return prevs; }
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private:
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// Textual representation of the address
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// Used to generate names
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@ -27,32 +27,28 @@ bool IsSupported(Arithmetic::Op op)
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bool IsBitwise(Arithmetic::Op op)
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{
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switch (op)
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{
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case Arithmetic::Op::BitwiseAnd: return true;
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case Arithmetic::Op::BitwiseXor: return true;
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case Arithmetic::Op::BitwiseOr: return true;
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case Arithmetic::Op::BitwiseBitClear: return true;
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default: break;
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}
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return op == Arithmetic::Op::BitwiseAnd ||
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op == Arithmetic::Op::BitwiseXor ||
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op == Arithmetic::Op::BitwiseOr ||
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op == Arithmetic::Op::BitwiseBitClear;
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}
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bool Arithmetic::Decode()
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{
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if (ReadFields({ CondDef(), FieldDef<3>(0), FieldDef<4>(&op), FieldDef<1>(&s), FieldDef<4>(&rn),
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if (ReadFields({ CondDef(), FieldDef<3>(0), FieldDef<4>(&op), FieldDef<1>(&set_flags), FieldDef<4>(&rn),
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FieldDef<4>(&rd), FieldDef<5>(&imm5), FieldDef<2>(&type), FieldDef<1>(0), FieldDef<4>(&rm)}))
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{
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form = Form::Register;
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if (rd == Register::PC && s) return false; // SEE SUBS PC, LR and related instructions;
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if (rd == Register::PC && set_flags) return false; // SEE SUBS PC, LR and related instructions;
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if (rn == Register::PC) return false;
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if (rm == Register::PC) return false;
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return IsSupported(op);
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}
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if (ReadFields({ CondDef(), FieldDef<3>(1), FieldDef<4>(&op), FieldDef<1>(&s), FieldDef<4>(&rn),
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if (ReadFields({ CondDef(), FieldDef<3>(1), FieldDef<4>(&op), FieldDef<1>(&set_flags), FieldDef<4>(&rn),
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FieldDef<4>(&rd), FieldDef<12>(&imm12) }))
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{
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form = Form::Immediate;
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if (rd == Register::PC && s) return false; // SEE SUBS PC, LR and related instructions;
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if (rd == Register::PC && set_flags) return false; // SEE SUBS PC, LR and related instructions;
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if (rn == Register::PC) return false;
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return IsSupported(op);
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}
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@ -117,7 +113,7 @@ void Arithmetic::GenerateInstructionCode(InstructionBlock* instruction_block)
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instruction_block->Write(rd, result.result);
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if (s)
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if (set_flags)
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{
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instruction_block->Write(Register::N, ir_builder->CreateICmpSLT(result.result, ir_builder->getInt32(0)));
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instruction_block->Write(Register::Z, ir_builder->CreateICmpEQ(result.result, ir_builder->getInt32(0)));
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BitwiseOr = 12, MoveAndShifts, BitwiseBitClear, BitwiseNot
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};
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public:
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virtual bool Decode() override;
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bool Decode() override;
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void GenerateInstructionCode(InstructionBlock* instruction_block) override;
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private:
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Form form;
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Op op;
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bool s;
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bool set_flags;
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Register rn;
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Register rd;
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u32 imm5;
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Immediate, Register
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};
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public:
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virtual bool Decode() override;
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bool Decode() override;
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void GenerateInstructionCode(InstructionBlock* instruction_block) override;
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private:
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Form form;
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*/
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void GenerateCode(InstructionBlock *instruction_block);
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u32 Address() { return address; }
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u32 Address() const { return address; }
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protected:
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/*
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* Derived classes must override this, and implement it by calling ReadFields
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PC, Reg, MultiReg
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};
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public:
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virtual bool Decode() override;
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bool Decode() override;
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void GenerateInstructionCode(InstructionBlock* instruction_block) override;
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private:
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Register, ImmediateA1, ImmediateA2
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};
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public:
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virtual bool Decode() override;
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bool Decode() override;
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void GenerateInstructionCode(InstructionBlock* instruction_block) override;
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private:
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Form form;
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Immediate, Reg, MultiReg
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};
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public:
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virtual bool Decode() override;
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bool Decode() override;
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void GenerateInstructionCode(InstructionBlock* instruction_block) override;
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private:
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@ -1,3 +1,4 @@
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#pragma once
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enum class Condition;
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enum class Register;
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@ -28,10 +28,10 @@ const std::initializer_list<Kernel::AddressMapping> default_address_mappings = {
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{ 0x1FF70000, 0x8000, true }, // part of DSP RAM
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{ 0x1F000000, 0x600000, false }, // entire VRAM
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};
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u32 ROMCodeStart = 0;
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u32 ROMCodeSize = 0;
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u32 ROMReadOnlyDataStart = 0;
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u32 ROMReadOnlyDataSize = 0;
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u32 ROMCodeStart;
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u32 ROMCodeSize;
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u32 ROMReadOnlyDataStart;
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u32 ROMReadOnlyDataSize;
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/**
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* Identifies the type of a bootable file
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@ -97,6 +97,11 @@ static const char* GetFileTypeString(FileType type) {
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}
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ResultStatus LoadFile(const std::string& filename) {
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ROMCodeStart = 0;
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ROMCodeSize = 0;
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ROMReadOnlyDataStart = 0;
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ROMReadOnlyDataSize = 0;
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std::unique_ptr<FileUtil::IOFile> file(new FileUtil::IOFile(filename, "rb"));
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if (!file->IsOpen()) {
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LOG_ERROR(Loader, "Failed to load file %s", filename.c_str());
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