Formatting

This commit is contained in:
Dani Messerman 2015-05-08 17:59:46 +03:00
parent a5aae07260
commit af8817314a
18 changed files with 44 additions and 60 deletions

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@ -195,10 +195,10 @@ endif()
option(ENABLE_BINARY_TRANSLATION "Enable binary translation. Requires LLVM" OFF) option(ENABLE_BINARY_TRANSLATION "Enable binary translation. Requires LLVM" OFF)
if(ENABLE_BINARY_TRANSLATION) if(ENABLE_BINARY_TRANSLATION)
add_definitions(-DENABLE_BINARY_TRANSLATION) add_definitions(-DENABLE_BINARY_TRANSLATION)
find_package(LLVM REQUIRED CONFIG) find_package(LLVM REQUIRED CONFIG)
include_directories(${LLVM_INCLUDE_DIRS}) include_directories(${LLVM_INCLUDE_DIRS})
add_definitions(${LLVM_DEFINITIONS}) add_definitions(${LLVM_DEFINITIONS})
llvm_map_components_to_libnames(llvm_libs Core Support X86 ExecutionEngine MCJIT BitWriter ipo) llvm_map_components_to_libnames(llvm_libs Core Support X86 ExecutionEngine MCJIT BitWriter ipo)
endif() endif()
add_subdirectory(src) add_subdirectory(src)

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@ -18,18 +18,6 @@ ARMFuncs::ShiftTN ARMFuncs::DecodeImmShift(InstructionBlock* instruction, u32 ty
} }
} }
ARMFuncs::SRType ARMFuncs::DecodeRegShift(u32 type)
{
switch (type)
{
case 0: return SRType::LSL;
case 1: return SRType::LSR;
case 2: return SRType::ASR;
case 3: return SRType::ROR;
default: assert(false, "Invalid shift type");
}
}
llvm::Value* ARMFuncs::Shift(InstructionBlock* instruction, llvm::Value* value, SRType type, llvm::Value* amount, llvm::Value* carry_in) llvm::Value* ARMFuncs::Shift(InstructionBlock* instruction, llvm::Value* value, SRType type, llvm::Value* amount, llvm::Value* carry_in)
{ {
return Shift_C(instruction, value, type, amount, carry_in).result; return Shift_C(instruction, value, type, amount, carry_in).result;

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@ -33,7 +33,6 @@ public:
}; };
static ShiftTN DecodeImmShift(InstructionBlock *instruction, u32 type, u32 imm5); static ShiftTN DecodeImmShift(InstructionBlock *instruction, u32 type, u32 imm5);
static SRType DecodeRegShift(u32 type);
static llvm::Value *Shift(InstructionBlock *instruction, llvm::Value *value, SRType type, llvm::Value *amount, llvm::Value *carry_in); static llvm::Value *Shift(InstructionBlock *instruction, llvm::Value *value, SRType type, llvm::Value *amount, llvm::Value *carry_in);
static ResultCarry Shift_C(InstructionBlock *instruction, llvm::Value *value, SRType type, llvm::Value *amount, llvm::Value *carry_in); static ResultCarry Shift_C(InstructionBlock *instruction, llvm::Value *value, SRType type, llvm::Value *amount, llvm::Value *carry_in);

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@ -11,8 +11,8 @@ struct BinarySearch
size_t max; size_t max;
BinarySearch(size_t max) : min(0), mid(max / 2), max(max) { } BinarySearch(size_t max) : min(0), mid(max / 2), max(max) { }
BinarySearch(size_t min, size_t max) : min(min), mid((min + max) / 2), max(max) { } BinarySearch(size_t min, size_t max) : min(min), mid((min + max) / 2), max(max) { }
BinarySearch l() { return BinarySearch(min, mid); } BinarySearch l() const { return BinarySearch(min, mid); }
BinarySearch r() { return BinarySearch(mid, max); } BinarySearch r() const { return BinarySearch(mid, max); }
operator size_t() operator size_t()
{ {
LOG_DEBUG(BinaryTranslator, "BinarySearch: %x: %x - %x (%x, %d)", mid, max, min, max - min, (size_t)std::log2(max - min)); LOG_DEBUG(BinaryTranslator, "BinarySearch: %x: %x - %x (%x, %d)", mid, max, min, max - min, (size_t)std::log2(max - min));

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@ -27,8 +27,8 @@ public:
void GenerateFunctions(); void GenerateFunctions();
llvm::FunctionType *GetFunctionType() { return function_type; } llvm::FunctionType *GetFunctionType() { return function_type; }
size_t GetColorCount() { return colors.size(); } size_t GetColorCount() const { return colors.size(); }
size_t GetColorInstructionCount(size_t color) { return colors[color].instructions.size(); } size_t GetColorInstructionCount(size_t color) const { return colors[color].instructions.size(); }
InstructionBlock *GetColorInstruction(size_t color, size_t index) { return colors[color].instructions[index]; } InstructionBlock *GetColorInstruction(size_t color, size_t index) { return colors[color].instructions[index]; }
llvm::Function *GetColorFunction(size_t color) { return colors[color].function; } llvm::Function *GetColorFunction(size_t color) { return colors[color].function; }
private: private:

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@ -37,14 +37,14 @@ void CodeGen::Run()
return; return;
} }
IntializeLLVM(); InitializeLLVM();
GenerateModule(); GenerateModule();
GenerateDebugFiles(); GenerateDebugFiles();
if (!Verify()) return; if (!Verify()) return;
OptimizeAndGenerate(); OptimizeAndGenerate();
} }
void CodeGen::IntializeLLVM() void CodeGen::InitializeLLVM()
{ {
InitializeNativeTarget(); InitializeNativeTarget();
InitializeNativeTargetAsmPrinter(); InitializeNativeTargetAsmPrinter();

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@ -19,7 +19,7 @@ public:
~CodeGen(); ~CodeGen();
void Run(); void Run();
void IntializeLLVM(); void InitializeLLVM();
void GenerateModule(); void GenerateModule();
void GenerateDebugFiles(); void GenerateDebugFiles();
bool Verify(); bool Verify();

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@ -54,7 +54,7 @@ void InstructionBlock::Link(InstructionBlock* prev, InstructionBlock* next)
next->prevs.push_back(prev); next->prevs.push_back(prev);
} }
u32 InstructionBlock::Address() u32 InstructionBlock::Address() const
{ {
return instruction->Address(); return instruction->Address();
} }

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@ -54,18 +54,18 @@ public:
*/ */
static void Link(InstructionBlock *prev, InstructionBlock *next); static void Link(InstructionBlock *prev, InstructionBlock *next);
u32 Address(); u32 Address() const;
ModuleGen *Module() { return module; } ModuleGen *Module() { return module; }
llvm::IRBuilder<> *IrBuilder() { return module->IrBuilder(); } llvm::IRBuilder<> *IrBuilder() { return module->IrBuilder(); }
llvm::BasicBlock *GetEntryBasicBlock() { return entry_basic_block; } llvm::BasicBlock *GetEntryBasicBlock() { return entry_basic_block; }
bool HasColor() { return has_color; } bool HasColor() const { return has_color; }
void SetColor(size_t color) { this->color = color; has_color = true; } void SetColor(size_t color) { this->color = color; has_color = true; }
size_t GetColor() { return color; } size_t GetColor() const { return color; }
std::list<InstructionBlock *> GetNexts() { return nexts; } std::list<InstructionBlock *> GetNexts() const { return nexts; }
std::list<InstructionBlock *> GetPrevs() { return prevs; } std::list<InstructionBlock *> GetPrevs() const { return prevs; }
private: private:
// Textual representation of the address // Textual representation of the address
// Used to generate names // Used to generate names

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@ -27,32 +27,28 @@ bool IsSupported(Arithmetic::Op op)
bool IsBitwise(Arithmetic::Op op) bool IsBitwise(Arithmetic::Op op)
{ {
switch (op) return op == Arithmetic::Op::BitwiseAnd ||
{ op == Arithmetic::Op::BitwiseXor ||
case Arithmetic::Op::BitwiseAnd: return true; op == Arithmetic::Op::BitwiseOr ||
case Arithmetic::Op::BitwiseXor: return true; op == Arithmetic::Op::BitwiseBitClear;
case Arithmetic::Op::BitwiseOr: return true;
case Arithmetic::Op::BitwiseBitClear: return true;
default: break;
}
} }
bool Arithmetic::Decode() bool Arithmetic::Decode()
{ {
if (ReadFields({ CondDef(), FieldDef<3>(0), FieldDef<4>(&op), FieldDef<1>(&s), FieldDef<4>(&rn), if (ReadFields({ CondDef(), FieldDef<3>(0), FieldDef<4>(&op), FieldDef<1>(&set_flags), FieldDef<4>(&rn),
FieldDef<4>(&rd), FieldDef<5>(&imm5), FieldDef<2>(&type), FieldDef<1>(0), FieldDef<4>(&rm)})) FieldDef<4>(&rd), FieldDef<5>(&imm5), FieldDef<2>(&type), FieldDef<1>(0), FieldDef<4>(&rm)}))
{ {
form = Form::Register; form = Form::Register;
if (rd == Register::PC && s) return false; // SEE SUBS PC, LR and related instructions; if (rd == Register::PC && set_flags) return false; // SEE SUBS PC, LR and related instructions;
if (rn == Register::PC) return false; if (rn == Register::PC) return false;
if (rm == Register::PC) return false; if (rm == Register::PC) return false;
return IsSupported(op); return IsSupported(op);
} }
if (ReadFields({ CondDef(), FieldDef<3>(1), FieldDef<4>(&op), FieldDef<1>(&s), FieldDef<4>(&rn), if (ReadFields({ CondDef(), FieldDef<3>(1), FieldDef<4>(&op), FieldDef<1>(&set_flags), FieldDef<4>(&rn),
FieldDef<4>(&rd), FieldDef<12>(&imm12) })) FieldDef<4>(&rd), FieldDef<12>(&imm12) }))
{ {
form = Form::Immediate; form = Form::Immediate;
if (rd == Register::PC && s) return false; // SEE SUBS PC, LR and related instructions; if (rd == Register::PC && set_flags) return false; // SEE SUBS PC, LR and related instructions;
if (rn == Register::PC) return false; if (rn == Register::PC) return false;
return IsSupported(op); return IsSupported(op);
} }
@ -117,7 +113,7 @@ void Arithmetic::GenerateInstructionCode(InstructionBlock* instruction_block)
instruction_block->Write(rd, result.result); instruction_block->Write(rd, result.result);
if (s) if (set_flags)
{ {
instruction_block->Write(Register::N, ir_builder->CreateICmpSLT(result.result, ir_builder->getInt32(0))); instruction_block->Write(Register::N, ir_builder->CreateICmpSLT(result.result, ir_builder->getInt32(0)));
instruction_block->Write(Register::Z, ir_builder->CreateICmpEQ(result.result, ir_builder->getInt32(0))); instruction_block->Write(Register::Z, ir_builder->CreateICmpEQ(result.result, ir_builder->getInt32(0)));

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@ -20,13 +20,12 @@ public:
BitwiseOr = 12, MoveAndShifts, BitwiseBitClear, BitwiseNot BitwiseOr = 12, MoveAndShifts, BitwiseBitClear, BitwiseNot
}; };
public: bool Decode() override;
virtual bool Decode() override;
void GenerateInstructionCode(InstructionBlock* instruction_block) override; void GenerateInstructionCode(InstructionBlock* instruction_block) override;
private: private:
Form form; Form form;
Op op; Op op;
bool s; bool set_flags;
Register rn; Register rn;
Register rd; Register rd;
u32 imm5; u32 imm5;

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@ -9,8 +9,7 @@ public:
Immediate, Register Immediate, Register
}; };
public: bool Decode() override;
virtual bool Decode() override;
void GenerateInstructionCode(InstructionBlock* instruction_block) override; void GenerateInstructionCode(InstructionBlock* instruction_block) override;
private: private:
Form form; Form form;

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@ -24,7 +24,7 @@ public:
*/ */
void GenerateCode(InstructionBlock *instruction_block); void GenerateCode(InstructionBlock *instruction_block);
u32 Address() { return address; } u32 Address() const { return address; }
protected: protected:
/* /*
* Derived classes must override this, and implement it by calling ReadFields * Derived classes must override this, and implement it by calling ReadFields

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@ -10,8 +10,7 @@ public:
PC, Reg, MultiReg PC, Reg, MultiReg
}; };
public: bool Decode() override;
virtual bool Decode() override;
void GenerateInstructionCode(InstructionBlock* instruction_block) override; void GenerateInstructionCode(InstructionBlock* instruction_block) override;
private: private:

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@ -18,8 +18,7 @@ public:
Register, ImmediateA1, ImmediateA2 Register, ImmediateA1, ImmediateA2
}; };
public: bool Decode() override;
virtual bool Decode() override;
void GenerateInstructionCode(InstructionBlock* instruction_block) override; void GenerateInstructionCode(InstructionBlock* instruction_block) override;
private: private:
Form form; Form form;

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@ -10,8 +10,7 @@ public:
Immediate, Reg, MultiReg Immediate, Reg, MultiReg
}; };
public: bool Decode() override;
virtual bool Decode() override;
void GenerateInstructionCode(InstructionBlock* instruction_block) override; void GenerateInstructionCode(InstructionBlock* instruction_block) override;
private: private:

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@ -1,3 +1,4 @@
#pragma once
enum class Condition; enum class Condition;
enum class Register; enum class Register;

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@ -28,10 +28,10 @@ const std::initializer_list<Kernel::AddressMapping> default_address_mappings = {
{ 0x1FF70000, 0x8000, true }, // part of DSP RAM { 0x1FF70000, 0x8000, true }, // part of DSP RAM
{ 0x1F000000, 0x600000, false }, // entire VRAM { 0x1F000000, 0x600000, false }, // entire VRAM
}; };
u32 ROMCodeStart = 0; u32 ROMCodeStart;
u32 ROMCodeSize = 0; u32 ROMCodeSize;
u32 ROMReadOnlyDataStart = 0; u32 ROMReadOnlyDataStart;
u32 ROMReadOnlyDataSize = 0; u32 ROMReadOnlyDataSize;
/** /**
* Identifies the type of a bootable file * Identifies the type of a bootable file
@ -97,6 +97,11 @@ static const char* GetFileTypeString(FileType type) {
} }
ResultStatus LoadFile(const std::string& filename) { ResultStatus LoadFile(const std::string& filename) {
ROMCodeStart = 0;
ROMCodeSize = 0;
ROMReadOnlyDataStart = 0;
ROMReadOnlyDataSize = 0;
std::unique_ptr<FileUtil::IOFile> file(new FileUtil::IOFile(filename, "rb")); std::unique_ptr<FileUtil::IOFile> file(new FileUtil::IOFile(filename, "rb"));
if (!file->IsOpen()) { if (!file->IsOpen()) {
LOG_ERROR(Loader, "Failed to load file %s", filename.c_str()); LOG_ERROR(Loader, "Failed to load file %s", filename.c_str());