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ARM:Disassembler Better differentiate TEQ from MSR
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@ -1500,6 +1500,9 @@ Opcode ARM_Disasm::DecodeALU(u32 insn) {
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u8 is_immed = (insn >> 25) & 0x1;
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u8 is_immed = (insn >> 25) & 0x1;
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u8 opcode = (insn >> 21) & 0xf;
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u8 opcode = (insn >> 21) & 0xf;
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u8 bit_s = (insn >> 20) & 1;
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u8 bit_s = (insn >> 20) & 1;
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u8 msr_15_12 = (insn >> 12) & 0xF;
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u8 msr_11_8 = (insn >> 8) & 0xF;
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u8 msr_7_4 = (insn >> 4) & 0xF;
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u8 shift_is_reg = (insn >> 4) & 1;
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u8 shift_is_reg = (insn >> 4) & 1;
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u8 bit7 = (insn >> 7) & 1;
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u8 bit7 = (insn >> 7) & 1;
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if (!is_immed && shift_is_reg && (bit7 != 0)) {
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if (!is_immed && shift_is_reg && (bit7 != 0)) {
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@ -1529,9 +1532,9 @@ Opcode ARM_Disasm::DecodeALU(u32 insn) {
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return OP_TST;
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return OP_TST;
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return OP_MRS;
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return OP_MRS;
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case 0x9:
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case 0x9:
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if (bit_s)
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if (msr_15_12 == 0xf && msr_11_8 == 0 && msr_7_4 == 0)
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return OP_TEQ;
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return OP_MSR;
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return OP_MSR;
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return OP_TEQ;
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case 0xa:
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case 0xa:
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if (bit_s)
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if (bit_s)
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return OP_CMP;
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return OP_CMP;
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