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GPU: Do periodic VBlank updates using CoreTiming

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This commit is contained in:
Yuri Kunde Schlesner 2015-01-14 01:19:08 -02:00
parent e29dd76e12
commit 9e084826b8
3 changed files with 43 additions and 50 deletions
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39
src/core/hw/gpu.cpp
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@ -9,6 +9,7 @@
#include "core/settings.h" #include "core/settings.h"
#include "core/core.h" #include "core/core.h"
#include "core/mem_map.h" #include "core/mem_map.h"
#include "core/core_timing.h"
#include "core/hle/hle.h" #include "core/hle/hle.h"
#include "core/hle/service/gsp_gpu.h" #include "core/hle/service/gsp_gpu.h"
@ -24,12 +25,17 @@ namespace GPU {
Regs g_regs; Regs g_regs;
bool g_skip_frame = false; ///< True if the current frame was skipped /// True if the current frame was skipped
bool g_skip_frame = false;
static u64 frame_ticks = 0; ///< 268MHz / gpu_refresh_rate frames per second /// 268MHz / gpu_refresh_rate frames per second
static u64 last_update_tick = 0; ///< CPU ticl count from last GPU update static u64 frame_ticks;
static u64 frame_count = 0; ///< Number of frames drawn /// Event id for CoreTiming
static bool last_skip_frame = false; ///< True if the last frame was skipped static int vblank_event;
/// Total number of frames drawn
static u64 frame_count;
/// True if the last frame was skipped
static bool last_skip_frame = false;
template <typename T> template <typename T>
inline void Read(T &var, const u32 raw_addr) { inline void Read(T &var, const u32 raw_addr) {
@ -192,21 +198,9 @@ template void Write<u16>(u32 addr, const u16 data);
template void Write<u8>(u32 addr, const u8 data); template void Write<u8>(u32 addr, const u8 data);
/// Update hardware /// Update hardware
void Update() { static void VBlankCallback(u64 userdata, int cycles_late) {
auto& framebuffer_top = g_regs.framebuffer_config[0]; auto& framebuffer_top = g_regs.framebuffer_config[0];
// Synchronize GPU on a thread reschedule: Because we cannot accurately predict a vertical
// blank, we need to simulate it. Based on testing, it seems that retail applications work more
// accurately when this is signalled between thread switches.
u64 current_ticks = Core::g_app_core->GetTicks();
if (HLE::g_reschedule) {
// Synchronize frame...
if ((current_ticks - last_update_tick) >= frame_ticks) {
last_update_tick += frame_ticks;
frame_count++; frame_count++;
last_skip_frame = g_skip_frame; last_skip_frame = g_skip_frame;
g_skip_frame = (frame_count & Settings::values.frame_skip) != 0; g_skip_frame = (frame_count & Settings::values.frame_skip) != 0;
@ -234,8 +228,9 @@ void Update() {
// until we can emulate DSP interrupts, this is probably the only reasonable place to do // until we can emulate DSP interrupts, this is probably the only reasonable place to do
// this. Certain games expect this to be periodically signaled. // this. Certain games expect this to be periodically signaled.
DSP_DSP::SignalInterrupt(); DSP_DSP::SignalInterrupt();
}
} // Reschedule recurrent event
CoreTiming::ScheduleEvent(frame_ticks - cycles_late, vblank_event);
} }
/// Initialize hardware /// Initialize hardware
@ -269,10 +264,12 @@ void Init() {
framebuffer_sub.active_fb = 0; framebuffer_sub.active_fb = 0;
frame_ticks = 268123480 / Settings::values.gpu_refresh_rate; frame_ticks = 268123480 / Settings::values.gpu_refresh_rate;
last_update_tick = Core::g_app_core->GetTicks();
last_skip_frame = false; last_skip_frame = false;
g_skip_frame = false; g_skip_frame = false;
vblank_event = CoreTiming::RegisterEvent("GPU::VBlankCallback", VBlankCallback);
CoreTiming::ScheduleEvent(frame_ticks, vblank_event);
LOG_DEBUG(HW_GPU, "initialized OK"); LOG_DEBUG(HW_GPU, "initialized OK");
} }

3
src/core/hw/gpu.h
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@ -252,9 +252,6 @@ void Read(T &var, const u32 addr);
template <typename T> template <typename T>
void Write(u32 addr, const T data); void Write(u32 addr, const T data);
/// Update hardware
void Update();
/// Initialize hardware /// Initialize hardware
void Init(); void Init();

1
src/core/hw/hw.cpp
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@ -75,7 +75,6 @@ template void Write<u8>(u32 addr, const u8 data);
/// Update hardware /// Update hardware
void Update() { void Update() {
GPU::Update();
} }
/// Initialize hardware /// Initialize hardware