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https://github.com/citra-emu/citra.git
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Revert "Extracted the attribute setup and draw commands into their own functions"
This reverts commit b3b34a1e76. This
commit causes a performance regression for not enough benefits
This commit is contained in:
James Rowe
parent
947067de81
commit
9d9693c13d
@ -119,16 +119,64 @@ static void WriteUniformFloatReg(ShaderRegs& config, Shader::ShaderSetup& setup,
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}
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}
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static void LoadDefaultVertexAttributes(u32 register_value) {
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static void WritePicaReg(u32 id, u32 value, u32 mask) {
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auto& regs = g_state.regs;
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if (id >= Regs::NUM_REGS) {
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LOG_ERROR(HW_GPU,
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"Commandlist tried to write to invalid register 0x%03X (value: %08X, mask: %X)",
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id, value, mask);
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return;
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}
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// TODO: Figure out how register masking acts on e.g. vs.uniform_setup.set_value
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u32 old_value = regs.reg_array[id];
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const u32 write_mask = expand_bits_to_bytes[mask];
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regs.reg_array[id] = (old_value & ~write_mask) | (value & write_mask);
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// Double check for is_pica_tracing to avoid call overhead
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if (DebugUtils::IsPicaTracing()) {
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DebugUtils::OnPicaRegWrite({(u16)id, (u16)mask, regs.reg_array[id]});
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}
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if (g_debug_context)
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g_debug_context->OnEvent(DebugContext::Event::PicaCommandLoaded,
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reinterpret_cast<void*>(&id));
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switch (id) {
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// Trigger IRQ
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case PICA_REG_INDEX(trigger_irq):
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Service::GSP::SignalInterrupt(Service::GSP::InterruptId::P3D);
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break;
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case PICA_REG_INDEX(pipeline.triangle_topology):
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g_state.primitive_assembler.Reconfigure(regs.pipeline.triangle_topology);
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break;
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case PICA_REG_INDEX(pipeline.restart_primitive):
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g_state.primitive_assembler.Reset();
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break;
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case PICA_REG_INDEX(pipeline.vs_default_attributes_setup.index):
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g_state.immediate.current_attribute = 0;
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g_state.immediate.reset_geometry_pipeline = true;
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default_attr_counter = 0;
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break;
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// Load default vertex input attributes
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case PICA_REG_INDEX_WORKAROUND(pipeline.vs_default_attributes_setup.set_value[0], 0x233):
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case PICA_REG_INDEX_WORKAROUND(pipeline.vs_default_attributes_setup.set_value[1], 0x234):
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case PICA_REG_INDEX_WORKAROUND(pipeline.vs_default_attributes_setup.set_value[2], 0x235): {
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// TODO: Does actual hardware indeed keep an intermediate buffer or does
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// it directly write the values?
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default_attr_write_buffer[default_attr_counter++] = register_value;
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default_attr_write_buffer[default_attr_counter++] = value;
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// Default attributes are written in a packed format such that four float24 values are encoded
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// in three 32-bit numbers.
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// We write to internal memory once a full such vector is written.
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// Default attributes are written in a packed format such that four float24 values are
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// encoded in
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// three 32-bit numbers. We write to internal memory once a full such vector is
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// written.
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if (default_attr_counter >= 3) {
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default_attr_counter = 0;
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@ -136,7 +184,7 @@ static void LoadDefaultVertexAttributes(u32 register_value) {
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if (setup.index >= 16) {
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LOG_ERROR(HW_GPU, "Invalid VS default attribute index %d", (int)setup.index);
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return;
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break;
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}
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Math::Vec4<float24> attribute;
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@ -201,16 +249,34 @@ static void LoadDefaultVertexAttributes(u32 register_value) {
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// See: https://github.com/citra-emu/citra/pull/2866#issuecomment-327011550
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VideoCore::g_renderer->Rasterizer()->DrawTriangles();
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if (g_debug_context) {
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g_debug_context->OnEvent(DebugContext::Event::FinishedPrimitiveBatch, nullptr);
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g_debug_context->OnEvent(DebugContext::Event::FinishedPrimitiveBatch,
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nullptr);
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}
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}
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}
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}
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}
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break;
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}
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static void Draw(u32 command_id) {
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case PICA_REG_INDEX(pipeline.gpu_mode):
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// This register likely just enables vertex processing and doesn't need any special handling
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break;
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case PICA_REG_INDEX_WORKAROUND(pipeline.command_buffer.trigger[0], 0x23c):
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case PICA_REG_INDEX_WORKAROUND(pipeline.command_buffer.trigger[1], 0x23d): {
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unsigned index =
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static_cast<unsigned>(id - PICA_REG_INDEX(pipeline.command_buffer.trigger[0]));
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u32* head_ptr = (u32*)Memory::GetPhysicalPointer(
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regs.pipeline.command_buffer.GetPhysicalAddress(index));
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g_state.cmd_list.head_ptr = g_state.cmd_list.current_ptr = head_ptr;
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g_state.cmd_list.length = regs.pipeline.command_buffer.GetSize(index) / sizeof(u32);
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break;
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}
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// It seems like these trigger vertex rendering
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case PICA_REG_INDEX(pipeline.trigger_draw):
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case PICA_REG_INDEX(pipeline.trigger_draw_indexed): {
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MICROPROFILE_SCOPE(GPU_Drawing);
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auto& regs = g_state.regs;
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#if PICA_LOG_TEV
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DebugUtils::DumpTevStageConfig(regs.GetTevStages());
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@ -225,7 +291,7 @@ static void Draw(u32 command_id) {
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VertexLoader loader(regs.pipeline);
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// Load vertices
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bool is_indexed = (command_id == PICA_REG_INDEX(pipeline.trigger_draw_indexed));
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bool is_indexed = (id == PICA_REG_INDEX(pipeline.trigger_draw_indexed));
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const auto& index_info = regs.pipeline.index_array;
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const u8* index_address_8 = Memory::GetPhysicalPointer(base_address + index_info.offset);
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@ -272,8 +338,8 @@ static void Draw(u32 command_id) {
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for (unsigned int index = 0; index < regs.pipeline.num_vertices; ++index) {
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// Indexed rendering doesn't use the start offset
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unsigned int vertex = is_indexed
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? (index_u16 ? index_address_16[index] : index_address_8[index])
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unsigned int vertex =
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is_indexed ? (index_u16 ? index_address_16[index] : index_address_8[index])
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: (index + regs.pipeline.vertex_offset);
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// -1 is a common special value used for primitive restart. Since it's unknown if
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@ -290,7 +356,8 @@ static void Draw(u32 command_id) {
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if (g_debug_context && Pica::g_debug_context->recorder) {
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int size = index_u16 ? 2 : 1;
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memory_accesses.AddAccess(base_address + index_info.offset + size * index, size);
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memory_accesses.AddAccess(base_address + index_info.offset + size * index,
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size);
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}
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for (unsigned int i = 0; i < VERTEX_CACHE_SIZE; ++i) {
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@ -335,82 +402,10 @@ static void Draw(u32 command_id) {
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if (g_debug_context) {
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g_debug_context->OnEvent(DebugContext::Event::FinishedPrimitiveBatch, nullptr);
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}
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}
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static void WritePicaReg(u32 id, u32 value, u32 mask) {
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auto& regs = g_state.regs;
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if (id >= Regs::NUM_REGS) {
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LOG_ERROR(HW_GPU,
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"Commandlist tried to write to invalid register 0x%03X (value: %08X, mask: %X)",
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id, value, mask);
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return;
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}
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// TODO: Figure out how register masking acts on e.g. vs.uniform_setup.set_value
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u32 old_value = regs.reg_array[id];
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const u32 write_mask = expand_bits_to_bytes[mask];
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regs.reg_array[id] = (old_value & ~write_mask) | (value & write_mask);
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// Double check for is_pica_tracing to avoid call overhead
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if (DebugUtils::IsPicaTracing()) {
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DebugUtils::OnPicaRegWrite({(u16)id, (u16)mask, regs.reg_array[id]});
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}
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if (g_debug_context)
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g_debug_context->OnEvent(DebugContext::Event::PicaCommandLoaded,
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reinterpret_cast<void*>(&id));
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switch (id) {
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// Trigger IRQ
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case PICA_REG_INDEX(trigger_irq):
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Service::GSP::SignalInterrupt(Service::GSP::InterruptId::P3D);
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break;
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case PICA_REG_INDEX(pipeline.triangle_topology):
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g_state.primitive_assembler.Reconfigure(regs.pipeline.triangle_topology);
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break;
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case PICA_REG_INDEX(pipeline.restart_primitive):
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g_state.primitive_assembler.Reset();
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break;
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case PICA_REG_INDEX(pipeline.vs_default_attributes_setup.index):
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g_state.immediate.current_attribute = 0;
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g_state.immediate.reset_geometry_pipeline = true;
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default_attr_counter = 0;
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break;
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// Load default vertex input attributes
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case PICA_REG_INDEX_WORKAROUND(pipeline.vs_default_attributes_setup.set_value[0], 0x233):
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case PICA_REG_INDEX_WORKAROUND(pipeline.vs_default_attributes_setup.set_value[1], 0x234):
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case PICA_REG_INDEX_WORKAROUND(pipeline.vs_default_attributes_setup.set_value[2], 0x235):
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LoadDefaultVertexAttributes(value);
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break;
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case PICA_REG_INDEX(pipeline.gpu_mode):
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// This register likely just enables vertex processing and doesn't need any special handling
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break;
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case PICA_REG_INDEX_WORKAROUND(pipeline.command_buffer.trigger[0], 0x23c):
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case PICA_REG_INDEX_WORKAROUND(pipeline.command_buffer.trigger[1], 0x23d): {
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unsigned index =
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static_cast<unsigned>(id - PICA_REG_INDEX(pipeline.command_buffer.trigger[0]));
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u32* head_ptr = (u32*)Memory::GetPhysicalPointer(
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regs.pipeline.command_buffer.GetPhysicalAddress(index));
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g_state.cmd_list.head_ptr = g_state.cmd_list.current_ptr = head_ptr;
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g_state.cmd_list.length = regs.pipeline.command_buffer.GetSize(index) / sizeof(u32);
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break;
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}
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// It seems like these trigger vertex rendering
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case PICA_REG_INDEX(pipeline.trigger_draw):
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case PICA_REG_INDEX(pipeline.trigger_draw_indexed):
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Draw(id);
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break;
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case PICA_REG_INDEX(gs.bool_uniforms):
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WriteUniformBoolReg(g_state.gs, g_state.regs.gs.bool_uniforms.Value());
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break;
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