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Merge pull request #3223 from lioncash/dyncom

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dyncom: Convert the SPSR checking define to a function
This commit is contained in:
bunnei 2017-12-05 23:11:49 -05:00 committed by GitHub
commit 959b1e4254
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GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 18 additions and 15 deletions
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29
src/core/arm/dyncom/arm_dyncom_interpreter.cpp
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@ -1403,7 +1403,6 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
cpu->VFlag = (cpu->Cpsr >> 28) & 1; \ cpu->VFlag = (cpu->Cpsr >> 28) & 1; \
cpu->TFlag = (cpu->Cpsr >> 5) & 1; cpu->TFlag = (cpu->Cpsr >> 5) & 1;
#define CurrentModeHasSPSR (cpu->Mode != SYSTEM32MODE) && (cpu->Mode != USER32MODE)
#define PC (cpu->Reg[15]) #define PC (cpu->Reg[15])
// GCC and Clang have a C++ extension to support a lookup table of labels. Otherwise, fallback // GCC and Clang have a C++ extension to support a lookup table of labels. Otherwise, fallback
@ -1669,7 +1668,7 @@ ADC_INST : {
RD = AddWithCarry(rn_val, SHIFTER_OPERAND, cpu->CFlag, &carry, &overflow); RD = AddWithCarry(rn_val, SHIFTER_OPERAND, cpu->CFlag, &carry, &overflow);
if (inst_cream->S && (inst_cream->Rd == 15)) { if (inst_cream->S && (inst_cream->Rd == 15)) {
if (CurrentModeHasSPSR) { if (cpu->CurrentModeHasSPSR()) {
cpu->Cpsr = cpu->Spsr_copy; cpu->Cpsr = cpu->Spsr_copy;
cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F); cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F);
LOAD_NZCVT; LOAD_NZCVT;
@ -1701,7 +1700,7 @@ ADD_INST : {
RD = AddWithCarry(rn_val, SHIFTER_OPERAND, 0, &carry, &overflow); RD = AddWithCarry(rn_val, SHIFTER_OPERAND, 0, &carry, &overflow);
if (inst_cream->S && (inst_cream->Rd == 15)) { if (inst_cream->S && (inst_cream->Rd == 15)) {
if (CurrentModeHasSPSR) { if (cpu->CurrentModeHasSPSR()) {
cpu->Cpsr = cpu->Spsr_copy; cpu->Cpsr = cpu->Spsr_copy;
cpu->ChangePrivilegeMode(cpu->Cpsr & 0x1F); cpu->ChangePrivilegeMode(cpu->Cpsr & 0x1F);
LOAD_NZCVT; LOAD_NZCVT;
@ -1735,7 +1734,7 @@ AND_INST : {
RD = lop & rop; RD = lop & rop;
if (inst_cream->S && (inst_cream->Rd == 15)) { if (inst_cream->S && (inst_cream->Rd == 15)) {
if (CurrentModeHasSPSR) { if (cpu->CurrentModeHasSPSR()) {
cpu->Cpsr = cpu->Spsr_copy; cpu->Cpsr = cpu->Spsr_copy;
cpu->ChangePrivilegeMode(cpu->Cpsr & 0x1F); cpu->ChangePrivilegeMode(cpu->Cpsr & 0x1F);
LOAD_NZCVT; LOAD_NZCVT;
@ -1779,7 +1778,7 @@ BIC_INST : {
u32 rop = SHIFTER_OPERAND; u32 rop = SHIFTER_OPERAND;
RD = lop & (~rop); RD = lop & (~rop);
if ((inst_cream->S) && (inst_cream->Rd == 15)) { if ((inst_cream->S) && (inst_cream->Rd == 15)) {
if (CurrentModeHasSPSR) { if (cpu->CurrentModeHasSPSR()) {
cpu->Cpsr = cpu->Spsr_copy; cpu->Cpsr = cpu->Spsr_copy;
cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F); cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F);
LOAD_NZCVT; LOAD_NZCVT;
@ -1995,7 +1994,7 @@ EOR_INST : {
u32 rop = SHIFTER_OPERAND; u32 rop = SHIFTER_OPERAND;
RD = lop ^ rop; RD = lop ^ rop;
if (inst_cream->S && (inst_cream->Rd == 15)) { if (inst_cream->S && (inst_cream->Rd == 15)) {
if (CurrentModeHasSPSR) { if (cpu->CurrentModeHasSPSR()) {
cpu->Cpsr = cpu->Spsr_copy; cpu->Cpsr = cpu->Spsr_copy;
cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F); cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F);
LOAD_NZCVT; LOAD_NZCVT;
@ -2075,7 +2074,7 @@ LDM_INST : {
} }
} }
if (CurrentModeHasSPSR) { if (cpu->CurrentModeHasSPSR()) {
cpu->Cpsr = cpu->Spsr_copy; cpu->Cpsr = cpu->Spsr_copy;
cpu->ChangePrivilegeMode(cpu->Cpsr & 0x1F); cpu->ChangePrivilegeMode(cpu->Cpsr & 0x1F);
LOAD_NZCVT; LOAD_NZCVT;
@ -2404,7 +2403,7 @@ MOV_INST : {
RD = SHIFTER_OPERAND; RD = SHIFTER_OPERAND;
if (inst_cream->S && (inst_cream->Rd == 15)) { if (inst_cream->S && (inst_cream->Rd == 15)) {
if (CurrentModeHasSPSR) { if (cpu->CurrentModeHasSPSR()) {
cpu->Cpsr = cpu->Spsr_copy; cpu->Cpsr = cpu->Spsr_copy;
cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F); cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F);
LOAD_NZCVT; LOAD_NZCVT;
@ -2510,7 +2509,7 @@ MSR_INST : {
cpu->ChangePrivilegeMode(cpu->Cpsr & 0x1F); cpu->ChangePrivilegeMode(cpu->Cpsr & 0x1F);
LOAD_NZCVT; LOAD_NZCVT;
} else { } else {
if (CurrentModeHasSPSR) { if (cpu->CurrentModeHasSPSR()) {
mask = byte_mask & (UserMask | PrivMask | StateMask); mask = byte_mask & (UserMask | PrivMask | StateMask);
cpu->Spsr_copy = (cpu->Spsr_copy & ~mask) | (operand & mask); cpu->Spsr_copy = (cpu->Spsr_copy & ~mask) | (operand & mask);
} }
@ -2545,7 +2544,7 @@ MVN_INST : {
RD = ~SHIFTER_OPERAND; RD = ~SHIFTER_OPERAND;
if (inst_cream->S && (inst_cream->Rd == 15)) { if (inst_cream->S && (inst_cream->Rd == 15)) {
if (CurrentModeHasSPSR) { if (cpu->CurrentModeHasSPSR()) {
cpu->Cpsr = cpu->Spsr_copy; cpu->Cpsr = cpu->Spsr_copy;
cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F); cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F);
LOAD_NZCVT; LOAD_NZCVT;
@ -2578,7 +2577,7 @@ ORR_INST : {
RD = lop | rop; RD = lop | rop;
if (inst_cream->S && (inst_cream->Rd == 15)) { if (inst_cream->S && (inst_cream->Rd == 15)) {
if (CurrentModeHasSPSR) { if (cpu->CurrentModeHasSPSR()) {
cpu->Cpsr = cpu->Spsr_copy; cpu->Cpsr = cpu->Spsr_copy;
cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F); cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F);
LOAD_NZCVT; LOAD_NZCVT;
@ -2832,7 +2831,7 @@ RSB_INST : {
RD = AddWithCarry(~rn_val, SHIFTER_OPERAND, 1, &carry, &overflow); RD = AddWithCarry(~rn_val, SHIFTER_OPERAND, 1, &carry, &overflow);
if (inst_cream->S && (inst_cream->Rd == 15)) { if (inst_cream->S && (inst_cream->Rd == 15)) {
if (CurrentModeHasSPSR) { if (cpu->CurrentModeHasSPSR()) {
cpu->Cpsr = cpu->Spsr_copy; cpu->Cpsr = cpu->Spsr_copy;
cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F); cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F);
LOAD_NZCVT; LOAD_NZCVT;
@ -2866,7 +2865,7 @@ RSC_INST : {
RD = AddWithCarry(~rn_val, SHIFTER_OPERAND, cpu->CFlag, &carry, &overflow); RD = AddWithCarry(~rn_val, SHIFTER_OPERAND, cpu->CFlag, &carry, &overflow);
if (inst_cream->S && (inst_cream->Rd == 15)) { if (inst_cream->S && (inst_cream->Rd == 15)) {
if (CurrentModeHasSPSR) { if (cpu->CurrentModeHasSPSR()) {
cpu->Cpsr = cpu->Spsr_copy; cpu->Cpsr = cpu->Spsr_copy;
cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F); cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F);
LOAD_NZCVT; LOAD_NZCVT;
@ -3008,7 +3007,7 @@ SBC_INST : {
RD = AddWithCarry(rn_val, ~SHIFTER_OPERAND, cpu->CFlag, &carry, &overflow); RD = AddWithCarry(rn_val, ~SHIFTER_OPERAND, cpu->CFlag, &carry, &overflow);
if (inst_cream->S && (inst_cream->Rd == 15)) { if (inst_cream->S && (inst_cream->Rd == 15)) {
if (CurrentModeHasSPSR) { if (cpu->CurrentModeHasSPSR()) {
cpu->Cpsr = cpu->Spsr_copy; cpu->Cpsr = cpu->Spsr_copy;
cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F); cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F);
LOAD_NZCVT; LOAD_NZCVT;
@ -3835,7 +3834,7 @@ SUB_INST : {
RD = AddWithCarry(rn_val, ~SHIFTER_OPERAND, 1, &carry, &overflow); RD = AddWithCarry(rn_val, ~SHIFTER_OPERAND, 1, &carry, &overflow);
if (inst_cream->S && (inst_cream->Rd == 15)) { if (inst_cream->S && (inst_cream->Rd == 15)) {
if (CurrentModeHasSPSR) { if (cpu->CurrentModeHasSPSR()) {
cpu->Cpsr = cpu->Spsr_copy; cpu->Cpsr = cpu->Spsr_copy;
cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F); cpu->ChangePrivilegeMode(cpu->Spsr_copy & 0x1F);
LOAD_NZCVT; LOAD_NZCVT;

4
src/core/arm/skyeye_common/armstate.h
View File

@ -178,6 +178,10 @@ public:
bool InAPrivilegedMode() const { bool InAPrivilegedMode() const {
return (Mode != USER32MODE); return (Mode != USER32MODE);
} }
// Whether or not the current CPU mode has a Saved Program Status Register
bool CurrentModeHasSPSR() const {
return Mode != SYSTEM32MODE && InAPrivilegedMode();
}
// Note that for the 3DS, a Thumb instruction will only ever be // Note that for the 3DS, a Thumb instruction will only ever be
// two bytes in size. Thus we don't need to worry about ThumbEE // two bytes in size. Thus we don't need to worry about ThumbEE
// or Thumb-2 where instructions can be 4 bytes in length. // or Thumb-2 where instructions can be 4 bytes in length.