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https://github.com/citra-emu/citra.git
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Move the shader epilogue into the jitted shader as well.
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parent
4f802f8d26
commit
8b48a9a0ae
@ -67,9 +67,6 @@ MICROPROFILE_DEFINE(GPU_VertexShader, "GPU", "Vertex Shader", MP_RGB(50, 50, 240
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OutputVertex Run(UnitState<false>& state, const InputVertex& input, int num_attributes) {
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OutputVertex Run(UnitState<false>& state, const InputVertex& input, int num_attributes) {
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MICROPROFILE_SCOPE(GPU_VertexShader);
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MICROPROFILE_SCOPE(GPU_VertexShader);
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state.debug.max_offset = 0;
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state.debug.max_opdesc_id = 0;
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// Setup output data
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// Setup output data
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OutputVertex ret;
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OutputVertex ret;
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@ -79,6 +76,9 @@ OutputVertex Run(UnitState<false>& state, const InputVertex& input, int num_attr
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} else
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} else
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#endif // ARCHITECTURE_x86_64
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#endif // ARCHITECTURE_x86_64
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{
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{
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state.debug.max_offset = 0;
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state.debug.max_opdesc_id = 0;
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auto& config = g_state.regs.vs;
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auto& config = g_state.regs.vs;
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// Setup input register table
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// Setup input register table
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state.program_counter = config.main_offset;
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state.program_counter = config.main_offset;
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@ -105,43 +105,43 @@ OutputVertex Run(UnitState<false>& state, const InputVertex& input, int num_attr
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if (num_attributes > 15) state.registers.input[attribute_register_map.attribute15_register] = input.attr[15];
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if (num_attributes > 15) state.registers.input[attribute_register_map.attribute15_register] = input.attr[15];
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RunInterpreter(state);
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RunInterpreter(state);
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}
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// TODO(neobrain): Under some circumstances, up to 16 attributes may be output. We need to
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// TODO(neobrain): Under some circumstances, up to 16 attributes may be output. We need to
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// figure out what those circumstances are and enable the remaining outputs then.
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// figure out what those circumstances are and enable the remaining outputs then.
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unsigned index = 0;
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unsigned index = 0;
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for (unsigned i = 0; i < 7; ++i) {
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for (unsigned i = 0; i < 7; ++i) {
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if (index >= g_state.regs.vs_output_total)
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if (index >= g_state.regs.vs_output_total)
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break;
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break;
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if ((g_state.regs.vs.output_mask & (1 << i)) == 0)
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if ((g_state.regs.vs.output_mask & (1 << i)) == 0)
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continue;
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continue;
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const auto& output_register_map = g_state.regs.vs_output_attributes[index]; // TODO: Don't hardcode VS here
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const auto& output_register_map = g_state.regs.vs_output_attributes[index]; // TODO: Don't hardcode VS here
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u32 semantics[4] = {
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u32 semantics[4] = {
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output_register_map.map_x, output_register_map.map_y,
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output_register_map.map_x, output_register_map.map_y,
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output_register_map.map_z, output_register_map.map_w
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output_register_map.map_z, output_register_map.map_w
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};
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};
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for (unsigned comp = 0; comp < 4; ++comp) {
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for (unsigned comp = 0; comp < 4; ++comp) {
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float24* out = ((float24*)&ret) + semantics[comp];
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float24* out = ((float24*)&ret) + semantics[comp];
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if (semantics[comp] != Regs::VSOutputAttributes::INVALID) {
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if (semantics[comp] != Regs::VSOutputAttributes::INVALID) {
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*out = state.registers.output[i][comp];
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*out = state.registers.output[i][comp];
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} else {
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} else {
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// Zero output so that attributes which aren't output won't have denormals in them,
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// Zero output so that attributes which aren't output won't have denormals in them,
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// which would slow us down later.
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// which would slow us down later.
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memset(out, 0, sizeof(*out));
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memset(out, 0, sizeof(*out));
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}
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}
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}
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index++;
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}
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}
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index++;
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// The hardware takes the absolute and saturates vertex colors like this, *before* doing interpolation
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}
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for (unsigned i = 0; i < 4; ++i) {
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ret.color[i] = float24::FromFloat32(
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// The hardware takes the absolute and saturates vertex colors like this, *before* doing interpolation
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std::fmin(std::fabs(ret.color[i].ToFloat32()), 1.0f));
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for (unsigned i = 0; i < 4; ++i) {
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}
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ret.color[i] = float24::FromFloat32(
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std::fmin(std::fabs(ret.color[i].ToFloat32()), 1.0f));
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}
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}
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LOG_TRACE(HW_GPU, "Output vertex: pos(%.2f, %.2f, %.2f, %.2f), quat(%.2f, %.2f, %.2f, %.2f), "
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LOG_TRACE(HW_GPU, "Output vertex: pos(%.2f, %.2f, %.2f, %.2f), quat(%.2f, %.2f, %.2f, %.2f), "
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@ -94,7 +94,7 @@ const JitFunction instr_table[64] = {
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// purposes, as documented below:
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// purposes, as documented below:
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/// Pointer to the uniform memory
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/// Pointer to the uniform memory
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static const X64Reg UNIFORMS = R9;
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static const X64Reg UNIFORMS = R15;
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/// The two 32-bit VS address offset registers set by the MOVA instruction
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/// The two 32-bit VS address offset registers set by the MOVA instruction
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static const X64Reg ADDROFFS_REG_0 = R10;
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static const X64Reg ADDROFFS_REG_0 = R10;
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static const X64Reg ADDROFFS_REG_1 = R11;
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static const X64Reg ADDROFFS_REG_1 = R11;
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@ -109,7 +109,12 @@ static const X64Reg COND0 = R13;
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/// Result of the previous CMP instruction for the Y-component comparison
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/// Result of the previous CMP instruction for the Y-component comparison
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static const X64Reg COND1 = R14;
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static const X64Reg COND1 = R14;
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/// Pointer to the UnitState instance for the current VS unit
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/// Pointer to the UnitState instance for the current VS unit
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static const X64Reg REGISTERS = R15;
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static const X64Reg REGISTERS = ABI_PARAM1;
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// Clashes with others, but only used in epilogue.
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static const X64Reg ISCRATCH1 = RSI;
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static const X64Reg ISCRATCH2 = RDI;
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/// Pointer to the input data. Aliased over LOOPCOUNT as this is before any loops execute.
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/// Pointer to the input data. Aliased over LOOPCOUNT as this is before any loops execute.
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static const X64Reg INPUT = RSI;
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static const X64Reg INPUT = RSI;
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/// SIMD scratch register
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/// SIMD scratch register
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@ -825,7 +830,7 @@ void JitShader::Compile() {
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ABI_PushRegistersAndAdjustStack(ABI_ALL_CALLEE_SAVED, 8);
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ABI_PushRegistersAndAdjustStack(ABI_ALL_CALLEE_SAVED, 8);
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// Prologue: Scatter inputs into registers according to map
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// Prologue: Scatter inputs into registers according to map
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MOV(PTRBITS, R(REGISTERS), R(ABI_PARAM1));
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// MOV(PTRBITS, R(REGISTERS), R(ABI_PARAM1));
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MOV(PTRBITS, R(INPUT), R(ABI_PARAM2));
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MOV(PTRBITS, R(INPUT), R(ABI_PARAM2));
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for (int i = 0; i < num_attributes; i++) {
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for (int i = 0; i < num_attributes; i++) {
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MOVAPS(SCRATCH, MDisp(INPUT, i * 16));
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MOVAPS(SCRATCH, MDisp(INPUT, i * 16));
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@ -850,7 +855,50 @@ void JitShader::Compile() {
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MOVAPS(NEGBIT, MatR(RAX));
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MOVAPS(NEGBIT, MatR(RAX));
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// Call the start of the shader program.
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// Call the start of the shader program.
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CALLptr(R(ABI_PARAM3));
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CALLptr(R(ABI_PARAM3));
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// Alright, back from the program. Now we can do the epilogue.
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// Alright, back from the program. Now we can do the epilogue.
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X64Reg OUTPUT = ABI_PARAM4;
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// TODO(neobrain): Under some circumstances, up to 16 attributes may be output. We need to
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// figure out what those circumstances are and enable the remaining outputs then.
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unsigned index = 0;
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for (unsigned i = 0; i < 7; ++i) {
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if (index >= g_state.regs.vs_output_total)
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break;
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if ((g_state.regs.vs.output_mask & (1 << i)) == 0)
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continue;
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const auto& output_register_map = g_state.regs.vs_output_attributes[index];
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u32 semantics[4] = {
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output_register_map.map_x, output_register_map.map_y,
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output_register_map.map_z, output_register_map.map_w
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};
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if (semantics[1] == semantics[0] + 1 && semantics[2] == semantics[1] + 1 && semantics[3] == semantics[2] + 1) {
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MOVAPS(SCRATCH, MDisp(REGISTERS, UnitState<false>::OutputOffset(i)));
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MOVAPS(MDisp(OUTPUT, semantics[0] * 4), SCRATCH);
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} else {
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for (unsigned comp = 0; comp < 4; ++comp) {
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int outOffset = semantics[comp] * 4;
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if (semantics[comp] != Regs::VSOutputAttributes::INVALID) {
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MOV(32, R(ISCRATCH1), MDisp(REGISTERS, UnitState<false>::OutputOffset(i) + comp * 4));
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MOV(32, MDisp(OUTPUT, outOffset), R(ISCRATCH1));
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} else {
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// Zero output so that attributes which aren't output won't have denormals in them,
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// which would slow us down later.
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MOV(32, MDisp(OUTPUT, outOffset), Imm32(0));
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}
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}
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}
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index++;
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}
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// Saturate/Clamp color, specifically.
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// These effectively do an ABS.
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MOVAPS(SCRATCH, R(NEGBIT));
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ANDNPS(SCRATCH, MDisp(OUTPUT, Regs::VSOutputAttributes::Semantic::COLOR_R * 4));
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// Clamp to 1.0.
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MINPS(SCRATCH, R(ONE));
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ABI_PopRegistersAndAdjustStack(ABI_ALL_CALLEE_SAVED, 8);
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ABI_PopRegistersAndAdjustStack(ABI_ALL_CALLEE_SAVED, 8);
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RET();
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RET();
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