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tests/JitX64: Add tests for testing data processing instructions with Rd=R15

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This commit is contained in:
MerryMage 2016-03-22 03:44:36 +00:00
parent be46235efe
commit 67ed95cb7d
4 changed files with 42 additions and 7 deletions
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2
src/core/arm/dyncom/arm_dyncom_interpreter.cpp
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@ -3888,6 +3888,8 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
LOAD_NZCVT; LOAD_NZCVT;
DISPATCH: DISPATCH:
{ {
if (num_instrs >= cpu->NumInstrsToExecute) goto END;
if (!cpu->NirqSig) { if (!cpu->NirqSig) {
if (!(cpu->Cpsr & 0x80)) { if (!(cpu->Cpsr & 0x80)) {
goto END; goto END;

12
src/core/arm/jit_x64/instructions/data_processing.cpp
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@ -49,10 +49,14 @@ void JitX64::CompileDataProcessingHelper_Reverse(ArmReg Rn_index, ArmReg Rd_inde
body(tmp); body(tmp);
// TODO: Efficiency: Could implement this as a register rebind instead of needing to MOV. if (Rd_index != 15) {
reg_alloc.LockAndDirtyArm(Rd_index); // TODO: Efficiency: Could implement this as a register rebind instead of needing to MOV.
code->MOV(32, reg_alloc.ArmR(Rd_index), R(tmp)); reg_alloc.LockAndDirtyArm(Rd_index);
reg_alloc.UnlockArm(Rd_index); code->MOV(32, reg_alloc.ArmR(Rd_index), R(tmp));
reg_alloc.UnlockArm(Rd_index);
} else {
code->MOV(32, MJitStateArmPC(), R(tmp));
}
reg_alloc.UnlockTemp(tmp); reg_alloc.UnlockTemp(tmp);
} }

2
src/core/arm/jit_x64/reg_alloc.h
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@ -61,7 +61,7 @@ private:
ArmReg arm_reg = -1; ///< Only holds a valid value when state == DirtyArmReg / CleanArmReg ArmReg arm_reg = -1; ///< Only holds a valid value when state == DirtyArmReg / CleanArmReg
}; };
std::array<ArmState, 15> arm_gpr; std::array<ArmState, 16> arm_gpr;
std::array<X64State, 16> x64_gpr; std::array<X64State, 16> x64_gpr;
Gen::XEmitter* code = nullptr; Gen::XEmitter* code = nullptr;

33
src/tests/core/arm/jit_x64/fuzz_arm_data_processing.cpp
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@ -3,6 +3,7 @@
// Refer to the license.txt file included. // Refer to the license.txt file included.
#include <cstdio> #include <cstdio>
#include <cstring>
#include <random> #include <random>
#include <catch.hpp> #include <catch.hpp>
@ -217,6 +218,34 @@ TEST_CASE("Fuzz ARM data processing instructions", "[JitX64]") {
return instructions[inst_index].first | (assemble_randoms & (~instructions[inst_index].second)); return instructions[inst_index].first | (assemble_randoms & (~instructions[inst_index].second));
}; };
FuzzJit(5, 10000, instruction_select_without_R15); SECTION("short blocks") {
FuzzJit(1024, 500, instruction_select_without_R15); FuzzJit(5, 5000, instruction_select_without_R15);
}
SECTION("long blocks") {
FuzzJit(1024, 200, instruction_select_without_R15);
}
auto instruction_select_only_R15 = [&]() -> u32 {
size_t inst_index = RandInt(0, instructions.size() - 1);
u32 cond = 0xE;
// Have a one-in-twenty-five chance of actually having a cond.
if (RandInt(1, 25) == 1) {
cond = RandInt(0x0, 0xD);
}
u32 Rn = RandInt(0, 15);
u32 Rd = 15;
u32 S = 0;
u32 shifter_operand = RandInt(0, 0xFFF);
u32 assemble_randoms = (shifter_operand << 0) | (Rd << 12) | (Rn << 16) | (S << 20) | (cond << 28);
return instructions[inst_index].first | (assemble_randoms & (~instructions[inst_index].second));
};
SECTION("R15") {
FuzzJit(1, 10000, instruction_select_only_R15);
}
} }