ARM_Interface: Allow for partial invalidation of instruction cache

src/core/arm/arm_interface.h

@@ -4,6 +4,7 @@
 
 #pragma once
 
+#include <cstddef>
 #include "common/common_types.h"
 #include "core/arm/skyeye_common/arm_regformat.h"
 #include "core/arm/skyeye_common/vfp/asm_vfp.h"
@@ -41,6 +42,13 @@ public:
     /// Clear all instruction cache
     virtual void ClearInstructionCache() = 0;
 
+    /**
+     * Invalidate the code cache at a range of addresses.
+     * @param start_address The starting address of the range to invalidate.
+     * @param length The length (in bytes) of the range to invalidate.
+     */
+    virtual void InvalidateCacheRange(u32 start_address, size_t length) = 0;
+
     /**
      * Set the Program Counter to an address
      * @param addr Address to set PC to

src/core/arm/dynarmic/arm_dynarmic.cpp

@@ -176,3 +176,7 @@ void ARM_Dynarmic::PrepareReschedule() {
 void ARM_Dynarmic::ClearInstructionCache() {
     jit->ClearCache();
 }
+
+void ARM_Dynarmic::InvalidateCacheRange(u32 start_address, size_t length) {
+    jit->InvalidateCacheRange(start_address, length);
+}

src/core/arm/dynarmic/arm_dynarmic.h

@@ -36,6 +36,7 @@ public:
     void ExecuteInstructions(int num_instructions) override;
 
     void ClearInstructionCache() override;
+    void InvalidateCacheRange(u32 start_address, size_t length) override;
 
 private:
     std::unique_ptr<Dynarmic::Jit> jit;

src/core/arm/dyncom/arm_dyncom.cpp

@@ -25,6 +25,11 @@ void ARM_DynCom::ClearInstructionCache() {
     trans_cache_buf_top = 0;
 }
 
+void ARM_DynCom::InvalidateCacheRange(u32, size_t) {
+    // Just clear the whole cache, we don't gain much from partial invalidations.
+    ClearInstructionCache();
+}
+
 void ARM_DynCom::SetPC(u32 pc) {
     state->Reg[15] = pc;
 }

src/core/arm/dyncom/arm_dyncom.h

@@ -16,6 +16,7 @@ public:
     ~ARM_DynCom();
 
     void ClearInstructionCache() override;
+    void InvalidateCacheRange(u32 start_address, size_t length) override;
 
     void SetPC(u32 pc) override;
     u32 GetPC() const override;