mirror of
https://github.com/citra-emu/citra.git
synced 2024-11-25 02:30:15 +00:00
Fix the callstack widget by keeping track of branches
Co-opts the interpreter to create a callstack, by checking for branches and returns from branches.
This commit is contained in:
parent
784c5539ea
commit
644e457a62
@ -7,69 +7,27 @@
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#include "citra_qt/debugger/callstack.h"
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#include "citra_qt/debugger/callstack.h"
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#include "common/common_types.h"
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#include "common/common_types.h"
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#include "common/symbols.h"
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#include "core/core.h"
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#include "core/core.h"
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#include "core/memory.h"
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#include "core/arm/arm_interface.h"
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#include "core/arm/arm_interface.h"
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#include "core/arm/disassembler/arm_disasm.h"
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CallstackWidget::CallstackWidget(QWidget* parent): QDockWidget(parent)
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CallstackWidget::CallstackWidget(QWidget* parent): QDockWidget(parent)
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{
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{
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ui.setupUi(this);
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ui.setupUi(this);
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callstack_model = new QStandardItemModel(this);
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callstack_model = new QStandardItemModel(this);
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callstack_model->setColumnCount(4);
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callstack_model->setColumnCount(1);
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callstack_model->setHeaderData(0, Qt::Horizontal, "Stack Pointer");
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callstack_model->setHeaderData(0, Qt::Horizontal, "Caller address");
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callstack_model->setHeaderData(2, Qt::Horizontal, "Return Address");
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callstack_model->setHeaderData(1, Qt::Horizontal, "Call Address");
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callstack_model->setHeaderData(3, Qt::Horizontal, "Function");
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ui.treeView->setModel(callstack_model);
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ui.treeView->setModel(callstack_model);
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}
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}
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void CallstackWidget::OnDebugModeEntered()
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void CallstackWidget::OnDebugModeEntered()
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{
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{
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// Stack pointer
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const u32 sp = Core::g_app_core->GetReg(13);
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Clear();
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Clear();
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int counter = 0;
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std::vector<u32> stack_trace = Core::g_app_core->GetStackTrace();
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for (u32 addr = 0x10000000; addr >= sp; addr -= 4)
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for (auto entry : stack_trace) {
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{
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callstack_model->setItem(callstack_model->rowCount(), new QStandardItem(QString("0x%1").arg(entry, 8, 16, QLatin1Char('0'))));
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const u32 ret_addr = Memory::Read32(addr);
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const u32 call_addr = ret_addr - 4; //get call address???
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if (Memory::GetPointer(call_addr) == nullptr)
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break;
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/* TODO (mattvail) clean me, move to debugger interface */
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u32 insn = Memory::Read32(call_addr);
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if (ARM_Disasm::Decode(insn) == OP_BL)
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{
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std::string name;
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// ripped from disasm
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u8 cond = (insn >> 28) & 0xf;
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u32 i_offset = insn & 0xffffff;
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// Sign-extend the 24-bit offset
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if ((i_offset >> 23) & 1)
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i_offset |= 0xff000000;
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// Pre-compute the left-shift and the prefetch offset
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i_offset <<= 2;
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i_offset += 8;
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const u32 func_addr = call_addr + i_offset;
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callstack_model->setItem(counter, 0, new QStandardItem(QString("0x%1").arg(addr, 8, 16, QLatin1Char('0'))));
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callstack_model->setItem(counter, 1, new QStandardItem(QString("0x%1").arg(ret_addr, 8, 16, QLatin1Char('0'))));
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callstack_model->setItem(counter, 2, new QStandardItem(QString("0x%1").arg(call_addr, 8, 16, QLatin1Char('0'))));
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name = Symbols::HasSymbol(func_addr) ? Symbols::GetSymbol(func_addr).name : "unknown";
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callstack_model->setItem(counter, 3, new QStandardItem(QString("%1_%2").arg(QString::fromStdString(name))
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.arg(QString("0x%1").arg(func_addr, 8, 16, QLatin1Char('0')))));
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counter++;
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}
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}
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}
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}
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}
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@ -80,9 +38,5 @@ void CallstackWidget::OnDebugModeLeft()
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void CallstackWidget::Clear()
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void CallstackWidget::Clear()
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{
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{
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for (int row = 0; row < callstack_model->rowCount(); row++) {
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callstack_model->removeRows(0, callstack_model->rowCount());
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for (int column = 0; column < callstack_model->columnCount(); column++) {
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callstack_model->setItem(row, column, new QStandardItem());
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}
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}
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}
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}
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@ -4,6 +4,8 @@
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#pragma once
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#pragma once
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#include <vector>
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#include "common/common_types.h"
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#include "common/common_types.h"
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#include "core/arm/skyeye_common/arm_regformat.h"
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#include "core/arm/skyeye_common/arm_regformat.h"
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@ -111,6 +113,8 @@ public:
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*/
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*/
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virtual void SetCP15Register(CP15Register reg, u32 value) = 0;
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virtual void SetCP15Register(CP15Register reg, u32 value) = 0;
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virtual std::vector<u32> GetStackTrace() const = 0;
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/**
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/**
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* Advance the CPU core by the specified number of ticks (e.g. to simulate CPU execution time)
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* Advance the CPU core by the specified number of ticks (e.g. to simulate CPU execution time)
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* @param ticks Number of ticks to advance the CPU core
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* @param ticks Number of ticks to advance the CPU core
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@ -72,6 +72,10 @@ void ARM_DynCom::SetCP15Register(CP15Register reg, u32 value) {
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state->CP15[reg] = value;
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state->CP15[reg] = value;
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}
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}
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std::vector<u32> ARM_DynCom::GetStackTrace() const {
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return state->stack_trace;
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}
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void ARM_DynCom::AddTicks(u64 ticks) {
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void ARM_DynCom::AddTicks(u64 ticks) {
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down_count -= ticks;
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down_count -= ticks;
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if (down_count < 0)
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if (down_count < 0)
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@ -89,12 +93,15 @@ void ARM_DynCom::ExecuteInstructions(int num_instructions) {
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}
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}
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void ARM_DynCom::ResetContext(Core::ThreadContext& context, u32 stack_top, u32 entry_point, u32 arg) {
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void ARM_DynCom::ResetContext(Core::ThreadContext& context, u32 stack_top, u32 entry_point, u32 arg) {
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memset(&context, 0, sizeof(Core::ThreadContext));
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context = Core::ThreadContext();
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context.cpu_registers[0] = arg;
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context.cpu_registers[0] = arg;
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context.pc = entry_point;
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context.pc = entry_point;
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context.sp = stack_top;
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context.sp = stack_top;
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context.cpsr = 0x1F; // Usermode
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context.cpsr = 0x1F; // Usermode
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context.stack_trace.clear();
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context.stack_trace.reserve(128);
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}
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}
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void ARM_DynCom::SaveContext(Core::ThreadContext& ctx) {
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void ARM_DynCom::SaveContext(Core::ThreadContext& ctx) {
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@ -108,6 +115,8 @@ void ARM_DynCom::SaveContext(Core::ThreadContext& ctx) {
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ctx.fpscr = state->VFP[1];
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ctx.fpscr = state->VFP[1];
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ctx.fpexc = state->VFP[2];
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ctx.fpexc = state->VFP[2];
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ctx.stack_trace = state->stack_trace;
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}
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}
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void ARM_DynCom::LoadContext(const Core::ThreadContext& ctx) {
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void ARM_DynCom::LoadContext(const Core::ThreadContext& ctx) {
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@ -121,6 +130,8 @@ void ARM_DynCom::LoadContext(const Core::ThreadContext& ctx) {
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state->VFP[1] = ctx.fpscr;
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state->VFP[1] = ctx.fpscr;
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state->VFP[2] = ctx.fpexc;
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state->VFP[2] = ctx.fpexc;
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state->stack_trace = ctx.stack_trace;
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}
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}
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void ARM_DynCom::PrepareReschedule() {
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void ARM_DynCom::PrepareReschedule() {
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@ -33,6 +33,7 @@ public:
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void SetCPSR(u32 cpsr) override;
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void SetCPSR(u32 cpsr) override;
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u32 GetCP15Register(CP15Register reg) override;
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u32 GetCP15Register(CP15Register reg) override;
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void SetCP15Register(CP15Register reg, u32 value) override;
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void SetCP15Register(CP15Register reg, u32 value) override;
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std::vector<u32> GetStackTrace() const override;
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void AddTicks(u64 ticks) override;
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void AddTicks(u64 ticks) override;
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@ -3816,6 +3816,11 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
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#define CurrentModeHasSPSR (cpu->Mode != SYSTEM32MODE) && (cpu->Mode != USER32MODE)
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#define CurrentModeHasSPSR (cpu->Mode != SYSTEM32MODE) && (cpu->Mode != USER32MODE)
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#define PC (cpu->Reg[15])
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#define PC (cpu->Reg[15])
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#define PUSH_STACK_TRACE \
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cpu->stack_trace.emplace_back(cpu->Reg[15])
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#define UPDATE_STACK_TRACE \
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if (cpu->stack_trace.size() > 0 && cpu->stack_trace.back() == PC - cpu->GetInstructionSize()) \
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cpu->stack_trace.pop_back()
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// GCC and Clang have a C++ extension to support a lookup table of labels. Otherwise, fallback
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// GCC and Clang have a C++ extension to support a lookup table of labels. Otherwise, fallback
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// to a clunky switch statement.
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// to a clunky switch statement.
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@ -3867,6 +3872,8 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
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else
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else
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cpu->Reg[15] &= 0xfffffffc;
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cpu->Reg[15] &= 0xfffffffc;
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UPDATE_STACK_TRACE;
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// Find the cached instruction cream, otherwise translate it...
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// Find the cached instruction cream, otherwise translate it...
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auto itr = cpu->instruction_cache.find(cpu->Reg[15]);
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auto itr = cpu->instruction_cache.find(cpu->Reg[15]);
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if (itr != cpu->instruction_cache.end()) {
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if (itr != cpu->instruction_cache.end()) {
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@ -3993,6 +4000,7 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
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if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) {
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if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) {
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bbl_inst *inst_cream = (bbl_inst *)inst_base->component;
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bbl_inst *inst_cream = (bbl_inst *)inst_base->component;
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if (inst_cream->L) {
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if (inst_cream->L) {
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PUSH_STACK_TRACE;
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LINK_RTN_ADDR;
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LINK_RTN_ADDR;
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}
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}
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SET_PC;
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SET_PC;
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@ -4049,6 +4057,8 @@ unsigned InterpreterMainLoop(ARMul_State* cpu) {
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{
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{
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blx_inst *inst_cream = (blx_inst *)inst_base->component;
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blx_inst *inst_cream = (blx_inst *)inst_base->component;
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if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) {
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if ((inst_base->cond == ConditionCode::AL) || CondPassed(cpu, inst_base->cond)) {
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PUSH_STACK_TRACE;
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unsigned int inst = inst_cream->inst;
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unsigned int inst = inst_cream->inst;
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if (BITS(inst, 20, 27) == 0x12 && BITS(inst, 4, 7) == 0x3) {
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if (BITS(inst, 20, 27) == 0x12 && BITS(inst, 4, 7) == 0x3) {
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cpu->Reg[14] = (cpu->Reg[15] + cpu->GetInstructionSize());
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cpu->Reg[14] = (cpu->Reg[15] + cpu->GetInstructionSize());
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@ -18,6 +18,7 @@
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#pragma once
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#pragma once
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#include <array>
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#include <array>
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#include <vector>
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#include <unordered_map>
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#include <unordered_map>
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#include "common/common_types.h"
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#include "common/common_types.h"
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@ -239,6 +240,7 @@ public:
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// TODO(bunnei): Move this cache to a better place - it should be per codeset (likely per
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// TODO(bunnei): Move this cache to a better place - it should be per codeset (likely per
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// process for our purposes), not per ARMul_State (which tracks CPU core state).
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// process for our purposes), not per ARMul_State (which tracks CPU core state).
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std::unordered_map<u32, int> instruction_cache;
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std::unordered_map<u32, int> instruction_cache;
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std::vector<u32> stack_trace;
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private:
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private:
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void ResetMPCoreCP15Registers();
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void ResetMPCoreCP15Registers();
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#pragma once
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#pragma once
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#include <memory>
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#include <memory>
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#include <vector>
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#include "common/common_types.h"
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#include "common/common_types.h"
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class ARM_Interface;
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class ARM_Interface;
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@ -22,6 +24,8 @@ struct ThreadContext {
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u32 fpu_registers[64];
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u32 fpu_registers[64];
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u32 fpscr;
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u32 fpscr;
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u32 fpexc;
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u32 fpexc;
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std::vector<u32> stack_trace;
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};
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};
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extern std::unique_ptr<ARM_Interface> g_app_core; ///< ARM11 application core
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extern std::unique_ptr<ARM_Interface> g_app_core; ///< ARM11 application core
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