mirror of
https://github.com/citra-emu/citra.git
synced 2024-11-22 17:50:05 +00:00
dyncom: Move CP15 register reading into its own function.
Keeps everything contained. Added all supported readable registers in an ARM11 MPCore.
This commit is contained in:
Lioncash
parent
de6eba0288
commit
5e5954c63b
@ -3697,6 +3697,7 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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#undef RS
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#define CRn inst_cream->crn
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#define OPCODE_1 inst_cream->opcode_1
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#define OPCODE_2 inst_cream->opcode_2
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#define CRm inst_cream->crm
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#define CP15_REG(n) cpu->CP15[CP15(n)]
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@ -4922,50 +4923,8 @@ unsigned InterpreterMainLoop(ARMul_State* state) {
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CITRA_IGNORE_EXIT(-1);
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goto END;
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} else {
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if (inst_cream->cp_num == 15) {
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if(CRn == 0 && OPCODE_2 == 0 && CRm == 0) {
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RD = cpu->CP15[CP15(CP15_MAIN_ID)];
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} else if (CRn == 0 && CRm == 0 && OPCODE_2 == 1) {
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RD = cpu->CP15[CP15(CP15_CACHE_TYPE)];
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} else if (CRn == 1 && CRm == 0 && OPCODE_2 == 0) {
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RD = cpu->CP15[CP15(CP15_CONTROL)];
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} else if (CRn == 1 && CRm == 0 && OPCODE_2 == 1) {
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RD = cpu->CP15[CP15(CP15_AUXILIARY_CONTROL)];
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} else if (CRn == 1 && CRm == 0 && OPCODE_2 == 2) {
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RD = cpu->CP15[CP15(CP15_COPROCESSOR_ACCESS_CONTROL)];
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} else if (CRn == 2 && CRm == 0 && OPCODE_2 == 0) {
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RD = cpu->CP15[CP15(CP15_TRANSLATION_BASE_TABLE_0)];
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} else if (CRn == 2 && CRm == 0 && OPCODE_2 == 1) {
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RD = cpu->CP15[CP15(CP15_TRANSLATION_BASE_TABLE_1)];
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} else if (CRn == 2 && CRm == 0 && OPCODE_2 == 2) {
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RD = cpu->CP15[CP15(CP15_TRANSLATION_BASE_CONTROL)];
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} else if (CRn == 3 && CRm == 0 && OPCODE_2 == 0) {
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RD = cpu->CP15[CP15(CP15_DOMAIN_ACCESS_CONTROL)];
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} else if (CRn == 5 && CRm == 0 && OPCODE_2 == 0) {
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RD = cpu->CP15[CP15(CP15_FAULT_STATUS)];
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} else if (CRn == 5 && CRm == 0 && OPCODE_2 == 1) {
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RD = cpu->CP15[CP15(CP15_INSTR_FAULT_STATUS)];
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} else if (CRn == 6 && CRm == 0 && OPCODE_2 == 0) {
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RD = cpu->CP15[CP15(CP15_FAULT_ADDRESS)];
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} else if (CRn == 13) {
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if(OPCODE_2 == 0) {
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RD = CP15_REG(CP15_PID);
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} else if(OPCODE_2 == 1) {
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RD = CP15_REG(CP15_CONTEXT_ID);
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} else if (OPCODE_2 == 2) {
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RD = CP15_REG(CP15_THREAD_UPRW);
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} else if(OPCODE_2 == 3) {
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RD = Memory::KERNEL_MEMORY_VADDR;
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} else if (OPCODE_2 == 4) {
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if (InAPrivilegedMode(cpu))
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RD = CP15_REG(CP15_THREAD_PRW);
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} else {
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LOG_ERROR(Core_ARM11, "mmu_mrr wrote UNKNOWN - reg %d", CRn);
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}
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} else {
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LOG_ERROR(Core_ARM11, "mrc CRn=%d, CRm=%d, OP2=%d is not implemented", CRn, CRm, OPCODE_2);
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}
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}
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if (inst_cream->cp_num == 15)
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RD = ReadCP15Register(cpu, CRn, OPCODE_1, CRm, OPCODE_2);
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}
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}
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cpu->Reg[15] += GET_INST_SIZE(cpu);
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@ -15,7 +15,9 @@
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
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#include "core/mem_map.h"
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#include "core/arm/skyeye_common/armdefs.h"
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#include "core/arm/skyeye_common/arm_regformat.h"
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// Unsigned sum of absolute difference
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u8 ARMul_UnsignedAbsoluteDifference(u8 left, u8 right)
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@ -213,3 +215,197 @@ bool InAPrivilegedMode(ARMul_State* cpu)
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{
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return (cpu->Mode != USER32MODE);
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}
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// Reads from the CP15 registers. Used with implementation of the MRC instruction.
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// Note that since the 3DS does not have the hypervisor extensions, these registers
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// are not implemented.
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u32 ReadCP15Register(ARMul_State* cpu, u32 crn, u32 opcode_1, u32 crm, u32 opcode_2)
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{
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// Unprivileged registers
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if (crn == 13 && opcode_1 == 0 && crm == 0)
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{
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if (opcode_2 == 2)
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return cpu->CP15[CP15(CP15_THREAD_UPRW)];
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// TODO: Whenever TLS is implemented, this should return
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// "cpu->CP15[CP15(CP15_THREAD_URO)];"
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// which contains the address of the 0x200-byte TLS
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if (opcode_2 == 3)
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return Memory::KERNEL_MEMORY_VADDR;
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}
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if (InAPrivilegedMode(cpu))
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{
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if (crn == 0 && opcode_1 == 0)
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{
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if (crm == 0)
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{
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if (opcode_2 == 0)
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return cpu->CP15[CP15(CP15_MAIN_ID)];
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if (opcode_2 == 1)
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return cpu->CP15[CP15(CP15_CACHE_TYPE)];
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if (opcode_2 == 3)
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return cpu->CP15[CP15(CP15_TLB_TYPE)];
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if (opcode_2 == 5)
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return cpu->CP15[CP15(CP15_CPU_ID)];
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}
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else if (crm == 1)
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{
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if (opcode_2 == 0)
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return cpu->CP15[CP15(CP15_PROCESSOR_FEATURE_0)];
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if (opcode_2 == 1)
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return cpu->CP15[CP15(CP15_PROCESSOR_FEATURE_1)];
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if (opcode_2 == 2)
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return cpu->CP15[CP15(CP15_DEBUG_FEATURE_0)];
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if (opcode_2 == 4)
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return cpu->CP15[CP15(CP15_MEMORY_MODEL_FEATURE_0)];
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if (opcode_2 == 5)
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return cpu->CP15[CP15(CP15_MEMORY_MODEL_FEATURE_1)];
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if (opcode_2 == 6)
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return cpu->CP15[CP15(CP15_MEMORY_MODEL_FEATURE_2)];
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if (opcode_2 == 7)
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return cpu->CP15[CP15(CP15_MEMORY_MODEL_FEATURE_3)];
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}
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else if (crm == 2)
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{
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if (opcode_2 == 0)
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return cpu->CP15[CP15(CP15_ISA_FEATURE_0)];
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if (opcode_2 == 1)
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return cpu->CP15[CP15(CP15_ISA_FEATURE_1)];
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if (opcode_2 == 2)
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return cpu->CP15[CP15(CP15_ISA_FEATURE_2)];
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if (opcode_2 == 3)
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return cpu->CP15[CP15(CP15_ISA_FEATURE_3)];
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if (opcode_2 == 4)
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return cpu->CP15[CP15(CP15_ISA_FEATURE_4)];
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}
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}
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if (crn == 1 && opcode_1 == 0 && crm == 0)
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{
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if (opcode_2 == 0)
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return cpu->CP15[CP15(CP15_CONTROL)];
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if (opcode_2 == 1)
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return cpu->CP15[CP15(CP15_AUXILIARY_CONTROL)];
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if (opcode_2 == 2)
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return cpu->CP15[CP15(CP15_COPROCESSOR_ACCESS_CONTROL)];
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}
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if (crn == 2 && opcode_1 == 0 && crm == 0)
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{
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if (opcode_2 == 0)
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return cpu->CP15[CP15(CP15_TRANSLATION_BASE_TABLE_0)];
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if (opcode_2 == 1)
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return cpu->CP15[CP15(CP15_TRANSLATION_BASE_TABLE_1)];
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if (opcode_2 == 2)
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return cpu->CP15[CP15(CP15_TRANSLATION_BASE_CONTROL)];
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}
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if (crn == 3 && opcode_1 == 0 && crm == 0 && opcode_2 == 0)
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return cpu->CP15[CP15(CP15_DOMAIN_ACCESS_CONTROL)];
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if (crn == 5 && opcode_1 == 0 && crm == 0)
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{
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if (opcode_2 == 0)
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return cpu->CP15[CP15(CP15_FAULT_STATUS)];
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if (opcode_2 == 1)
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return cpu->CP15[CP15(CP15_INSTR_FAULT_STATUS)];
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}
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if (crn == 6 && opcode_1 == 0 && crm == 0)
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{
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if (opcode_2 == 0)
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return cpu->CP15[CP15(CP15_FAULT_ADDRESS)];
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if (opcode_2 == 1)
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return cpu->CP15[CP15(CP15_WFAR)];
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}
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if (crn == 7 && opcode_1 == 0 && crm == 4 && opcode_2 == 0)
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return cpu->CP15[CP15(CP15_PHYS_ADDRESS)];
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if (crn == 9 && opcode_1 == 0 && crm == 0 && opcode_2 == 0)
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return cpu->CP15[CP15(CP15_DATA_CACHE_LOCKDOWN)];
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if (crn == 10 && opcode_1 == 0)
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{
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if (crm == 0 && opcode_2 == 0)
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return cpu->CP15[CP15(CP15_TLB_LOCKDOWN)];
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if (crm == 2)
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{
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if (opcode_2 == 0)
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return cpu->CP15[CP15(CP15_PRIMARY_REGION_REMAP)];
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if (opcode_2 == 1)
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return cpu->CP15[CP15(CP15_NORMAL_REGION_REMAP)];
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}
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}
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if (crn == 13 && crm == 0)
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{
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if (opcode_2 == 0)
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return cpu->CP15[CP15(CP15_PID)];
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if (opcode_2 == 1)
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return cpu->CP15[CP15(CP15_CONTEXT_ID)];
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if (opcode_2 == 4)
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return cpu->CP15[CP15(CP15_THREAD_PRW)];
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}
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if (crn == 15)
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{
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if (opcode_1 == 0 && crm == 12)
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{
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if (opcode_2 == 0)
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return cpu->CP15[CP15(CP15_PERFORMANCE_MONITOR_CONTROL)];
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if (opcode_2 == 1)
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return cpu->CP15[CP15(CP15_CYCLE_COUNTER)];
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if (opcode_2 == 2)
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return cpu->CP15[CP15(CP15_COUNT_0)];
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if (opcode_2 == 3)
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return cpu->CP15[CP15(CP15_COUNT_1)];
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}
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if (opcode_1 == 5 && opcode_2 == 2)
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{
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if (crm == 5)
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return cpu->CP15[CP15(CP15_MAIN_TLB_LOCKDOWN_VIRT_ADDRESS)];
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if (crm == 6)
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return cpu->CP15[CP15(CP15_MAIN_TLB_LOCKDOWN_PHYS_ADDRESS)];
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if (crm == 7)
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return cpu->CP15[CP15(CP15_MAIN_TLB_LOCKDOWN_ATTRIBUTE)];
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}
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if (opcode_1 == 7 && crm == 1 && opcode_2 == 0)
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return cpu->CP15[CP15(CP15_TLB_DEBUG_CONTROL)];
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}
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}
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LOG_ERROR(Core_ARM11, "MRC CRn=%u, CRm=%u, OP1=%u OP2=%u is not implemented. Returning zero.", crn, crm, opcode_1, opcode_2);
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return 0;
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}
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@ -50,6 +50,8 @@ enum {
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EXCLUSIVE_TAG,
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EXCLUSIVE_STATE,
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EXCLUSIVE_RESULT,
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// c0 - Information registers
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CP15_BASE,
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CP15_C0 = CP15_BASE,
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CP15_C0_C0 = CP15_C0,
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@ -57,15 +59,30 @@ enum {
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CP15_CACHE_TYPE,
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CP15_TCM_STATUS,
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CP15_TLB_TYPE,
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CP15_CPU_ID,
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CP15_C0_C1,
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CP15_PROCESSOR_FEATURE_0 = CP15_C0_C1,
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CP15_PROCESSOR_FEATURE_1,
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CP15_DEBUG_FEATURE_0,
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CP15_AUXILIARY_FEATURE_0,
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CP15_MEMORY_MODEL_FEATURE_0,
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CP15_MEMORY_MODEL_FEATURE_1,
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CP15_MEMORY_MODEL_FEATURE_2,
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CP15_MEMORY_MODEL_FEATURE_3,
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CP15_C0_C2,
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CP15_ISA_FEATURE_0 = CP15_C0_C2,
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CP15_ISA_FEATURE_1,
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CP15_ISA_FEATURE_2,
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CP15_ISA_FEATURE_3,
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CP15_ISA_FEATURE_4,
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// c1 - Control registers
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CP15_C1_C0,
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CP15_CONTROL = CP15_C1_C0,
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CP15_AUXILIARY_CONTROL,
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CP15_COPROCESSOR_ACCESS_CONTROL,
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// c2 - Translation table registers
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CP15_C2,
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CP15_C2_C0 = CP15_C2,
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CP15_TRANSLATION_BASE = CP15_C2_C0,
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@ -74,24 +91,54 @@ enum {
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CP15_TRANSLATION_BASE_CONTROL,
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CP15_DOMAIN_ACCESS_CONTROL,
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CP15_RESERVED,
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/* Fault status */
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// c5 - Fault status registers
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CP15_FAULT_STATUS,
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CP15_INSTR_FAULT_STATUS,
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CP15_COMBINED_DATA_FSR = CP15_FAULT_STATUS,
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CP15_INST_FSR,
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/* Fault Address register */
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// c6 - Fault Address registers
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CP15_FAULT_ADDRESS,
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CP15_COMBINED_DATA_FAR = CP15_FAULT_ADDRESS,
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CP15_WFAR,
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CP15_IFAR,
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// c7 - Cache operation registers
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CP15_PHYS_ADDRESS,
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// c9 - Data cache lockdown register
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CP15_DATA_CACHE_LOCKDOWN,
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// c10 - TLB/Memory map registers
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CP15_TLB_LOCKDOWN,
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CP15_PRIMARY_REGION_REMAP,
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CP15_NORMAL_REGION_REMAP,
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// c13 - Thread related registers
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CP15_PID,
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CP15_CONTEXT_ID,
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CP15_THREAD_UPRW, // Thread ID register - User/Privileged Read/Write
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CP15_THREAD_URO, // Thread ID register - User Read Only (Privileged R/W)
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CP15_THREAD_PRW, // Thread ID register - Privileged R/W only.
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CP15_TLB_FAULT_ADDR, /* defined by SkyEye */
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CP15_TLB_FAULT_STATUS, /* defined by SkyEye */
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/* VFP registers */
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// c15 - Performance and TLB lockdown registers
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CP15_PERFORMANCE_MONITOR_CONTROL,
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CP15_CYCLE_COUNTER,
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CP15_COUNT_0,
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CP15_COUNT_1,
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CP15_READ_MAIN_TLB_LOCKDOWN_ENTRY,
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CP15_WRITE_MAIN_TLB_LOCKDOWN_ENTRY,
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CP15_MAIN_TLB_LOCKDOWN_VIRT_ADDRESS,
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CP15_MAIN_TLB_LOCKDOWN_PHYS_ADDRESS,
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CP15_MAIN_TLB_LOCKDOWN_ATTRIBUTE,
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CP15_TLB_DEBUG_CONTROL,
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// Skyeye defined
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CP15_TLB_FAULT_ADDR,
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CP15_TLB_FAULT_STATUS,
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// VFP registers
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VFP_BASE,
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VFP_FPSID = VFP_BASE,
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VFP_FPSCR,
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@ -358,3 +358,5 @@ extern u32 ARMul_UnsignedSatQ(s32, u8, bool*);
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extern bool InBigEndianMode(ARMul_State*);
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extern bool InAPrivilegedMode(ARMul_State*);
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extern u32 ReadCP15Register(ARMul_State* cpu, u32 crn, u32 opcode_1, u32 crm, u32 opcode_2);
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