mirror of
https://github.com/citra-emu/citra.git
synced 2024-11-30 09:30:05 +00:00
optimized threading
This commit is contained in:
parent
07ff3527a0
commit
502f0c991b
@ -14,7 +14,7 @@
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namespace Common {
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namespace Common {
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class ThreadPool {
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class ThreadPool : NonCopyable {
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private:
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private:
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explicit ThreadPool(unsigned int num_threads) :
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explicit ThreadPool(unsigned int num_threads) :
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num_threads(num_threads),
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num_threads(num_threads),
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@ -4,6 +4,7 @@
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#include <array>
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#include <array>
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#include <cstddef>
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#include <cstddef>
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#include <future>
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#include <memory>
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#include <memory>
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#include <utility>
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#include <utility>
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#include "common/assert.h"
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#include "common/assert.h"
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@ -278,6 +279,7 @@ static void WritePicaReg(u32 id, u32 value, u32 mask) {
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case PICA_REG_INDEX(pipeline.trigger_draw):
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case PICA_REG_INDEX(pipeline.trigger_draw):
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case PICA_REG_INDEX(pipeline.trigger_draw_indexed): {
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case PICA_REG_INDEX(pipeline.trigger_draw_indexed): {
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MICROPROFILE_SCOPE(GPU_Drawing);
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MICROPROFILE_SCOPE(GPU_Drawing);
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const bool is_indexed = (id == PICA_REG_INDEX(pipeline.trigger_draw_indexed));
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#if PICA_LOG_TEV
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#if PICA_LOG_TEV
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DebugUtils::DumpTevStageConfig(regs.GetTevStages());
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DebugUtils::DumpTevStageConfig(regs.GetTevStages());
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@ -285,49 +287,47 @@ static void WritePicaReg(u32 id, u32 value, u32 mask) {
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if (g_debug_context)
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if (g_debug_context)
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g_debug_context->OnEvent(DebugContext::Event::IncomingPrimitiveBatch, nullptr);
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g_debug_context->OnEvent(DebugContext::Event::IncomingPrimitiveBatch, nullptr);
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struct CachedVertex {
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explicit CachedVertex() : batch(0), lock{ ATOMIC_FLAG_INIT } {}
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CachedVertex(const CachedVertex& other) : CachedVertex() {}
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union {
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Shader::AttributeBuffer output_attr; // GS used
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Shader::OutputVertex output_vertex; // No GS
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};
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std::atomic<u32> batch;
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std::atomic_flag lock;
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};
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static std::vector<CachedVertex> vs_output(0x10000);
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if (!is_indexed && vs_output.size() < regs.pipeline.num_vertices)
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vs_output.resize(regs.pipeline.num_vertices);
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// used as a mean to invalidate data from the previous batch without clearing it
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static u32 batch_id = std::numeric_limits<u32>::max();
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++batch_id;
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if (batch_id == 0) { // reset cache when id overflows for safety
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++batch_id;
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for (auto& entry : vs_output)
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entry.batch = 0;
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}
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// Processes information about internal vertex attributes to figure out how a vertex is
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// Processes information about internal vertex attributes to figure out how a vertex is
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// loaded.
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// loaded.
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// Later, these can be compiled and cached.
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// Later, these can be compiled and cached.
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const u32 base_address = regs.pipeline.vertex_attributes.GetPhysicalBaseAddress();
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const u32 base_address = regs.pipeline.vertex_attributes.GetPhysicalBaseAddress();
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VertexLoader loader(regs.pipeline);
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VertexLoader loader(regs.pipeline);
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// Load vertices
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bool is_indexed = (id == PICA_REG_INDEX(pipeline.trigger_draw_indexed));
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const auto& index_info = regs.pipeline.index_array;
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const auto& index_info = regs.pipeline.index_array;
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const u8* index_address_8 = Memory::GetPhysicalPointer(base_address + index_info.offset);
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const u8* index_address_8 = Memory::GetPhysicalPointer(base_address + index_info.offset);
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const u16* index_address_16 = reinterpret_cast<const u16*>(index_address_8);
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const u16* index_address_16 = reinterpret_cast<const u16*>(index_address_8);
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bool index_u16 = index_info.format != 0;
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bool index_u16 = index_info.format != 0;
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struct CacheEntry {
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auto VertexIndex = [&](unsigned int index) {
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Shader::AttributeBuffer output_attr;
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// Indexed rendering doesn't use the start offset
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Shader::OutputVertex output_vertex;
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return is_indexed ? (index_u16 ? index_address_16[index] : index_address_8[index])
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std::atomic<u32> id;
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: (index + regs.pipeline.vertex_offset);
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std::atomic_flag writing{ ATOMIC_FLAG_INIT }; // Set when a thread is writing into this entry
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};
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};
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static std::array<CacheEntry, 0x10000> cache;
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// used as a mean to invalidate data from the previous batch without clearing it
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static u32 cache_batch_id = std::numeric_limits<u32>::max();
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++cache_batch_id;
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if (cache_batch_id == 0) { // reset cache if the emu ever runs long enough to overflow id
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++cache_batch_id;
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for (auto& entry : cache)
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entry.id = 0;
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}
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struct VsOutput {
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explicit VsOutput() = default;
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VsOutput(VsOutput&& other) { batch_id = 0; }
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Pica::Shader::OutputVertex vertex;
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std::atomic<u32> batch_id;
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};
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static std::vector<VsOutput> vs_output;
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while (vs_output.size() < regs.pipeline.num_vertices) {
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vs_output.emplace_back();
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}
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PrimitiveAssembler<Shader::OutputVertex>& primitive_assembler = g_state.primitive_assembler;
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PrimitiveAssembler<Shader::OutputVertex>& primitive_assembler = g_state.primitive_assembler;
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@ -345,146 +345,135 @@ static void WritePicaReg(u32 id, u32 value, u32 mask) {
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}
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}
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}
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}
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DebugUtils::MemoryAccessTracker memory_accesses;
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auto* shader_engine = Shader::GetEngine();
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auto* shader_engine = Shader::GetEngine();
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shader_engine->SetupBatch(g_state.vs, regs.vs.main_offset);
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shader_engine->SetupBatch(g_state.vs, regs.vs.main_offset);
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const bool use_gs = regs.pipeline.use_gs == PipelineRegs::UseGS::Yes;
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g_state.geometry_pipeline.Reconfigure();
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g_state.geometry_pipeline.Reconfigure();
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g_state.geometry_pipeline.Setup(shader_engine);
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g_state.geometry_pipeline.Setup(shader_engine);
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if (g_state.geometry_pipeline.NeedIndexInput())
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if (g_state.geometry_pipeline.NeedIndexInput())
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ASSERT(is_indexed);
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ASSERT(is_indexed);
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auto UnitLoop = [&](bool single_thread,
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auto VSUnitLoop = [&](u32 thread_id, auto num_threads) {
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u32 index_start,
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constexpr bool single_thread = std::is_same_v<std::integral_constant<u32, 1>, decltype(num_threads)>;
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u32 index_end) {
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DebugUtils::MemoryAccessTracker memory_accesses;
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Shader::UnitState shader_unit;
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Shader::UnitState shader_unit;
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for (unsigned int index = index_start; index < index_end; ++index) {
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for (unsigned int index = thread_id; index < regs.pipeline.num_vertices; index += num_threads) {
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// Indexed rendering doesn't use the start offset
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unsigned int vertex = VertexIndex(index);
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unsigned int vertex =
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auto& cached_vertex = vs_output[is_indexed ? vertex : index];
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is_indexed ? (index_u16 ? index_address_16[index] : index_address_8[index])
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: (index + regs.pipeline.vertex_offset);
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// -1 is a common special value used for primitive restart. Since it's unknown if
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// -1 is a common special value used for primitive restart. Since it's unknown if
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// the PICA supports it, and it would mess up the caching, guard against it here.
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// the PICA supports it, and it would mess up the caching, guard against it here.
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ASSERT(vertex != -1);
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ASSERT(vertex != -1);
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bool vertex_cache_hit = false;
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Shader::AttributeBuffer output_attr_tmp;
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Shader::AttributeBuffer& output_attr = is_indexed ? cache[vertex].output_attr : output_attr_tmp;
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Pica::Shader::OutputVertex output_vertex_tmp;
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Pica::Shader::OutputVertex& output_vertex = is_indexed ? cache[vertex].output_vertex : output_vertex_tmp;
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if (is_indexed) {
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if (is_indexed) {
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if (single_thread && g_state.geometry_pipeline.NeedIndexInput()) {
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g_state.geometry_pipeline.SubmitIndex(vertex);
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continue;
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}
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if (g_debug_context && Pica::g_debug_context->recorder) {
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if (g_debug_context && Pica::g_debug_context->recorder) {
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int size = index_u16 ? 2 : 1;
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int size = index_u16 ? 2 : 1;
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memory_accesses.AddAccess(base_address + index_info.offset + size * index,
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memory_accesses.AddAccess(base_address + index_info.offset + size * index,
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size);
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size);
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}
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}
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if (single_thread) {
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if (!single_thread) {
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if (cache[vertex].id.load(std::memory_order_relaxed) == cache_batch_id) {
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// Try locking this vertex
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vertex_cache_hit = true;
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if (cached_vertex.lock.test_and_set(std::memory_order_acquire)) {
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// Another thread is processing this vertex
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continue;
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}
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// Vertex is not being processed and is from the correct batch
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else if (cached_vertex.batch.load(std::memory_order_acquire) == batch_id) {
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// Unlock
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cached_vertex.lock.clear(std::memory_order_release);
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continue;
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}
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}
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}
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}
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else if (cache[vertex].id.load(std::memory_order_acquire) == cache_batch_id) {
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else if (cached_vertex.batch.load(std::memory_order_relaxed) == batch_id) {
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vertex_cache_hit = true;
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continue;
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}
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// Set the "writing" flag and check its previous status
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else if (cache[vertex].writing.test_and_set(std::memory_order_acquire)) {
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// Another thread is writing into the cache, spin until it's done
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while (cache[vertex].writing.test_and_set(std::memory_order_acquire));
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cache[vertex].writing.clear(std::memory_order_release);
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vertex_cache_hit = true;
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}
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}
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}
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}
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Shader::AttributeBuffer attribute_buffer;
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Shader::AttributeBuffer& output_attr = use_gs ? cached_vertex.output_attr : attribute_buffer;
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if (!vertex_cache_hit) {
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// Initialize data for the current vertex
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// Initialize data for the current vertex
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loader.LoadVertex(base_address, index, vertex, attribute_buffer, memory_accesses);
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Shader::AttributeBuffer input;
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loader.LoadVertex(base_address, index, vertex, input, memory_accesses);
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// Send to vertex shader
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// Send to vertex shader
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if (g_debug_context)
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if (g_debug_context)
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g_debug_context->OnEvent(DebugContext::Event::VertexShaderInvocation, &input);
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g_debug_context->OnEvent(DebugContext::Event::VertexShaderInvocation, &attribute_buffer);
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shader_unit.LoadInput(regs.vs, input);
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shader_unit.LoadInput(regs.vs, attribute_buffer);
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shader_engine->Run(g_state.vs, shader_unit);
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shader_engine->Run(g_state.vs, shader_unit);
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shader_unit.WriteOutput(regs.vs, output_attr);
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shader_unit.WriteOutput(regs.vs, output_attr);
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if (!single_thread)
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if (!use_gs)
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output_vertex = Shader::OutputVertex::FromAttributeBuffer(regs.rasterizer, output_attr);
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cached_vertex.output_vertex = Shader::OutputVertex::FromAttributeBuffer(regs.rasterizer, output_attr);
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if (!single_thread) {
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cached_vertex.batch.store(batch_id, std::memory_order_release);
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if (is_indexed) {
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if (is_indexed) {
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if (single_thread) {
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cached_vertex.lock.clear(std::memory_order_release);
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cache[vertex].id.store(cache_batch_id, std::memory_order_relaxed);
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}
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else {
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cache[vertex].id.store(cache_batch_id, std::memory_order_release);
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cache[vertex].writing.clear(std::memory_order_release);
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}
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}
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}
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}
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}
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else if (is_indexed) {
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if (single_thread) {
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cached_vertex.batch.store(batch_id, std::memory_order_relaxed);
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// Send to geometry pipeline
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g_state.geometry_pipeline.SubmitVertex(output_attr);
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} else {
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vs_output[index].vertex = output_vertex;
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vs_output[index].batch_id.store(cache_batch_id, std::memory_order_release);
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}
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}
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static std::mutex dbg_mtx;
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if (!memory_accesses.ranges.empty()) {
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std::lock_guard<std::mutex> lock(dbg_mtx);
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for (auto& range : memory_accesses.ranges) {
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g_debug_context->recorder->MemoryAccessed(Memory::GetPhysicalPointer(range.first),
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range.second, range.first);
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}
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}
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}
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}
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};
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};
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constexpr unsigned int VS_UNITS = 3;
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const bool use_gs = regs.pipeline.use_gs == PipelineRegs::UseGS::Yes;
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auto& thread_pool = Common::ThreadPool::GetPool();
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auto& thread_pool = Common::ThreadPool::GetPool();
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unsigned int num_threads = use_gs ? 1 : thread_pool.total_threads();//VS_UNITS;
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std::vector<std::future<void>> futures;
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if (num_threads == 1) {
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constexpr unsigned int MIN_VERTICES_PER_THREAD = 20;
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UnitLoop(true, 0, regs.pipeline.num_vertices);
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unsigned int num_threads = regs.pipeline.num_vertices / MIN_VERTICES_PER_THREAD +
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}
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(regs.pipeline.num_vertices % MIN_VERTICES_PER_THREAD != 0);
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else {
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num_threads = std::min(num_threads, std::thread::hardware_concurrency() - 1);
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const u32 range = std::max(regs.pipeline.num_vertices / num_threads + 1, 50u);
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if (num_threads <= 1) {
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VSUnitLoop(0, std::integral_constant<u32, 1>{});
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} else {
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for (unsigned int thread_id = 0; thread_id < num_threads; ++thread_id) {
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for (unsigned int thread_id = 0; thread_id < num_threads; ++thread_id) {
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const u32 loop_start = range * thread_id;
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futures.emplace_back(thread_pool.push(VSUnitLoop, thread_id, num_threads));
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const u32 loop_end = loop_start + range;
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}
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if (loop_end >= regs.pipeline.num_vertices) {
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}
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thread_pool.push(UnitLoop, false, loop_start, regs.pipeline.num_vertices);
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break;
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for (unsigned int index = 0; index < regs.pipeline.num_vertices; ++index) {
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unsigned int vertex = VertexIndex(index);
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auto& cached_vertex = vs_output[is_indexed ? vertex : index];
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if (use_gs && is_indexed && g_state.geometry_pipeline.NeedIndexInput()) {
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g_state.geometry_pipeline.SubmitIndex(vertex);
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continue;
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}
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// Synchronize threads
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if (num_threads != 1) {
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while (cached_vertex.batch.load(std::memory_order_acquire) != batch_id) {
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std::this_thread::yield();
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}
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}
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thread_pool.push(UnitLoop, false, loop_start, loop_end);
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}
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}
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for (unsigned int index = 0; index < regs.pipeline.num_vertices; ++index) {
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while (vs_output[index].batch_id.load(std::memory_order_acquire) != cache_batch_id);
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if (use_gs) {
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using Pica::Shader::OutputVertex;
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// Send to geometry pipeline
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primitive_assembler.SubmitVertex(vs_output[index].vertex,
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g_state.geometry_pipeline.SubmitVertex(cached_vertex.output_attr);
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[] (const OutputVertex& v0,
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} else {
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const OutputVertex& v1,
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primitive_assembler.SubmitVertex(cached_vertex.output_vertex,
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const OutputVertex& v2) {
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std::bind(&std::decay_t<decltype(*VideoCore::g_renderer->Rasterizer())>::AddTriangle,
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VideoCore::g_renderer->Rasterizer()->AddTriangle(v0, v1, v2);
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VideoCore::g_renderer->Rasterizer(),
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});
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std::placeholders::_1, std::placeholders::_2, std::placeholders::_3));
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}
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}
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}
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}
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for (auto& future : futures)
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future.get();
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for (auto& range : memory_accesses.ranges) {
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g_debug_context->recorder->MemoryAccessed(Memory::GetPhysicalPointer(range.first),
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range.second, range.first);
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}
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VideoCore::g_renderer->Rasterizer()->DrawTriangles();
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VideoCore::g_renderer->Rasterizer()->DrawTriangles();
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if (g_debug_context) {
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if (g_debug_context) {
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g_debug_context->OnEvent(DebugContext::Event::FinishedPrimitiveBatch, nullptr);
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g_debug_context->OnEvent(DebugContext::Event::FinishedPrimitiveBatch, nullptr);
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}
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}
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@ -235,6 +235,8 @@ class MemoryAccessTracker {
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public:
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public:
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/// Record a particular memory access in the list
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/// Record a particular memory access in the list
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void AddAccess(u32 paddr, u32 size) {
|
void AddAccess(u32 paddr, u32 size) {
|
||||||
|
std::lock_guard<std::mutex> lock(mutex);
|
||||||
|
|
||||||
// Create new range or extend existing one
|
// Create new range or extend existing one
|
||||||
ranges[paddr] = std::max(ranges[paddr], size);
|
ranges[paddr] = std::max(ranges[paddr], size);
|
||||||
|
|
||||||
@ -242,6 +244,8 @@ public:
|
|||||||
SimplifyRanges();
|
SimplifyRanges();
|
||||||
}
|
}
|
||||||
|
|
||||||
|
std::mutex mutex;
|
||||||
|
|
||||||
/// Map of accessed ranges (mapping start address to range size)
|
/// Map of accessed ranges (mapping start address to range size)
|
||||||
std::map<u32, u32> ranges;
|
std::map<u32, u32> ranges;
|
||||||
};
|
};
|
||||||
|
Loading…
Reference in New Issue
Block a user