diff --git a/src/video_core/command_processor.cpp b/src/video_core/command_processor.cpp index 6c5c3c7cb..c5643f3f6 100644 --- a/src/video_core/command_processor.cpp +++ b/src/video_core/command_processor.cpp @@ -33,10 +33,6 @@ namespace Pica { namespace CommandProcessor { -static int float_regs_counter = 0; - -static u32 uniform_write_buffer[4]; - static int default_attr_counter = 0; static u32 default_attr_write_buffer[3]; @@ -306,9 +302,7 @@ static void WritePicaReg(u32 id, u32 value, u32 mask) { } case PICA_REG_INDEX(vs.bool_uniforms): - for (unsigned i = 0; i < 16; ++i) - g_state.vs.uniforms.b[i] = (regs.vs.bool_uniforms.Value() & (1 << i)) != 0; - + Shader::WriteUniformBoolReg(false, value); break; case PICA_REG_INDEX_WORKAROUND(vs.int_uniforms[0], 0x2b1): @@ -316,14 +310,16 @@ static void WritePicaReg(u32 id, u32 value, u32 mask) { case PICA_REG_INDEX_WORKAROUND(vs.int_uniforms[2], 0x2b3): case PICA_REG_INDEX_WORKAROUND(vs.int_uniforms[3], 0x2b4): { - int index = (id - PICA_REG_INDEX_WORKAROUND(vs.int_uniforms[0], 0x2b1)); + unsigned index = (id - PICA_REG_INDEX_WORKAROUND(vs.int_uniforms[0], 0x2b1)); auto values = regs.vs.int_uniforms[index]; - g_state.vs.uniforms.i[index] = Math::Vec4(values.x, values.y, values.z, values.w); - LOG_TRACE(HW_GPU, "Set integer uniform %d to %02x %02x %02x %02x", - index, values.x.Value(), values.y.Value(), values.z.Value(), values.w.Value()); + Shader::WriteUniformIntReg(false, index, Math::Vec4(values.x, values.y, values.z, values.w)); break; } + case PICA_REG_INDEX_WORKAROUND(vs.uniform_setup.setup, 0x2c0): + Shader::WriteUniformFloatSetupReg(false, value); + break; + case PICA_REG_INDEX_WORKAROUND(vs.uniform_setup.set_value[0], 0x2c1): case PICA_REG_INDEX_WORKAROUND(vs.uniform_setup.set_value[1], 0x2c2): case PICA_REG_INDEX_WORKAROUND(vs.uniform_setup.set_value[2], 0x2c3): @@ -333,49 +329,15 @@ static void WritePicaReg(u32 id, u32 value, u32 mask) { case PICA_REG_INDEX_WORKAROUND(vs.uniform_setup.set_value[6], 0x2c7): case PICA_REG_INDEX_WORKAROUND(vs.uniform_setup.set_value[7], 0x2c8): { - auto& uniform_setup = regs.vs.uniform_setup; - - // TODO: Does actual hardware indeed keep an intermediate buffer or does - // it directly write the values? - uniform_write_buffer[float_regs_counter++] = value; - - // Uniforms are written in a packed format such that four float24 values are encoded in - // three 32-bit numbers. We write to internal memory once a full such vector is - // written. - if ((float_regs_counter >= 4 && uniform_setup.IsFloat32()) || - (float_regs_counter >= 3 && !uniform_setup.IsFloat32())) { - float_regs_counter = 0; - - auto& uniform = g_state.vs.uniforms.f[uniform_setup.index]; - - if (uniform_setup.index > 95) { - LOG_ERROR(HW_GPU, "Invalid VS uniform index %d", (int)uniform_setup.index); - break; - } - - // NOTE: The destination component order indeed is "backwards" - if (uniform_setup.IsFloat32()) { - for (auto i : {0,1,2,3}) - uniform[3 - i] = float24::FromFloat32(*(float*)(&uniform_write_buffer[i])); - } else { - // TODO: Untested - uniform.w = float24::FromRaw(uniform_write_buffer[0] >> 8); - uniform.z = float24::FromRaw(((uniform_write_buffer[0] & 0xFF) << 16) | ((uniform_write_buffer[1] >> 16) & 0xFFFF)); - uniform.y = float24::FromRaw(((uniform_write_buffer[1] & 0xFFFF) << 8) | ((uniform_write_buffer[2] >> 24) & 0xFF)); - uniform.x = float24::FromRaw(uniform_write_buffer[2] & 0xFFFFFF); - } - - LOG_TRACE(HW_GPU, "Set uniform %x to (%f %f %f %f)", (int)uniform_setup.index, - uniform.x.ToFloat32(), uniform.y.ToFloat32(), uniform.z.ToFloat32(), - uniform.w.ToFloat32()); - - // TODO: Verify that this actually modifies the register! - uniform_setup.index.Assign(uniform_setup.index + 1); - } + Shader::WriteUniformFloatReg(false, value); break; } // Load shader program code + case PICA_REG_INDEX_WORKAROUND(vs.program.offset, 0x2cb): + Shader::WriteProgramCodeOffset(false, value); + break; + case PICA_REG_INDEX_WORKAROUND(vs.program.set_word[0], 0x2cc): case PICA_REG_INDEX_WORKAROUND(vs.program.set_word[1], 0x2cd): case PICA_REG_INDEX_WORKAROUND(vs.program.set_word[2], 0x2ce): @@ -385,12 +347,15 @@ static void WritePicaReg(u32 id, u32 value, u32 mask) { case PICA_REG_INDEX_WORKAROUND(vs.program.set_word[6], 0x2d2): case PICA_REG_INDEX_WORKAROUND(vs.program.set_word[7], 0x2d3): { - g_state.vs.program_code[regs.vs.program.offset] = value; - regs.vs.program.offset++; + Shader::WriteProgramCode(false, value); break; } // Load swizzle pattern data + case PICA_REG_INDEX_WORKAROUND(vs.swizzle_patterns.offset, 0x2d5): + Shader::WriteSwizzlePatternsOffset(false, value); + break; + case PICA_REG_INDEX_WORKAROUND(vs.swizzle_patterns.set_word[0], 0x2d6): case PICA_REG_INDEX_WORKAROUND(vs.swizzle_patterns.set_word[1], 0x2d7): case PICA_REG_INDEX_WORKAROUND(vs.swizzle_patterns.set_word[2], 0x2d8): @@ -400,8 +365,7 @@ static void WritePicaReg(u32 id, u32 value, u32 mask) { case PICA_REG_INDEX_WORKAROUND(vs.swizzle_patterns.set_word[6], 0x2dc): case PICA_REG_INDEX_WORKAROUND(vs.swizzle_patterns.set_word[7], 0x2dd): { - g_state.vs.swizzle_data[regs.vs.swizzle_patterns.offset] = value; - regs.vs.swizzle_patterns.offset++; + Shader::WriteSwizzlePatterns(false, value); break; } diff --git a/src/video_core/pica.h b/src/video_core/pica.h index 7c7ef8da1..1801ab693 100644 --- a/src/video_core/pica.h +++ b/src/video_core/pica.h @@ -1237,6 +1237,8 @@ struct Regs { } union { + u32 setup; + // Index of the next uniform to write to // TODO: ctrulib uses 8 bits for this, however that seems to yield lots of invalid indices // TODO: Maybe the uppermost index is for the geometry shader? Investigate! diff --git a/src/video_core/shader/shader.cpp b/src/video_core/shader/shader.cpp index 2e6c64b75..6d86760a4 100644 --- a/src/video_core/shader/shader.cpp +++ b/src/video_core/shader/shader.cpp @@ -163,6 +163,159 @@ DebugData ShaderSetup::ProduceDebugInfo(const InputVertex& input, int num_ return state.debug; } +bool SharedGS() { + return g_state.regs.vs_com_mode == Pica::Regs::VSComMode::Shared; +} + +void WriteUniformBoolReg(bool gs, u32 value) { + auto& setup = gs ? g_state.gs : g_state.vs; + + ASSERT(setup.uniforms.b.size() == 16); + for (unsigned i = 0; i < 16; ++i) + setup.uniforms.b[i] = (value & (1 << i)) != 0; + + // Copy for GS in shared mode + if (!gs && SharedGS()) { + WriteUniformBoolReg(true, value); + } +} + +void WriteUniformIntReg(bool gs, unsigned index, const Math::Vec4& values) { + const char* shader_type = gs ? "GS" : "VS"; + auto& setup = gs ? g_state.gs : g_state.vs; + + ASSERT(index < setup.uniforms.i.size()); + setup.uniforms.i[index] = values; + LOG_TRACE(HW_GPU, "Set %s integer uniform %d to %02x %02x %02x %02x", + shader_type, index, values.x.Value(), values.y.Value(), values.z.Value(), values.w.Value()); + + // Copy for GS in shared mode + if (!gs && SharedGS()) { + WriteUniformIntReg(true, index, values); + } +} + +void WriteUniformFloatSetupReg(bool gs, u32 value) { + auto& config = gs ? g_state.regs.gs : g_state.regs.vs; + + config.uniform_setup.setup = value; + + // Copy for GS in shared mode + if (!gs && SharedGS()) { + WriteUniformFloatSetupReg(true, value); + } +} + +void WriteUniformFloatReg(bool gs, u32 value) { + const char* shader_type = gs ? "GS" : "VS"; + auto& config = gs ? g_state.regs.gs : g_state.regs.vs; + auto& setup = gs ? g_state.gs : g_state.vs; + + auto& uniform_setup = config.uniform_setup; + auto& uniform_write_buffer = setup.uniform_write_buffer; + auto& float_regs_counter = setup.float_regs_counter; + + // TODO: Does actual hardware indeed keep an intermediate buffer or does + // it directly write the values? + uniform_write_buffer[float_regs_counter++] = value; + + // Uniforms are written in a packed format such that four float24 values are encoded in + // three 32-bit numbers. We write to internal memory once a full such vector is + // written. + if ((float_regs_counter >= 4 && uniform_setup.IsFloat32()) || + (float_regs_counter >= 3 && !uniform_setup.IsFloat32())) { + float_regs_counter = 0; + + auto& uniform = setup.uniforms.f[uniform_setup.index]; + + if (uniform_setup.index >= 96) { + LOG_ERROR(HW_GPU, "Invalid %s float uniform index %d", shader_type, (int)uniform_setup.index); + } else { + + // NOTE: The destination component order indeed is "backwards" + if (uniform_setup.IsFloat32()) { + for (auto i : {0,1,2,3}) + uniform[3 - i] = float24::FromFloat32(*(float*)(&uniform_write_buffer[i])); + } else { + // TODO: Untested + uniform.w = float24::FromRaw(uniform_write_buffer[0] >> 8); + uniform.z = float24::FromRaw(((uniform_write_buffer[0] & 0xFF) << 16) | ((uniform_write_buffer[1] >> 16) & 0xFFFF)); + uniform.y = float24::FromRaw(((uniform_write_buffer[1] & 0xFFFF) << 8) | ((uniform_write_buffer[2] >> 24) & 0xFF)); + uniform.x = float24::FromRaw(uniform_write_buffer[2] & 0xFFFFFF); + } + + LOG_TRACE(HW_GPU, "Set %s float uniform %x to (%f %f %f %f)", shader_type, (int)uniform_setup.index, + uniform.x.ToFloat32(), uniform.y.ToFloat32(), uniform.z.ToFloat32(), + uniform.w.ToFloat32()); + + // TODO: Verify that this actually modifies the register! + uniform_setup.index.Assign(uniform_setup.index + 1); + } + + } + + // Copy for GS in shared mode + if (!gs && SharedGS()) { + WriteUniformFloatReg(true, value); + } +} + +void WriteProgramCodeOffset(bool gs, u32 value) { + auto& config = gs ? g_state.regs.gs : g_state.regs.vs; + config.program.offset = value; + + // Copy for GS in shared mode + if (!gs && SharedGS()) { + WriteProgramCodeOffset(true, value); + } +} + +void WriteProgramCode(bool gs, u32 value) { + const char* shader_type = gs ? "GS" : "VS"; + auto& config = gs ? g_state.regs.gs : g_state.regs.vs; + auto& setup = gs ? g_state.gs : g_state.vs; + + if (config.program.offset >= setup.program_code.size()) { + LOG_ERROR(HW_GPU, "Invalid %s program offset %d", shader_type, (int)config.program.offset); + } else { + setup.program_code[config.program.offset] = value; + config.program.offset++; + } + + // Copy for GS in shared mode + if (!gs && SharedGS()) { + WriteProgramCode(true, value); + } +} + +void WriteSwizzlePatternsOffset(bool gs, u32 value) { + auto& config = gs ? g_state.regs.gs : g_state.regs.vs; + config.swizzle_patterns.offset = value; + + // Copy for GS in shared mode + if (!gs && SharedGS()) { + WriteSwizzlePatternsOffset(true, value); + } +} + +void WriteSwizzlePatterns(bool gs, u32 value) { + const char* shader_type = gs ? "GS" : "VS"; + auto& config = gs ? g_state.regs.gs : g_state.regs.vs; + auto& setup = gs ? g_state.gs : g_state.vs; + + if (config.swizzle_patterns.offset >= setup.swizzle_data.size()) { + LOG_ERROR(HW_GPU, "Invalid %s swizzle pattern offset %d", shader_type, (int)config.swizzle_patterns.offset); + } else { + setup.swizzle_data[config.swizzle_patterns.offset] = value; + config.swizzle_patterns.offset++; + } + + // Copy for GS in shared mode + if (!gs && SharedGS()) { + WriteSwizzlePatterns(true, value); + } +} + } // namespace Shader } // namespace Pica diff --git a/src/video_core/shader/shader.h b/src/video_core/shader/shader.h index e9a56c578..b0498f95f 100644 --- a/src/video_core/shader/shader.h +++ b/src/video_core/shader/shader.h @@ -355,6 +355,9 @@ struct ShaderSetup { } } + int float_regs_counter = 0; + u32 uniform_write_buffer[4]; + std::array program_code; std::array swizzle_data; @@ -388,6 +391,16 @@ struct ShaderSetup { }; +bool SharedGS(); +void WriteUniformBoolReg(bool gs, u32 value); +void WriteUniformIntReg(bool gs, unsigned index, const Math::Vec4& values); +void WriteUniformFloatSetupReg(bool gs, u32 value); +void WriteUniformFloatReg(bool gs, u32 value); +void WriteProgramCodeOffset(bool gs, u32 value); +void WriteProgramCode(bool gs, u32 value); +void WriteSwizzlePatternsOffset(bool gs, u32 value); +void WriteSwizzlePatterns(bool gs, u32 value); + } // namespace Shader } // namespace Pica