diff --git a/src/core/arm/jit_x64/jit_x64.cpp b/src/core/arm/jit_x64/jit_x64.cpp index aab4829fa..d35da5b31 100644 --- a/src/core/arm/jit_x64/jit_x64.cpp +++ b/src/core/arm/jit_x64/jit_x64.cpp @@ -171,4 +171,18 @@ Gen::OpArg JitX64::MJitStateVFlag() { return Gen::MDisp(reg_alloc.JitStateReg(), offsetof(JitState, cpu_state) + offsetof(ARMul_State, VFlag)); } +Gen::OpArg JitX64::MJitStateExclusiveTag() { + static_assert(std::is_same::value, "JitState::cpu_state must be ARMul_State"); + static_assert(std::is_same::value, "exclusive_tag must be u32"); + + return Gen::MDisp(reg_alloc.JitStateReg(), offsetof(JitState, cpu_state) + offsetof(ARMul_State, exclusive_tag)); +} + +Gen::OpArg JitX64::MJitStateExclusiveState() { + static_assert(std::is_same::value, "JitState::cpu_state must be ARMul_State"); + static_assert(std::is_same::value, "exclusive_state must be bool"); + + return Gen::MDisp(reg_alloc.JitStateReg(), offsetof(JitState, cpu_state) + offsetof(ARMul_State, exclusive_state)); +} + } diff --git a/src/core/arm/jit_x64/jit_x64.h b/src/core/arm/jit_x64/jit_x64.h index fe4d3bb4e..9262d7913 100644 --- a/src/core/arm/jit_x64/jit_x64.h +++ b/src/core/arm/jit_x64/jit_x64.h @@ -82,6 +82,8 @@ private: Gen::OpArg MJitStateCFlag(); Gen::OpArg MJitStateNFlag(); Gen::OpArg MJitStateVFlag(); + Gen::OpArg MJitStateExclusiveTag(); + Gen::OpArg MJitStateExclusiveState(); private: struct CondManager { diff --git a/src/core/arm/skyeye_common/armstate.h b/src/core/arm/skyeye_common/armstate.h index d42ff2669..39777055c 100644 --- a/src/core/arm/skyeye_common/armstate.h +++ b/src/core/arm/skyeye_common/armstate.h @@ -240,7 +240,6 @@ public: // process for our purposes), not per ARMul_State (which tracks CPU core state). std::unordered_map instruction_cache; -private: void ResetMPCoreCP15Registers(); // Defines a reservation granule of 2 words, which protects the first 2 words starting at the tag.