From 32d81463cf35e506e2809aaf9bc4a272ff008430 Mon Sep 17 00:00:00 2001 From: MerryMage Date: Sat, 2 Apr 2016 15:27:24 +0100 Subject: [PATCH] fixup! Fix non-MSVC builds --- src/core/arm/disassembler/arm_disasm.cpp | 2 +- src/core/arm/jit_x64/instructions/data_processing.cpp | 2 +- src/core/arm/jit_x64/instructions/load_store.cpp | 2 +- src/tests/core/arm/jit_x64/fuzz_arm_common.cpp | 2 +- src/tests/core/arm/jit_x64/fuzz_thumb.cpp | 2 +- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/core/arm/disassembler/arm_disasm.cpp b/src/core/arm/disassembler/arm_disasm.cpp index f8c3f6895..240f55bde 100644 --- a/src/core/arm/disassembler/arm_disasm.cpp +++ b/src/core/arm/disassembler/arm_disasm.cpp @@ -519,7 +519,7 @@ std::string ARM_Disasm::DisassembleBLX(u32 insn) if ((insn & 0xFE000000) == 0xFA000000) { u32 imm24 = insn & 0xFFFFFF; u32 H = (insn >> 24) & 1; - s32 offset = MathUtil::SignExtend<26, s32>(imm24 << 2 + H << 1) + 8; + s32 offset = MathUtil::SignExtend<26, s32>((imm24 << 2) + (H << 1)) + 8; return Common::StringFromFormat("blx\t#+%d", offset); } else if ((insn & 0x0FFFFFF0) == 0x012FFF30) { u8 cond = (insn >> 28) & 0xf; diff --git a/src/core/arm/jit_x64/instructions/data_processing.cpp b/src/core/arm/jit_x64/instructions/data_processing.cpp index d27b38f5c..c9396b2ff 100644 --- a/src/core/arm/jit_x64/instructions/data_processing.cpp +++ b/src/core/arm/jit_x64/instructions/data_processing.cpp @@ -202,7 +202,7 @@ X64Reg JitX64::CompileDataProcessingHelper_rsr(ArmReg Rs_index, ShiftType shift, code->MOV(32, R(tmp), Imm32(0)); // } code->SetJumpTarget(jmp_to_end_1); - code->SetJumpTarget(jmp_to_end_1); + code->SetJumpTarget(jmp_to_end_2); code->SetJumpTarget(Rs_zero); } break; diff --git a/src/core/arm/jit_x64/instructions/load_store.cpp b/src/core/arm/jit_x64/instructions/load_store.cpp index a77620dd0..f95227725 100644 --- a/src/core/arm/jit_x64/instructions/load_store.cpp +++ b/src/core/arm/jit_x64/instructions/load_store.cpp @@ -1005,7 +1005,7 @@ static void ExecuteSTMBE(u32 start_address, u16 reg_list, JitState* jit_state) { void JitX64::STM(Cond cond, bool P, bool U, bool W, ArmReg Rn_index, ArmRegList list) { cond_manager.CompileCond((ConditionCode)cond); - ASSERT(list != 0, "UNPREDICTABLE"); + ASSERT_MSG(list != 0, "UNPREDICTABLE"); if (W && (list & (1 << Rn_index))) ASSERT_MSG((list & ((1 << Rn_index) - 1)) == 0, "UNPREDICTABLE"); diff --git a/src/tests/core/arm/jit_x64/fuzz_arm_common.cpp b/src/tests/core/arm/jit_x64/fuzz_arm_common.cpp index 2e22974e5..fb908e928 100644 --- a/src/tests/core/arm/jit_x64/fuzz_arm_common.cpp +++ b/src/tests/core/arm/jit_x64/fuzz_arm_common.cpp @@ -2,9 +2,9 @@ // Licensed under GPLv2 or any later version // Refer to the license.txt file included. +#include #include #include -#include #include #include diff --git a/src/tests/core/arm/jit_x64/fuzz_thumb.cpp b/src/tests/core/arm/jit_x64/fuzz_thumb.cpp index 969f4bf8f..ca0b45197 100644 --- a/src/tests/core/arm/jit_x64/fuzz_thumb.cpp +++ b/src/tests/core/arm/jit_x64/fuzz_thumb.cpp @@ -2,9 +2,9 @@ // Licensed under GPLv2 or any later version // Refer to the license.txt file included. +#include #include #include -#include #include