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dyncom: Remove unnecessary abort-related cruft
Both the MPCore and the ARM9 have the same data abort model (base restored), so differentiating isn't necessary.
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parent
dfb424b6d1
commit
3257d797e1
src/core/arm
@ -23,10 +23,7 @@ ARM_DynCom::ARM_DynCom(PrivilegeMode initial_mode) {
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ARMul_NewState(state.get());
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ARMul_NewState(state.get());
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ARMul_SelectProcessor(state.get(), ARM_v6_Prop | ARM_v5_Prop | ARM_v5e_Prop);
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ARMul_SelectProcessor(state.get(), ARM_v6_Prop | ARM_v5_Prop | ARM_v5e_Prop);
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state->abort_model = ABORT_BASE_RESTORED;
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state->bigendSig = LOW;
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state->bigendSig = LOW;
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state->lateabtSig = LOW;
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state->NirqSig = HIGH;
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state->NirqSig = HIGH;
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// Reset the core to initial state
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// Reset the core to initial state
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@ -37,13 +37,6 @@ enum {
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INSTCACHE = 2,
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INSTCACHE = 2,
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};
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};
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// Abort models
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enum {
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ABORT_BASE_RESTORED = 0,
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ABORT_EARLY = 1,
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ABORT_BASE_UPDATED = 2
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};
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#define VFP_REG_NUM 64
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#define VFP_REG_NUM 64
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struct ARMul_State
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struct ARMul_State
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{
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{
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@ -96,50 +89,13 @@ struct ARMul_State
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unsigned bigendSig;
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unsigned bigendSig;
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unsigned syscallSig;
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unsigned syscallSig;
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/* 2004-05-09 chy
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// For differentiating ARM core emulation.
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----------------------------------------------------------
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read ARM Architecture Reference Manual
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2.6.5 Data Abort
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There are three Abort Model in ARM arch.
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Early Abort Model: used in some ARMv3 and earlier implementations. In this
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model, base register wirteback occurred for LDC,LDM,STC,STM instructions, and
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the base register was unchanged for all other instructions. (oldest)
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Base Restored Abort Model: If a Data Abort occurs in an instruction which
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specifies base register writeback, the value in the base register is
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unchanged. (strongarm, xscale)
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Base Updated Abort Model: If a Data Abort occurs in an instruction which
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specifies base register writeback, the base register writeback still occurs.
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(arm720T)
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read PART B
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chap2 The System Control Coprocessor CP15
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2.4 Register1:control register
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L(bit 6): in some ARMv3 and earlier implementations, the abort model of the
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processor could be configured:
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0=early Abort Model Selected(now obsolete)
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1=Late Abort Model selceted(same as Base Updated Abort Model)
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on later processors, this bit reads as 1 and ignores writes.
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-------------------------------------------------------------
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So, if lateabtSig=1, then it means Late Abort Model(Base Updated Abort Model)
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if lateabtSig=0, then it means Base Restored Abort Model
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*/
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unsigned lateabtSig;
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// For differentiating ARM core emulaiton.
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bool is_v4; // Are we emulating a v4 architecture (or higher)?
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bool is_v4; // Are we emulating a v4 architecture (or higher)?
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bool is_v5; // Are we emulating a v5 architecture?
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bool is_v5; // Are we emulating a v5 architecture?
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bool is_v5e; // Are we emulating a v5e architecture?
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bool is_v5e; // Are we emulating a v5e architecture?
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bool is_v6; // Are we emulating a v6 architecture?
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bool is_v6; // Are we emulating a v6 architecture?
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bool is_v7; // Are we emulating a v7 architecture?
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bool is_v7; // Are we emulating a v7 architecture?
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// ARM_ARM A2-18
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// 0 Base Restored Abort Model, 1 the Early Abort Model, 2 Base Updated Abort Model
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int abort_model;
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// TODO(bunnei): Move this cache to a better place - it should be per codeset (likely per
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// TODO(bunnei): Move this cache to a better place - it should be per codeset (likely per
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// process for our purposes), not per ARMul_State (which tracks CPU core state).
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// process for our purposes), not per ARMul_State (which tracks CPU core state).
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std::unordered_map<u32, int> instruction_cache;
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std::unordered_map<u32, int> instruction_cache;
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